Searched refs:getSubClassWithSubReg (Results 1 – 14 of 14) sorted by relevance
| /trueos/contrib/llvm/lib/Target/X86/ |
| HD | X86RegisterInfo.h | 79 getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const;
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| HD | X86RegisterInfo.cpp | 114 X86RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, in getSubClassWithSubReg() function in X86RegisterInfo
122 return X86GenRegisterInfo::getSubClassWithSubReg(RC, Idx); in getSubClassWithSubReg()
131 A = X86GenRegisterInfo::getSubClassWithSubReg(A, X86::sub_8bit_hi); in getMatchingSuperRegClass()
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| HD | X86ISelLowering.cpp | 14450 TRI->getSubClassWithSubReg(getRegClassFor(MVT::i32), X86::sub_8bit); in EmitAtomicLoadArith()
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| /trueos/contrib/llvm/lib/CodeGen/ |
| HD | PeepholeOptimizer.cpp | 175 DstRC = TM->getRegisterInfo()->getSubClassWithSubReg(DstRC, SubIdx); in INITIALIZE_PASS_DEPENDENCY()
185 getSubClassWithSubReg(MRI->getRegClass(SrcReg), SubIdx) != 0; in INITIALIZE_PASS_DEPENDENCY()
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| HD | MachineRegisterInfo.cpp | 90 NewRC = getTargetRegisterInfo()->getSubClassWithSubReg(NewRC, SubIdx); in recomputeRegClass()
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| HD | MachineVerifier.cpp | 916 TRI->getSubClassWithSubReg(RC, SubIdx); in visitMachineOperand()
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| /trueos/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| HD | InstrEmitter.cpp | 442 const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx); in ConstrainForSubReg()
455 RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT), SubIdx); in ConstrainForSubReg()
548 SRC = TRI->getSubClassWithSubReg(SRC, SubIdx); in EmitSubregNode()
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| HD | FastISel.cpp | 1433 MRI.constrainRegClass(Op0, TRI.getSubClassWithSubReg(RC, Idx)); in FastEmitInst_extractsubreg()
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| /trueos/contrib/llvm/include/llvm/Target/ |
| HD | TargetRegisterInfo.h | 484 getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const { in getSubClassWithSubReg() function
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| /trueos/contrib/llvm/utils/TableGen/ |
| HD | CodeGenRegisters.h | 317 getSubClassWithSubReg(CodeGenSubRegIndex *SubIdx) const { in getSubClassWithSubReg() function
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| HD | RegisterInfoEmitter.cpp | 1248 if (CodeGenRegisterClass *SRC = RC.getSubClassWithSubReg(Idx)) in runTargetDesc()
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| HD | CodeGenRegisters.cpp | 1845 if (RC->getSubClassWithSubReg(SubIdx) != RC) in inferMatchingSuperRegClass()
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| /trueos/contrib/llvm/lib/Target/R600/ |
| HD | AMDGPUISelDAGToDAG.cpp | 132 return TM.getRegisterInfo()->getSubClassWithSubReg(SuperRC, SubRegIdx); in getOperandRegClass()
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| HD | SIISelLowering.cpp | 1015 return TRI.getSubClassWithSubReg(SuperClass, SubIdx); in getRegClassForNode()
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