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Searched refs:getNode (Results 1 – 25 of 118) sorted by relevance

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/trueos/contrib/llvm/lib/CodeGen/SelectionDAG/
HDDAGCombiner.cpp515 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(), in GetNegatedExpression()
520 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(), in GetNegatedExpression()
534 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(), in GetNegatedExpression()
545 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(), in GetNegatedExpression()
551 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(), in GetNegatedExpression()
558 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(), in GetNegatedExpression()
562 return DAG.getNode(ISD::FP_ROUND, SDLoc(Op), Op.getValueType(), in GetNegatedExpression()
601 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) in isOneUseSetCC()
616 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode); in ReassociateOps()
620 SDValue OpNode = DAG.getNode(Opc, SDLoc(N0), VT, in ReassociateOps()
[all …]
HDLegalizeVectorOps.cpp133 for (unsigned i = 0, e = Op.getNode()->getNumValues(); i != e; ++i) in TranslateLegalizeResults()
144 SDNode* Node = Op.getNode(); in LegalizeOp()
152 SDValue(DAG.UpdateNodeOperands(Op.getNode(), Ops.data(), Ops.size()), 0); in LegalizeOp()
155 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode()); in LegalizeOp()
164 StoreSDNode *ST = cast<StoreSDNode>(Op.getNode()); in LegalizeOp()
282 if (Tmp1.getNode()) { in LegalizeOp()
302 Result = DAG.UnrollVectorOp(Op.getNode()); in LegalizeOp()
323 assert(Op.getNode()->getNumValues() == 1 && in PromoteVectorOp()
331 Operands[j] = DAG.getNode(ISD::BITCAST, dl, NVT, Op.getOperand(j)); in PromoteVectorOp()
336 Op = DAG.getNode(Op.getOpcode(), dl, NVT, &Operands[0], Operands.size()); in PromoteVectorOp()
[all …]
HDLegalizeIntegerTypes.cpp143 if (Res.getNode()) in PromoteIntegerResult()
156 return DAG.getNode(ISD::AssertSext, SDLoc(N), in PromoteIntRes_AssertSext()
163 return DAG.getNode(ISD::AssertZext, SDLoc(N), in PromoteIntRes_AssertZext()
220 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp)); in PromoteIntRes_BITCAST()
224 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp)); in PromoteIntRes_BITCAST()
231 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, in PromoteIntRes_BITCAST()
245 InOp = DAG.getNode(ISD::ANY_EXTEND, dl, in PromoteIntRes_BITCAST()
249 return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp); in PromoteIntRes_BITCAST()
256 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetWidenedVector(InOp)); in PromoteIntRes_BITCAST()
259 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, in PromoteIntRes_BITCAST()
[all …]
HDLegalizeDAG.cpp174 ReplacedNode(Old.getNode()); in ReplaceNode()
324 SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val); in ExpandUnalignedStore()
365 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, in ExpandUnalignedStore()
367 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); in ExpandUnalignedStore()
390 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], in ExpandUnalignedStore()
407 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount); in ExpandUnalignedStore()
415 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, in ExpandUnalignedStore()
424 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2); in ExpandUnalignedStore()
447 SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad); in ExpandUnalignedLoad()
449 Result = DAG.getNode(VT.isFloatingPoint() ? ISD::FP_EXTEND : in ExpandUnalignedLoad()
[all …]
HDSelectionDAGBuilder.cpp136 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]); in getCopyFromParts()
137 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]); in getCopyFromParts()
143 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi); in getCopyFromParts()
157 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi); in getCopyFromParts()
158 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi, in getCopyFromParts()
161 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo); in getCopyFromParts()
162 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi); in getCopyFromParts()
169 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]); in getCopyFromParts()
170 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]); in getCopyFromParts()
173 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi); in getCopyFromParts()
[all …]
HDLegalizeTypesGeneric.cpp54 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
55 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
61 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
62 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
68 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
69 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
74 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
75 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
85 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
86 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
[all …]
HDLegalizeVectorTypes.cpp126 if (R.getNode()) in ScalarizeVectorResult()
133 return DAG.getNode(N->getOpcode(), SDLoc(N), in ScalarizeVecRes_BinOp()
141 return DAG.getNode(N->getOpcode(), SDLoc(N), in ScalarizeVecRes_TernaryOp()
153 return DAG.getNode(ISD::BITCAST, SDLoc(N), in ScalarizeVecRes_BITCAST()
163 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp); in ScalarizeVecRes_BUILD_VECTOR()
179 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), in ScalarizeVecRes_EXTRACT_SUBVECTOR()
187 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), in ScalarizeVecRes_FP_ROUND()
193 return DAG.getNode(ISD::FPOWI, SDLoc(N), in ScalarizeVecRes_FPOWI()
204 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, Op); in ScalarizeVecRes_INSERT_VECTOR_ELT()
233 return DAG.getNode(N->getOpcode(), SDLoc(N), DestVT, Op); in ScalarizeVecRes_UnaryOp()
[all …]
HDResourcePriorityQueue.cpp79 const SDNode *ScegN = PredSU->getNode(); in numberRCValPredInSU()
117 const SDNode *ScegN = SuccSU->getNode(); in numberRCValSuccInSU()
135 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); in numberRCValSuccInSU()
248 if (!SU || !SU->getNode()) in isResourceAvailable()
253 if (SU->getNode()->getGluedNode()) in isResourceAvailable()
258 if (SU->getNode()->isMachineOpcode()) in isResourceAvailable()
259 switch (SU->getNode()->getMachineOpcode()) { in isResourceAvailable()
262 SU->getNode()->getMachineOpcode()))) in isResourceAvailable()
293 if (!isResourceAvailable(SU) || SU->getNode()->getGluedNode()) { in reserveResources()
298 if (SU->getNode() && SU->getNode()->isMachineOpcode()) { in reserveResources()
[all …]
HDTargetLowering.cpp205 SDValue Tmp = DAG.getNode(ISD::SETCC, dl, in softenSetCCOperands()
210 NewLHS = DAG.getNode(ISD::SETCC, dl, in softenSetCCOperands()
213 NewLHS = DAG.getNode(ISD::OR, dl, Tmp.getValueType(), Tmp, NewLHS); in softenSetCCOperands()
301 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0), in ShrinkDemandedConstant()
326 assert(Op.getNode()->getNumValues() == 1 && in ShrinkDemandedOp()
331 if (!Op.getNode()->hasOneUse()) in ShrinkDemandedOp()
346 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT, in ShrinkDemandedOp()
347 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, in ShrinkDemandedOp()
348 Op.getNode()->getOperand(0)), in ShrinkDemandedOp()
349 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, in ShrinkDemandedOp()
[all …]
HDLegalizeTypes.cpp102 assert(NewVal.getNode()->getNodeId() != NewNode && in PerformExpensiveChecks()
271 if (IgnoreNodeResults(N->getOperand(i).getNode())) in run()
416 if (!IgnoreNodeResults(I->getOperand(i).getNode()) && in run()
476 if (Op.getNode()->getNodeId() == Processed) in AnalyzeNewNode()
522 Val.setNode(AnalyzeNewNode(Val.getNode())); in AnalyzeNewValue()
523 if (Val.getNode()->getNodeId() == Processed) in AnalyzeNewValue()
558 assert(I->first.getNode() != N); in ExpungeNode()
564 assert(I->first.getNode() != N); in ExpungeNode()
570 assert(I->first.getNode() != N); in ExpungeNode()
576 assert(I->first.getNode() != N); in ExpungeNode()
[all …]
/trueos/contrib/llvm/lib/Target/R600/
HDAMDILISelLowering.cpp302 DST = SDValue(Op.getNode(), 0); in LowerSDIV()
320 DST = SDValue(Op.getNode(), 0); in LowerSREM()
339 Data = DAG.getNode(ISD::ZERO_EXTEND, DL, IVT, Data); in LowerSIGN_EXTEND_INREG()
345 Data = DAG.getNode(ISD::SHL, DL, DVT, Data, Shift); in LowerSIGN_EXTEND_INREG()
347 Data = DAG.getNode(ISD::SRA, DL, DVT, Data, Shift); in LowerSIGN_EXTEND_INREG()
383 Result = DAG.getNode( in LowerBRCOND()
411 SDValue jq = DAG.getNode(ISD::XOR, DL, OVT, LHS, RHS); in LowerSDIV24()
414 jq = DAG.getNode(ISD::SRA, DL, OVT, jq, DAG.getConstant(bitsize - 2, OVT)); in LowerSDIV24()
417 jq = DAG.getNode(ISD::OR, DL, OVT, jq, DAG.getConstant(1, OVT)); in LowerSDIV24()
429 SDValue fa = DAG.getNode(ISD::SINT_TO_FP, DL, FLTTY, ia); in LowerSDIV24()
[all …]
HDAMDGPUISelLowering.cpp247 return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain); in LowerReturn()
258 Op.getNode()->dump(); in LowerOperation()
312 Args.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op), in ExtractVectorElements()
329 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), in LowerCONCAT_VECTORS()
342 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), in LowerEXTRACT_SUBVECTOR()
373 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
377 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
379 return DAG.getNode(AMDGPUISD::FMAX, DL, VT, Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
382 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
385 return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
[all …]
HDR600ISelLowering.cpp541 return DAG.getNode(AMDGPUISD::EXPORT, SDLoc(Op), Op.getValueType(), in LowerOperation()
618 return DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v2f32, in LowerOperation()
692 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, MVT::v4f32, TexArgs, 19); in LowerOperation()
696 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
698 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
700 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
702 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
704 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
706 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
708 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
[all …]
/trueos/contrib/llvm/lib/Target/Mips/
HDMipsSEISelLowering.cpp296 SDNode *ADDCNode = ADDENode->getOperand(2).getNode(); in selectMADD()
303 SDNode *MultNode = MultHi.getNode(); in selectMADD()
307 if (MultLo.getNode() != MultNode) in selectMADD()
332 SDValue ACCIn = CurDAG->getNode(MipsISD::MTLOHI, DL, MVT::Untyped, in selectMADD()
339 SDValue MAdd = CurDAG->getNode(MultOpc, DL, MVT::Untyped, in selectMADD()
346 SDValue LoOut = CurDAG->getNode(MipsISD::MFLO, DL, MVT::i32, MAdd); in selectMADD()
350 SDValue HiOut = CurDAG->getNode(MipsISD::MFHI, DL, MVT::i32, MAdd); in selectMADD()
368 SDNode *SUBCNode = SUBENode->getOperand(2).getNode(); in selectMSUB()
375 SDNode *MultNode = MultHi.getNode(); in selectMSUB()
379 if (MultLo.getNode() != MultNode) in selectMSUB()
[all …]
/trueos/contrib/llvm/lib/Target/XCore/
HDXCoreISelLowering.cpp212 case ISD::SUB: return ExpandADDSUB(Op.getNode(), DAG); in LowerOperation()
246 SDValue Cond = DAG.getNode(ISD::SETCC, dl, MVT::i32, Op.getOperand(2), in LowerSELECT_CC()
248 return DAG.getNode(ISD::SELECT, dl, MVT::i32, Cond, Op.getOperand(0), in LowerSELECT_CC()
264 return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, GA); in getGlobalAddressWrapper()
265 return DAG.getNode(XCoreISD::DPRelativeWrapper, dl, MVT::i32, GA); in getGlobalAddressWrapper()
267 return DAG.getNode(XCoreISD::PCRelativeWrapper, dl, MVT::i32, GA); in getGlobalAddressWrapper()
284 GA = DAG.getNode(ISD::ADD, DL, MVT::i32, GA, Remaining); in LowerGlobalAddress()
297 return DAG.getNode(XCoreISD::PCRelativeWrapper, DL, getPointerTy(), Result); in LowerBlockAddress()
315 return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, Res); in LowerConstantPool()
337 return DAG.getNode(XCoreISD::BR_JT, dl, MVT::Other, Chain, TargetJT, Index); in LowerBR_JT()
[all …]
/trueos/contrib/llvm/lib/Target/X86/
HDX86ISelLowering.cpp87 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT, in ExtractSubVector()
91 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, in ExtractSubVector()
138 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, in InsertSubVector()
1703 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy()); in getPICJumpTableRelocBase()
1827 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy); in LowerReturn()
1829 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy); in LowerReturn()
1831 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy); in LowerReturn()
1833 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy); in LowerReturn()
1856 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy); in LowerReturn()
1867 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy); in LowerReturn()
[all …]
HDX86ISelDAGToDAG.cpp83 IndexReg.getNode() != 0 || Base_Reg.getNode() != 0; in hasBaseOrIndexReg()
91 dyn_cast_or_null<RegisterSDNode>(Base_Reg.getNode())) in isRIPRelative()
105 if (Base_Reg.getNode() != 0) in dump()
106 Base_Reg.getNode()->dump(); in dump()
112 if (IndexReg.getNode() != 0) in dump()
113 IndexReg.getNode()->dump(); in dump()
258 if (AM.Segment.getNode()) in getAddressOperands()
366 if (Chain.getNode() == Load.getNode()) in MoveBelowOrigChain()
372 if (Chain.getOperand(i).getNode() == Load.getNode()) in MoveBelowOrigChain()
377 CurDAG->getNode(ISD::TokenFactor, SDLoc(Load), in MoveBelowOrigChain()
[all …]
/trueos/contrib/llvm/lib/Target/ARM/
HDARMISelLowering.cpp1351 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); in LowerCallResult()
1354 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64); in LowerCallResult()
1355 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, in LowerCallResult()
1366 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); in LowerCallResult()
1367 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, in LowerCallResult()
1381 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val); in LowerCallResult()
1400 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); in LowerMemOpCallTo()
1414 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl, in PassF64ArgInRegs()
1422 if (StackPtr.getNode() == 0) in PassF64ArgInRegs()
1510 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
[all …]
HDARMSelectionDAGInfo.cpp67 DAG.getNode(ISD::ADD, dl, MVT::i32, Src, in EmitTargetCodeForMemcpy()
74 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i); in EmitTargetCodeForMemcpy()
79 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst, in EmitTargetCodeForMemcpy()
85 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i); in EmitTargetCodeForMemcpy()
106 DAG.getNode(ISD::ADD, dl, MVT::i32, Src, in EmitTargetCodeForMemcpy()
115 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i); in EmitTargetCodeForMemcpy()
129 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst, in EmitTargetCodeForMemcpy()
136 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i); in EmitTargetCodeForMemcpy()
171 Src = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src); in EmitTargetCodeForMemset()
173 Src = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Src); in EmitTargetCodeForMemset()
/trueos/contrib/llvm/lib/Target/SystemZ/
HDSystemZSelectionDAGInfo.cpp49 return DAG.getNode(Loop, DL, MVT::Other, Chain, Dst, Src, in emitMemMem()
52 return DAG.getNode(Sequence, DL, MVT::Other, Chain, Dst, Src, in emitMemMem()
115 Dst = DAG.getNode(ISD::ADD, DL, PtrVT, Dst, in EmitTargetCodeForMemset()
120 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chain1, Chain2); in EmitTargetCodeForMemset()
129 SDValue Dst2 = DAG.getNode(ISD::ADD, DL, PtrVT, Dst, in EmitTargetCodeForMemset()
134 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chain1, Chain2); in EmitTargetCodeForMemset()
149 SDValue DstPlus1 = DAG.getNode(ISD::ADD, DL, PtrVT, Dst, in EmitTargetCodeForMemset()
172 return DAG.getNode(SystemZISD::CLC_LOOP, DL, VTs, Chain, Src1, Src2, in emitCLC()
175 return DAG.getNode(SystemZISD::CLC, DL, VTs, Chain, Src1, Src2, in emitCLC()
184 SDValue IPM = DAG.getNode(SystemZISD::IPM, DL, MVT::i32, Glue); in addIPMSequence()
[all …]
/trueos/contrib/llvm/lib/Target/PowerPC/
HDPPCISelLowering.cpp703 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) { in isFloatingPointZero()
905 if (UniquedVals[i&(Multiple-1)].getNode() == 0) in get_VSPLTI_elt()
920 if (UniquedVals[i].getNode() == 0) continue; // Must have been undefs. in get_VSPLTI_elt()
927 if (UniquedVals[Multiple-1].getNode() == 0) in get_VSPLTI_elt()
934 if (UniquedVals[Multiple-1].getNode() == 0) in get_VSPLTI_elt()
947 if (OpVal.getNode() == 0) in get_VSPLTI_elt()
953 if (OpVal.getNode() == 0) return SDValue(); // All UNDEF: use implicit def. in get_VSPLTI_elt()
1012 return isIntS16Immediate(Op.getNode(), Imm); in isIntS16Immediate()
1262 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode())) in getPreIndexedAddressParts()
1340 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero); in LowerLabelRef()
[all …]
/trueos/contrib/llvm/lib/Target/Sparc/
HDSparcISelLowering.cpp235 if (Flag.getNode()) in LowerReturn_32()
238 return DAG.getNode(SPISD::RET_FLAG, DL, MVT::Other, in LowerReturn_32()
276 OutVal = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
279 OutVal = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
282 OutVal = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
290 OutVal = DAG.getNode(ISD::SHL, DL, MVT::i64, OutVal, in LowerReturn_64()
296 SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, OutVals[i+1]); in LowerReturn_64()
297 OutVal = DAG.getNode(ISD::OR, DL, MVT::i64, OutVal, NV); in LowerReturn_64()
313 if (Flag.getNode()) in LowerReturn_64()
316 return DAG.getNode(SPISD::RET_FLAG, DL, MVT::Other, in LowerReturn_64()
[all …]
/trueos/contrib/llvm/lib/Target/NVPTX/
HDNVPTXISelLowering.cpp343 return DAG.getNode(NVPTXISD::Wrapper, dl, getPointerTy(), Op); in LowerGlobalAddress()
577 Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs, in LowerCall()
594 StVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, StVal); in LowerCall()
623 Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs, in LowerCall()
639 Elt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Elt); in LowerCall()
654 Elt0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Elt0); in LowerCall()
655 Elt1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Elt1); in LowerCall()
699 StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal); in LowerCall()
706 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal); in LowerCall()
718 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal); in LowerCall()
[all …]
/trueos/contrib/llvm/lib/Analysis/
HDTypeBasedAliasAnalysis.cpp151 const MDNode *getNode() const { return Node; } in getNode() function in __anon78b0dfab0111::TBAANode
189 const MDNode *getNode() const { return Node; } in getNode() function in __anon78b0dfab0111::TBAAStructTagNode
225 const MDNode *getNode() const { return Node; } in getNode() function in __anon78b0dfab0111::TBAAStructTypeNode
351 if (T.getNode() == B) in Aliases()
357 if (!T.getNode()) in Aliases()
363 if (T.getNode() == A) in Aliases()
369 if (!T.getNode()) in Aliases()
377 if (RootA.getNode() != RootB.getNode()) in Aliases()
406 if (T.getNode() == BaseB) in PathAliases()
414 if (!T.getNode()) in PathAliases()
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/trueos/contrib/llvm/lib/Target/AArch64/
HDAArch64ISelLowering.cpp1085 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN, in SaveVarArgRegisters()
1109 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN, in SaveVarArgRegisters()
1124 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, &MemOps[0], in SaveVarArgRegisters()
1192 ArgValue = DAG.getNode(ISD::BITCAST,dl, VA.getValVT(), ArgValue); in LowerFormalArguments()
1296 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerReturn()
1299 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); in LowerReturn()
1311 if (Flag.getNode()) in LowerReturn()
1314 return DAG.getNode(AArch64ISD::Ret, dl, MVT::Other, in LowerReturn()
1433 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); in LowerCall()
1465 DstAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); in LowerCall()
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