| /trueos/contrib/llvm/lib/Target/R600/ |
| HD | R600ISelLowering.cpp | 821 DAG.getCondCode(ISD::SETNE) in LowerFPTOUINT()
883 CC = DAG.getCondCode(InverseCC); in LowerSELECT_CC()
889 CC = DAG.getCondCode(SwapInvCC); in LowerSELECT_CC()
917 CC = DAG.getCondCode(CCSwapped); in LowerSELECT_CC()
925 CC = DAG.getCondCode(CCSwapped); in LowerSELECT_CC()
957 DAG.getCondCode(CCOpcode)); in LowerSELECT_CC()
990 DAG.getCondCode(ISD::SETNE)); in LowerSELECT_CC()
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| /trueos/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| HD | LegalizeFloatTypes.cpp | 684 DAG.getCondCode(CCCode), NewLHS, NewRHS, in SoftenFloatOp_BR_CC()
731 DAG.getCondCode(CCCode)), in SoftenFloatOp_SELECT_CC()
753 DAG.getCondCode(CCCode)), in SoftenFloatOp_SETCC()
1350 DAG.getCondCode(CCCode), NewLHS, NewRHS, in ExpandFloatOp_BR_CC()
1444 DAG.getCondCode(CCCode)), 0); in ExpandFloatOp_SELECT_CC()
1461 DAG.getCondCode(CCCode)), 0); in ExpandFloatOp_SETCC()
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| HD | LegalizeDAG.cpp | 1633 CC = DAG.getCondCode(InvCC); in LegalizeSetCCCondCode()
1684 CC = DAG.getCondCode(InvCC); in LegalizeSetCCCondCode()
3688 DAG.getCondCode(ISD::SETNE), Tmp3, in ExpandNode()
3784 CC = DAG.getCondCode(ISD::SETNE); in ExpandNode()
3815 Tmp4 = DAG.getCondCode(ISD::SETNE); in ExpandNode()
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| HD | LegalizeIntegerTypes.cpp | 2590 LHSHi, RHSHi, DAG.getCondCode(CCCode)); in IntegerExpandSetCCOperands()
2634 DAG.getCondCode(CCCode), NewLHS, NewRHS, in ExpandIntOp_BR_CC()
2653 DAG.getCondCode(CCCode)), 0); in ExpandIntOp_SELECT_CC()
2670 DAG.getCondCode(CCCode)), 0); in ExpandIntOp_SETCC()
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| HD | TargetLowering.cpp | 207 NewLHS, NewRHS, DAG.getCondCode(CCCode)); in softenSetCCOperands()
212 NewRHS, DAG.getCondCode(getCmpLibcallCC(LC2))); in softenSetCCOperands()
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| HD | SelectionDAG.cpp | 1332 SDValue SelectionDAG::getCondCode(ISD::CondCode Cond) { in getCondCode() function in SelectionDAG
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| /trueos/contrib/llvm/include/llvm/CodeGen/ |
| HD | SelectionDAG.h | 530 SDValue getCondCode(ISD::CondCode Cond);
665 return getNode(ISD::SETCC, DL, VT, LHS, RHS, getCondCode(Cond));
686 LHS, RHS, True, False, getCondCode(Cond));
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| /trueos/contrib/llvm/lib/Target/AArch64/ |
| HD | AArch64ISelLowering.cpp | 1865 DAG.getCondCode(CC)); in getSelectableIntSetCC()
1944 DAG.getCondCode(ISD::SETNE)); in LowerBRCOND()
1992 DAG.getCondCode(CC)); in LowerBR_CC()
2476 DAG.getCondCode(CC)); in LowerSELECT_CC()
2506 DAG.getCondCode(ISD::SETNE)); in LowerSELECT()
2599 DAG.getNode(Opcode, DL, VT, Op0, Op1, DAG.getCondCode(CC)); in LowerVectorSETCC()
2688 DAG.getNode(Opcode, DL, VT, Op0, Op1, DAG.getCondCode(ISD::SETGT)); in LowerVectorSETCC()
2697 DAG.getNode(Opcode, DL, VT, Op0, Op1, DAG.getCondCode(ISD::SETGE)); in LowerVectorSETCC()
2709 SDValue NeonCmp = DAG.getNode(Opcode, DL, VT, Op0, Op1, DAG.getCondCode(CC)); in LowerVectorSETCC()
2764 DAG.getCondCode(CC)); in LowerSETCC()
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| /trueos/contrib/llvm/lib/Target/AArch64/AsmParser/ |
| HD | AArch64AsmParser.cpp | 255 A64CC::CondCodes getCondCode() const { in getCondCode() function in __anon90ea03eb0211::AArch64Operand
943 Inst.addOperand(MCOperand::CreateImm(getCondCode())); in addCondCodeOperands()
970 unsigned Encoded = A64InvertCondCode(getCondCode()); in addInvCondCodeOperands()
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| /trueos/contrib/llvm/lib/Target/ARM/AsmParser/ |
| HD | ARMAsmParser.cpp | 552 ARMCC::CondCodes getCondCode() const { in getCondCode() function in __anon87cffc590311::ARMOperand
1540 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode()))); in addCondCodeOperands()
1541 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; in addCondCodeOperands()
1567 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode()))); in addITCondCodeOperands()
2508 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">"; in print()
4181 unsigned Cond = static_cast<ARMOperand*>(Operands[CondOp])->getCondCode(); in cvtThumbBranches()
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