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Searched refs:gen_rtx_REG (Results 1 – 25 of 63) sorted by relevance

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/trueos/contrib/gcc/config/ia64/
HDia64.c939 thread_pointer_rtx = gen_rtx_REG (Pmode, 13); in gen_thread_pointer()
1161 out[reversed] = gen_rtx_REG (DImode, REGNO (in)); in ia64_split_tmode()
1162 out[!reversed] = gen_rtx_REG (DImode, REGNO (in) + 1); in ia64_split_tmode()
1436 op1 = gen_rtx_REG (TImode, REGNO (op1)); in ia64_expand_movxf_movrf()
1438 emit_move_insn (gen_rtx_REG (TImode, REGNO (op0)), op1); in ia64_expand_movxf_movrf()
1445 emit_move_insn (gen_rtx_REG (DImode, REGNO (op0)), in ia64_expand_movxf_movrf()
1448 emit_move_insn (gen_rtx_REG (DImode, REGNO (op0) + 1), in ia64_expand_movxf_movrf()
1461 out[0] = gen_rtx_REG (DImode, REGNO (op0)); in ia64_expand_movxf_movrf()
1462 out[1] = gen_rtx_REG (DImode, REGNO (op0) + 1); in ia64_expand_movxf_movrf()
1481 rtx op1 = gen_rtx_REG (TImode, REGNO (operands[1])); in ia64_expand_movxf_movrf()
[all …]
HDia64.md258 "operands[2] = gen_rtx_REG (CCImode, REGNO (operands[0]));
259 operands[3] = gen_rtx_REG (CCImode, REGNO (operands[0]) + 1);
260 operands[4] = gen_rtx_REG (CCImode, REGNO (operands[1]));
261 operands[5] = gen_rtx_REG (CCImode, REGNO (operands[1]) + 1);")
1510 "operands[3] = gen_rtx_REG (CCImode, REGNO (operands[1]));
1511 operands[4] = gen_rtx_REG (CCImode, REGNO (operands[2]));")
3096 operands[6] = gen_rtx_REG (XFmode, REGNO (operands[0]));
3097 operands[7] = gen_rtx_REG (XFmode, REGNO (operands[1]));
3098 operands[8] = gen_rtx_REG (XFmode, REGNO (operands[2]));
3099 operands[9] = gen_rtx_REG (DFmode, REGNO (operands[0]));
[all …]
HDvect.md1252 operands[0] = gen_rtx_REG (V2SFmode, REGNO (operands[0]));
1256 operands[1] = gen_rtx_REG (SFmode, REGNO (operands[1]));
1270 operands[0] = gen_rtx_REG (V2SFmode, REGNO (operands[0]));
1272 operands[1] = gen_rtx_REG (SFmode, REGNO (operands[1]));
1285 operands[0] = gen_rtx_REG (DImode, REGNO (operands[0]));
1286 operands[1] = gen_rtx_REG (DImode, REGNO (operands[1]));
HDsync.md120 rtx ccv = gen_rtx_REG (DImode, AR_CCV_REGNUM);
HDia64.h1000 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, BR_REG (0))
1213 gen_rtx_REG (MODE, \
/trueos/contrib/gcc/config/rs6000/
HDrs6000.c3157 tlsreg = gen_rtx_REG (Pmode, 13); in rs6000_legitimize_tls_address()
3162 tlsreg = gen_rtx_REG (Pmode, 2); in rs6000_legitimize_tls_address()
3174 tlsreg = gen_rtx_REG (Pmode, 13); in rs6000_legitimize_tls_address()
3179 tlsreg = gen_rtx_REG (Pmode, 2); in rs6000_legitimize_tls_address()
3199 got = gen_rtx_REG (Pmode, 2); in rs6000_legitimize_tls_address()
3203 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM); in rs6000_legitimize_tls_address()
3238 r3 = gen_rtx_REG (Pmode, 3); in rs6000_legitimize_tls_address()
3256 r3 = gen_rtx_REG (Pmode, 3); in rs6000_legitimize_tls_address()
4875 r1 = gen_rtx_REG (DImode, gregno); in spe_build_register_parallel()
4880 r1 = gen_rtx_REG (DImode, gregno); in spe_build_register_parallel()
[all …]
/trueos/contrib/gcc/config/sparc/
HDsparc.c1113 temp = gen_rtx_REG (DImode, REGNO (temp)); in sparc_emit_set_symbolic_const64()
1195 temp = gen_rtx_REG (DImode, REGNO (temp) + 1); in sparc_emit_set_symbolic_const64()
1267 temp = gen_rtx_REG (DImode, REGNO (temp) + 1); in sparc_emit_set_symbolic_const64()
1998 cc_reg = gen_rtx_REG (mode, reg + SPARC_FIRST_V9_FCC_REG); in gen_compare_reg()
2004 cc_reg = gen_rtx_REG (mode, SPARC_FCC_REG); in gen_compare_reg()
2006 cc_reg = gen_rtx_REG (mode, SPARC_ICC_REG); in gen_compare_reg()
2147 return gen_rtx_REG (DFmode, regno); in gen_df_reg()
2634 if (reg_mentioned_p (gen_rtx_REG (Pmode, 1), pat)) in eligible_for_sibcall_delay()
2649 if (reg_mentioned_p (gen_rtx_REG (Pmode, 15), pat)) in eligible_for_sibcall_delay()
3075 o0 = gen_rtx_REG (Pmode, 8); in legitimize_tls_address()
[all …]
HDsparc.h1725 ? gen_rtx_REG (Pmode, 31) \
1736 plus_constant (gen_rtx_REG (word_mode, 15), 8)
1746 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 1) /* %g1 */
1747 #define EH_RETURN_HANDLER_RTX gen_rtx_REG (Pmode, 31) /* %i7 */
HDsparc.md4260 gen_rtx_REG (CCmode, SPARC_ICC_REG)))));
4433 gen_rtx_REG (CCmode, SPARC_ICC_REG)))));
5815 gen_rtx_REG (CCmode,
6736 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 15)))));
6743 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 15)))));
6756 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 15)))));
6762 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 15)))));
6886 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 15)));
6940 rtx valreg1 = gen_rtx_REG (DImode, 8);
6941 rtx valreg2 = gen_rtx_REG (TARGET_ARCH64 ? TFmode : DFmode, 32);
[all …]
/trueos/contrib/gcc/config/s390/
HDs390.c774 rtx cc = gen_rtx_REG (mode, CC_REGNUM); in s390_emit_compare()
1244 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM)); in s390_expand_logical_operator()
1539 rtx fake_pool_base = gen_rtx_REG (Pmode, ARG_POINTER_REGNUM); in s390_decompose_address()
2347 *lo = gen_rtx_REG (SImode, REGNO (reg) + 1); in s390_split_access_reg()
2348 *hi = gen_rtx_REG (SImode, REGNO (reg)); in s390_split_access_reg()
3128 emit_move_insn (tp, gen_rtx_REG (Pmode, TP_REGNUM)); in s390_get_thread_pointer()
3152 gen_rtx_REG (Pmode, RETURN_REGNUM)); in s390_emit_tls_call_insn()
3171 r2 = gen_rtx_REG (Pmode, 2); in legitimize_tls_address()
3194 r2 = gen_rtx_REG (Pmode, 2); in legitimize_tls_address()
3714 rtx ccreg = gen_rtx_REG (CCUmode, CC_REGNUM); in s390_expand_cmpmem()
[all …]
HDs390.h540 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, RETURN_REGNUM)
/trueos/contrib/gcc/config/mips/
HDmips.c2030 a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST); in mips_call_tls_get_addr()
2063 v0 = gen_rtx_REG (Pmode, GP_RETURN); in mips_legitimize_tls_address()
2064 v1 = gen_rtx_REG (Pmode, GP_RETURN + 1); in mips_legitimize_tls_address()
2378 emit_insn (gen_mfhilo_si (gen_rtx_REG (SImode, REGNO (dest)), in mips_legitimize_move()
2379 gen_rtx_REG (SImode, REGNO (src)), in mips_legitimize_move()
2380 gen_rtx_REG (SImode, other_regno))); in mips_legitimize_move()
2382 emit_insn (gen_mfhilo_di (gen_rtx_REG (DImode, REGNO (dest)), in mips_legitimize_move()
2383 gen_rtx_REG (DImode, REGNO (src)), in mips_legitimize_move()
2384 gen_rtx_REG (DImode, other_regno))); in mips_legitimize_move()
2779 return gen_rtx_REG (word_mode, high_p ? REGNO (op) + 1 : REGNO (op)); in mips_subword()
[all …]
HDmips.h985 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
991 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1459 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1460 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
HDmips-ps-3d.md511 = gen_rtx_REG (CCmode, REGNO (operands[2]) + INTVAL (operands[3]));
533 = gen_rtx_REG (CCmode, REGNO (operands[2]) + INTVAL (operands[3]));
/trueos/contrib/gcc/config/arm/
HDarm.c2752 return gen_rtx_REG (mode, pcum->iwmmxt_nregs + FIRST_IWMMXT_REGNUM); in arm_function_arg()
2781 return gen_rtx_REG (mode, pcum->nregs); in arm_function_arg()
3231 cfun->machine->pic_reg = gen_rtx_REG (Pmode, arm_pic_register); in legitimize_pic_address()
3462 pic_tmp = gen_rtx_REG (SImode, in arm_load_pic_register()
3883 tmp = gen_rtx_REG (SImode, 0); in arm_load_tp()
6287 emit_move_insn (gen_rtx_REG (SImode, base_regno + i), mem); in arm_gen_load_multiple()
6318 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, base_regno + j), mem); in arm_gen_load_multiple()
6350 emit_move_insn (mem, gen_rtx_REG (SImode, base_regno + i)); in arm_gen_store_multiple()
6382 = gen_rtx_SET (VOIDmode, mem, gen_rtx_REG (SImode, base_regno + j)); in arm_gen_store_multiple()
6420 part_bytes_reg = gen_rtx_REG (SImode, (in_words_to_go - 1) & 3); in arm_gen_movmemqi()
[all …]
HDlinux-elf.h103 emit_insn (gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, LR_REGNUM)))
HDarm.h804 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM)
1297 ? gen_rtx_REG (MODE, FIRST_FPA_REGNUM) \
1300 ? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \
1302 ? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \
1303 : gen_rtx_REG (MODE, ARG_REGISTER (1)))
2419 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
/trueos/contrib/gcc/
HDpostreload.c197 rtx testreg = gen_rtx_REG (VOIDmode, -1); in reload_cse_regs_1()
339 rtx wide_dest = gen_rtx_REG (word_mode, REGNO (SET_DEST (set))); in reload_cse_simplify_set()
461 gen_rtx_REG (word_mode, REGNO (SET_DEST (set))), in reload_cse_simplify_operands()
635 gen_rtx_REG (mode, op_alt_regno[i][j]), 1); in reload_cse_simplify_operands()
647 gen_rtx_REG (mode, op_alt_regno[op][j]), 1); in reload_cse_simplify_operands()
846 rtx index_reg = gen_rtx_REG (GET_MODE (reg), i); in reload_combine()
1285 rtx narrow_reg = gen_rtx_REG (narrow_mode, in reload_cse_move2add()
HDcaller-save.c162 addr_reg = gen_rtx_REG (Pmode, i); in init_caller_save()
187 test_reg = gen_rtx_REG (VOIDmode, 0); in init_caller_save()
689 gen_rtx_REG (GET_MODE (mem), in insert_restore()
761 gen_rtx_REG (GET_MODE (mem), in insert_save()
HDintegrate.c255 ivs->entries[ivs->num_entries].hard_reg = gen_rtx_REG (mode, regno); in get_hard_reg_initial_val()
HDreload.c855 dst = gen_rtx_REG (mode, regno); in can_reload_into()
1193 in = gen_rtx_REG (GET_MODE (in), subreg_regno (in)); in push_reload()
1200 out = gen_rtx_REG (GET_MODE (out), subreg_regno (out)); in push_reload()
1577 rld[i].reg_rtx = gen_rtx_REG (rel_mode, regno); in push_reload()
1864 = gen_rtx_REG (rld[output_reload].outmode, in combine_reloads()
1978 value = gen_rtx_REG (outmode, regno); in find_dummy_reload()
2043 value = gen_rtx_REG (inmode, regno); in find_dummy_reload()
4717 rtx reg = gen_rtx_REG (GET_MODE (tem), max_reg_num ()); in maybe_memory_address_p()
5400 op0 = gen_rtx_REG (word_mode, in find_reloads_address_1()
5415 op1 = gen_rtx_REG (GET_MODE (op1), in find_reloads_address_1()
[all …]
HDrtl-factoring.c705 pseq->link_reg = gen_rtx_REG (Pmode, i); in recompute_gain_for_pattern_seq()
1330 reg = gen_rtx_REG (Pmode, 0); in compute_init_costs()
HDreload1.c464 gen_rtx_REG (Pmode, in init_reload()
485 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM), in init_reload()
486 gen_rtx_REG (Pmode, i)); in init_reload()
3619 ep->from_rtx = gen_rtx_REG (Pmode, ep->from); in init_elim_table()
3620 ep->to_rtx = gen_rtx_REG (Pmode, ep->to); in init_elim_table()
5205 = gen_rtx_REG (rld[r].mode, spill_regs[i]); in set_reload_reg()
5672 ? last_reg : gen_rtx_REG (mode, i)); in choose_reload_regs()
5791 equiv = gen_rtx_REG (rld[r].mode, regno); in choose_reload_regs()
6857 old = gen_rtx_REG (mode, REGNO (reloadreg)); in emit_output_reload_insns()
7798 out = gen_rtx_REG (GET_MODE (loc), REGNO (out)); in gen_reload()
[all …]
HDfunction.c2603 rtx reg = gen_rtx_REG (mode, REGNO (entry_parm)); in assign_parm_setup_block()
2622 rtx reg = gen_rtx_REG (word_mode, REGNO (entry_parm)); in assign_parm_setup_block()
4455 emit_move_insn (gen_rtx_REG (GET_MODE (decl_rtl), in expand_function_end()
4828 base = gen_rtx_REG (Pmode, REGNO (ret_ptr)); in keep_stack_depressed()
4836 base = gen_rtx_REG (Pmode, REGNO (XEXP (ret_ptr, 0))); in keep_stack_depressed()
4877 reg = gen_rtx_REG (Pmode, regno); in keep_stack_depressed()
5066 dest = gen_rtx_REG (GET_MODE (p->equiv_reg_src), in emit_equiv_load()
/trueos/contrib/gcc/config/i386/
HDi386.c3198 tmp = gen_rtx_REG (orig_mode, regno); in gen_reg_or_parallel()
3201 tmp = gen_rtx_REG (mode, regno); in gen_reg_or_parallel()
3699 return gen_rtx_REG (mode, intreg[0]); in construct_container()
3706 return gen_rtx_REG (mode, FIRST_STACK_REG); in construct_container()
3715 return gen_rtx_REG (mode, SSE_REGNO (sse_regno)); in construct_container()
3718 return gen_rtx_REG (XFmode, FIRST_STACK_REG); in construct_container()
3723 return gen_rtx_REG (mode, intreg[0]); in construct_container()
3745 gen_rtx_REG (tmpmode, *intreg), in construct_container()
3751 gen_rtx_REG (SFmode, in construct_container()
3758 gen_rtx_REG (DFmode, in construct_container()
[all …]

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