1 /****************************************************************************** 2 3 Copyright (c) 2013-2014, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #ifndef _I40E_TYPE_H_ 36 #define _I40E_TYPE_H_ 37 38 #include "i40e_status.h" 39 #include "i40e_osdep.h" 40 #include "i40e_register.h" 41 #include "i40e_adminq.h" 42 #include "i40e_hmc.h" 43 #include "i40e_lan_hmc.h" 44 45 #define UNREFERENCED_XPARAMETER 46 47 /* Vendor ID */ 48 #define I40E_INTEL_VENDOR_ID 0x8086 49 50 /* Device IDs */ 51 #define I40E_DEV_ID_SFP_XL710 0x1572 52 #define I40E_DEV_ID_QEMU 0x1574 53 #define I40E_DEV_ID_KX_A 0x157F 54 #define I40E_DEV_ID_KX_B 0x1580 55 #define I40E_DEV_ID_KX_C 0x1581 56 #define I40E_DEV_ID_QSFP_A 0x1583 57 #define I40E_DEV_ID_QSFP_B 0x1584 58 #define I40E_DEV_ID_QSFP_C 0x1585 59 #define I40E_DEV_ID_10G_BASE_T 0x1586 60 #define I40E_DEV_ID_VF 0x154C 61 #define I40E_DEV_ID_VF_HV 0x1571 62 63 #define i40e_is_40G_device(d) ((d) == I40E_DEV_ID_QSFP_A || \ 64 (d) == I40E_DEV_ID_QSFP_B || \ 65 (d) == I40E_DEV_ID_QSFP_C) 66 67 #ifndef I40E_MASK 68 /* I40E_MASK is a macro used on 32 bit registers */ 69 #define I40E_MASK(mask, shift) (mask << shift) 70 #endif 71 72 #define I40E_MAX_PF 16 73 #define I40E_MAX_PF_VSI 64 74 #define I40E_MAX_PF_QP 128 75 #define I40E_MAX_VSI_QP 16 76 #define I40E_MAX_VF_VSI 3 77 #define I40E_MAX_CHAINED_RX_BUFFERS 5 78 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS 16 79 80 /* something less than 1 minute */ 81 #define I40E_HEARTBEAT_TIMEOUT (HZ * 50) 82 83 /* Max default timeout in ms, */ 84 #define I40E_MAX_NVM_TIMEOUT 18000 85 86 /* Check whether address is multicast. */ 87 #define I40E_IS_MULTICAST(address) (bool)(((u8 *)(address))[0] & ((u8)0x01)) 88 89 /* Check whether an address is broadcast. */ 90 #define I40E_IS_BROADCAST(address) \ 91 ((((u8 *)(address))[0] == ((u8)0xff)) && \ 92 (((u8 *)(address))[1] == ((u8)0xff))) 93 94 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */ 95 #define I40E_MS_TO_GTIME(time) ((time) * 1000) 96 97 /* forward declaration */ 98 struct i40e_hw; 99 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *); 100 101 #define I40E_ETH_LENGTH_OF_ADDRESS 6 102 /* Data type manipulation macros. */ 103 #define I40E_HI_DWORD(x) ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF)) 104 #define I40E_LO_DWORD(x) ((u32)((x) & 0xFFFFFFFF)) 105 106 #define I40E_HI_WORD(x) ((u16)(((x) >> 16) & 0xFFFF)) 107 #define I40E_LO_WORD(x) ((u16)((x) & 0xFFFF)) 108 109 #define I40E_HI_BYTE(x) ((u8)(((x) >> 8) & 0xFF)) 110 #define I40E_LO_BYTE(x) ((u8)((x) & 0xFF)) 111 112 /* Number of Transmit Descriptors must be a multiple of 8. */ 113 #define I40E_REQ_TX_DESCRIPTOR_MULTIPLE 8 114 /* Number of Receive Descriptors must be a multiple of 32 if 115 * the number of descriptors is greater than 32. 116 */ 117 #define I40E_REQ_RX_DESCRIPTOR_MULTIPLE 32 118 119 #define I40E_DESC_UNUSED(R) \ 120 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \ 121 (R)->next_to_clean - (R)->next_to_use - 1) 122 123 /* bitfields for Tx queue mapping in QTX_CTL */ 124 #define I40E_QTX_CTL_VF_QUEUE 0x0 125 #define I40E_QTX_CTL_VM_QUEUE 0x1 126 #define I40E_QTX_CTL_PF_QUEUE 0x2 127 128 /* debug masks - set these bits in hw->debug_mask to control output */ 129 enum i40e_debug_mask { 130 I40E_DEBUG_INIT = 0x00000001, 131 I40E_DEBUG_RELEASE = 0x00000002, 132 133 I40E_DEBUG_LINK = 0x00000010, 134 I40E_DEBUG_PHY = 0x00000020, 135 I40E_DEBUG_HMC = 0x00000040, 136 I40E_DEBUG_NVM = 0x00000080, 137 I40E_DEBUG_LAN = 0x00000100, 138 I40E_DEBUG_FLOW = 0x00000200, 139 I40E_DEBUG_DCB = 0x00000400, 140 I40E_DEBUG_DIAG = 0x00000800, 141 I40E_DEBUG_FD = 0x00001000, 142 143 I40E_DEBUG_AQ_MESSAGE = 0x01000000, 144 I40E_DEBUG_AQ_DESCRIPTOR = 0x02000000, 145 I40E_DEBUG_AQ_DESC_BUFFER = 0x04000000, 146 I40E_DEBUG_AQ_COMMAND = 0x06000000, 147 I40E_DEBUG_AQ = 0x0F000000, 148 149 I40E_DEBUG_USER = 0xF0000000, 150 151 I40E_DEBUG_ALL = 0xFFFFFFFF 152 }; 153 154 /* PCI Bus Info */ 155 #define I40E_PCI_LINK_STATUS 0xB2 156 #define I40E_PCI_LINK_WIDTH 0x3F0 157 #define I40E_PCI_LINK_WIDTH_1 0x10 158 #define I40E_PCI_LINK_WIDTH_2 0x20 159 #define I40E_PCI_LINK_WIDTH_4 0x40 160 #define I40E_PCI_LINK_WIDTH_8 0x80 161 #define I40E_PCI_LINK_SPEED 0xF 162 #define I40E_PCI_LINK_SPEED_2500 0x1 163 #define I40E_PCI_LINK_SPEED_5000 0x2 164 #define I40E_PCI_LINK_SPEED_8000 0x3 165 166 /* Memory types */ 167 enum i40e_memset_type { 168 I40E_NONDMA_MEM = 0, 169 I40E_DMA_MEM 170 }; 171 172 /* Memcpy types */ 173 enum i40e_memcpy_type { 174 I40E_NONDMA_TO_NONDMA = 0, 175 I40E_NONDMA_TO_DMA, 176 I40E_DMA_TO_DMA, 177 I40E_DMA_TO_NONDMA 178 }; 179 180 /* These are structs for managing the hardware information and the operations. 181 * The structures of function pointers are filled out at init time when we 182 * know for sure exactly which hardware we're working with. This gives us the 183 * flexibility of using the same main driver code but adapting to slightly 184 * different hardware needs as new parts are developed. For this architecture, 185 * the Firmware and AdminQ are intended to insulate the driver from most of the 186 * future changes, but these structures will also do part of the job. 187 */ 188 enum i40e_mac_type { 189 I40E_MAC_UNKNOWN = 0, 190 I40E_MAC_X710, 191 I40E_MAC_XL710, 192 I40E_MAC_VF, 193 I40E_MAC_GENERIC, 194 }; 195 196 enum i40e_media_type { 197 I40E_MEDIA_TYPE_UNKNOWN = 0, 198 I40E_MEDIA_TYPE_FIBER, 199 I40E_MEDIA_TYPE_BASET, 200 I40E_MEDIA_TYPE_BACKPLANE, 201 I40E_MEDIA_TYPE_CX4, 202 I40E_MEDIA_TYPE_DA, 203 I40E_MEDIA_TYPE_VIRTUAL 204 }; 205 206 enum i40e_fc_mode { 207 I40E_FC_NONE = 0, 208 I40E_FC_RX_PAUSE, 209 I40E_FC_TX_PAUSE, 210 I40E_FC_FULL, 211 I40E_FC_PFC, 212 I40E_FC_DEFAULT 213 }; 214 215 enum i40e_set_fc_aq_failures { 216 I40E_SET_FC_AQ_FAIL_NONE = 0, 217 I40E_SET_FC_AQ_FAIL_GET = 1, 218 I40E_SET_FC_AQ_FAIL_SET = 2, 219 I40E_SET_FC_AQ_FAIL_UPDATE = 4, 220 I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6 221 }; 222 223 enum i40e_vsi_type { 224 I40E_VSI_MAIN = 0, 225 I40E_VSI_VMDQ1, 226 I40E_VSI_VMDQ2, 227 I40E_VSI_CTRL, 228 I40E_VSI_FCOE, 229 I40E_VSI_MIRROR, 230 I40E_VSI_SRIOV, 231 I40E_VSI_FDIR, 232 I40E_VSI_TYPE_UNKNOWN 233 }; 234 235 enum i40e_queue_type { 236 I40E_QUEUE_TYPE_RX = 0, 237 I40E_QUEUE_TYPE_TX, 238 I40E_QUEUE_TYPE_PE_CEQ, 239 I40E_QUEUE_TYPE_UNKNOWN 240 }; 241 242 struct i40e_link_status { 243 enum i40e_aq_phy_type phy_type; 244 enum i40e_aq_link_speed link_speed; 245 u8 link_info; 246 u8 an_info; 247 u8 ext_info; 248 u8 loopback; 249 bool an_enabled; 250 /* is Link Status Event notification to SW enabled */ 251 bool lse_enable; 252 u16 max_frame_size; 253 bool crc_enable; 254 u8 pacing; 255 }; 256 257 struct i40e_phy_info { 258 struct i40e_link_status link_info; 259 struct i40e_link_status link_info_old; 260 u32 autoneg_advertised; 261 u32 phy_id; 262 u32 module_type; 263 bool get_link_info; 264 enum i40e_media_type media_type; 265 }; 266 267 #define I40E_HW_CAP_MAX_GPIO 30 268 #define I40E_HW_CAP_MDIO_PORT_MODE_MDIO 0 269 #define I40E_HW_CAP_MDIO_PORT_MODE_I2C 1 270 271 /* Capabilities of a PF or a VF or the whole device */ 272 struct i40e_hw_capabilities { 273 u32 switch_mode; 274 #define I40E_NVM_IMAGE_TYPE_EVB 0x0 275 #define I40E_NVM_IMAGE_TYPE_CLOUD 0x2 276 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3 277 278 u32 management_mode; 279 u32 npar_enable; 280 u32 os2bmc; 281 u32 valid_functions; 282 bool sr_iov_1_1; 283 bool vmdq; 284 bool evb_802_1_qbg; /* Edge Virtual Bridging */ 285 bool evb_802_1_qbh; /* Bridge Port Extension */ 286 bool dcb; 287 bool fcoe; 288 bool mfp_mode_1; 289 bool mgmt_cem; 290 bool ieee_1588; 291 bool iwarp; 292 bool fd; 293 u32 fd_filters_guaranteed; 294 u32 fd_filters_best_effort; 295 bool rss; 296 u32 rss_table_size; 297 u32 rss_table_entry_width; 298 bool led[I40E_HW_CAP_MAX_GPIO]; 299 bool sdp[I40E_HW_CAP_MAX_GPIO]; 300 u32 nvm_image_type; 301 u32 num_flow_director_filters; 302 u32 num_vfs; 303 u32 vf_base_id; 304 u32 num_vsis; 305 u32 num_rx_qp; 306 u32 num_tx_qp; 307 u32 base_queue; 308 u32 num_msix_vectors; 309 u32 num_msix_vectors_vf; 310 u32 led_pin_num; 311 u32 sdp_pin_num; 312 u32 mdio_port_num; 313 u32 mdio_port_mode; 314 u8 rx_buf_chain_len; 315 u32 enabled_tcmap; 316 u32 maxtc; 317 }; 318 319 struct i40e_mac_info { 320 enum i40e_mac_type type; 321 u8 addr[I40E_ETH_LENGTH_OF_ADDRESS]; 322 u8 perm_addr[I40E_ETH_LENGTH_OF_ADDRESS]; 323 u8 san_addr[I40E_ETH_LENGTH_OF_ADDRESS]; 324 u8 port_addr[I40E_ETH_LENGTH_OF_ADDRESS]; 325 u16 max_fcoeq; 326 }; 327 328 enum i40e_aq_resources_ids { 329 I40E_NVM_RESOURCE_ID = 1 330 }; 331 332 enum i40e_aq_resource_access_type { 333 I40E_RESOURCE_READ = 1, 334 I40E_RESOURCE_WRITE 335 }; 336 337 struct i40e_nvm_info { 338 u64 hw_semaphore_timeout; /* 2usec global time (GTIME resolution) */ 339 u64 hw_semaphore_wait; /* - || - */ 340 u32 timeout; /* [ms] */ 341 u16 sr_size; /* Shadow RAM size in words */ 342 bool blank_nvm_mode; /* is NVM empty (no FW present)*/ 343 u16 version; /* NVM package version */ 344 u32 eetrack; /* NVM data version */ 345 }; 346 347 /* definitions used in NVM update support */ 348 349 enum i40e_nvmupd_cmd { 350 I40E_NVMUPD_INVALID, 351 I40E_NVMUPD_READ_CON, 352 I40E_NVMUPD_READ_SNT, 353 I40E_NVMUPD_READ_LCB, 354 I40E_NVMUPD_READ_SA, 355 I40E_NVMUPD_WRITE_ERA, 356 I40E_NVMUPD_WRITE_CON, 357 I40E_NVMUPD_WRITE_SNT, 358 I40E_NVMUPD_WRITE_LCB, 359 I40E_NVMUPD_WRITE_SA, 360 I40E_NVMUPD_CSUM_CON, 361 I40E_NVMUPD_CSUM_SA, 362 I40E_NVMUPD_CSUM_LCB, 363 }; 364 365 enum i40e_nvmupd_state { 366 I40E_NVMUPD_STATE_INIT, 367 I40E_NVMUPD_STATE_READING, 368 I40E_NVMUPD_STATE_WRITING 369 }; 370 371 /* nvm_access definition and its masks/shifts need to be accessible to 372 * application, core driver, and shared code. Where is the right file? 373 */ 374 #define I40E_NVM_READ 0xB 375 #define I40E_NVM_WRITE 0xC 376 377 #define I40E_NVM_MOD_PNT_MASK 0xFF 378 379 #define I40E_NVM_TRANS_SHIFT 8 380 #define I40E_NVM_TRANS_MASK (0xf << I40E_NVM_TRANS_SHIFT) 381 #define I40E_NVM_CON 0x0 382 #define I40E_NVM_SNT 0x1 383 #define I40E_NVM_LCB 0x2 384 #define I40E_NVM_SA (I40E_NVM_SNT | I40E_NVM_LCB) 385 #define I40E_NVM_ERA 0x4 386 #define I40E_NVM_CSUM 0x8 387 388 #define I40E_NVM_ADAPT_SHIFT 16 389 #define I40E_NVM_ADAPT_MASK (0xffffULL << I40E_NVM_ADAPT_SHIFT) 390 391 #define I40E_NVMUPD_MAX_DATA 4096 392 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */ 393 394 struct i40e_nvm_access { 395 u32 command; 396 u32 config; 397 u32 offset; /* in bytes */ 398 u32 data_size; /* in bytes */ 399 u8 data[1]; 400 }; 401 402 /* PCI bus types */ 403 enum i40e_bus_type { 404 i40e_bus_type_unknown = 0, 405 i40e_bus_type_pci, 406 i40e_bus_type_pcix, 407 i40e_bus_type_pci_express, 408 i40e_bus_type_reserved 409 }; 410 411 /* PCI bus speeds */ 412 enum i40e_bus_speed { 413 i40e_bus_speed_unknown = 0, 414 i40e_bus_speed_33 = 33, 415 i40e_bus_speed_66 = 66, 416 i40e_bus_speed_100 = 100, 417 i40e_bus_speed_120 = 120, 418 i40e_bus_speed_133 = 133, 419 i40e_bus_speed_2500 = 2500, 420 i40e_bus_speed_5000 = 5000, 421 i40e_bus_speed_8000 = 8000, 422 i40e_bus_speed_reserved 423 }; 424 425 /* PCI bus widths */ 426 enum i40e_bus_width { 427 i40e_bus_width_unknown = 0, 428 i40e_bus_width_pcie_x1 = 1, 429 i40e_bus_width_pcie_x2 = 2, 430 i40e_bus_width_pcie_x4 = 4, 431 i40e_bus_width_pcie_x8 = 8, 432 i40e_bus_width_32 = 32, 433 i40e_bus_width_64 = 64, 434 i40e_bus_width_reserved 435 }; 436 437 /* Bus parameters */ 438 struct i40e_bus_info { 439 enum i40e_bus_speed speed; 440 enum i40e_bus_width width; 441 enum i40e_bus_type type; 442 443 u16 func; 444 u16 device; 445 u16 lan_id; 446 }; 447 448 /* Flow control (FC) parameters */ 449 struct i40e_fc_info { 450 enum i40e_fc_mode current_mode; /* FC mode in effect */ 451 enum i40e_fc_mode requested_mode; /* FC mode requested by caller */ 452 }; 453 454 #define I40E_MAX_TRAFFIC_CLASS 8 455 #define I40E_MAX_USER_PRIORITY 8 456 #define I40E_DCBX_MAX_APPS 32 457 #define I40E_LLDPDU_SIZE 1500 458 459 /* IEEE 802.1Qaz ETS Configuration data */ 460 struct i40e_ieee_ets_config { 461 u8 willing; 462 u8 cbs; 463 u8 maxtcs; 464 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS]; 465 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS]; 466 u8 tsatable[I40E_MAX_TRAFFIC_CLASS]; 467 }; 468 469 /* IEEE 802.1Qaz ETS Recommendation data */ 470 struct i40e_ieee_ets_recommend { 471 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS]; 472 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS]; 473 u8 tsatable[I40E_MAX_TRAFFIC_CLASS]; 474 }; 475 476 /* IEEE 802.1Qaz PFC Configuration data */ 477 struct i40e_ieee_pfc_config { 478 u8 willing; 479 u8 mbc; 480 u8 pfccap; 481 u8 pfcenable; 482 }; 483 484 /* IEEE 802.1Qaz Application Priority data */ 485 struct i40e_ieee_app_priority_table { 486 u8 priority; 487 u8 selector; 488 u16 protocolid; 489 }; 490 491 struct i40e_dcbx_config { 492 u32 numapps; 493 struct i40e_ieee_ets_config etscfg; 494 struct i40e_ieee_ets_recommend etsrec; 495 struct i40e_ieee_pfc_config pfc; 496 struct i40e_ieee_app_priority_table app[I40E_DCBX_MAX_APPS]; 497 }; 498 499 /* Port hardware description */ 500 struct i40e_hw { 501 u8 *hw_addr; 502 void *back; 503 504 /* function pointer structs */ 505 struct i40e_phy_info phy; 506 struct i40e_mac_info mac; 507 struct i40e_bus_info bus; 508 struct i40e_nvm_info nvm; 509 struct i40e_fc_info fc; 510 511 /* pci info */ 512 u16 device_id; 513 u16 vendor_id; 514 u16 subsystem_device_id; 515 u16 subsystem_vendor_id; 516 u8 revision_id; 517 u8 port; 518 bool adapter_stopped; 519 520 /* capabilities for entire device and PCI func */ 521 struct i40e_hw_capabilities dev_caps; 522 struct i40e_hw_capabilities func_caps; 523 524 /* Flow Director shared filter space */ 525 u16 fdir_shared_filter_count; 526 527 /* device profile info */ 528 u8 pf_id; 529 u16 main_vsi_seid; 530 531 /* Closest numa node to the device */ 532 u16 numa_node; 533 534 /* Admin Queue info */ 535 struct i40e_adminq_info aq; 536 537 /* state of nvm update process */ 538 enum i40e_nvmupd_state nvmupd_state; 539 540 /* HMC info */ 541 struct i40e_hmc_info hmc; /* HMC info struct */ 542 543 /* LLDP/DCBX Status */ 544 u16 dcbx_status; 545 546 /* DCBX info */ 547 struct i40e_dcbx_config local_dcbx_config; 548 struct i40e_dcbx_config remote_dcbx_config; 549 550 /* debug mask */ 551 u32 debug_mask; 552 }; 553 #define i40e_is_vf(_hw) ((_hw)->mac.type == I40E_MAC_VF) 554 555 struct i40e_driver_version { 556 u8 major_version; 557 u8 minor_version; 558 u8 build_version; 559 u8 subbuild_version; 560 u8 driver_string[32]; 561 }; 562 563 /* RX Descriptors */ 564 union i40e_16byte_rx_desc { 565 struct { 566 __le64 pkt_addr; /* Packet buffer address */ 567 __le64 hdr_addr; /* Header buffer address */ 568 } read; 569 struct { 570 struct { 571 struct { 572 union { 573 __le16 mirroring_status; 574 __le16 fcoe_ctx_id; 575 } mirr_fcoe; 576 __le16 l2tag1; 577 } lo_dword; 578 union { 579 __le32 rss; /* RSS Hash */ 580 __le32 fd_id; /* Flow director filter id */ 581 __le32 fcoe_param; /* FCoE DDP Context id */ 582 } hi_dword; 583 } qword0; 584 struct { 585 /* ext status/error/pktype/length */ 586 __le64 status_error_len; 587 } qword1; 588 } wb; /* writeback */ 589 }; 590 591 union i40e_32byte_rx_desc { 592 struct { 593 __le64 pkt_addr; /* Packet buffer address */ 594 __le64 hdr_addr; /* Header buffer address */ 595 /* bit 0 of hdr_buffer_addr is DD bit */ 596 __le64 rsvd1; 597 __le64 rsvd2; 598 } read; 599 struct { 600 struct { 601 struct { 602 union { 603 __le16 mirroring_status; 604 __le16 fcoe_ctx_id; 605 } mirr_fcoe; 606 __le16 l2tag1; 607 } lo_dword; 608 union { 609 __le32 rss; /* RSS Hash */ 610 __le32 fcoe_param; /* FCoE DDP Context id */ 611 /* Flow director filter id in case of 612 * Programming status desc WB 613 */ 614 __le32 fd_id; 615 } hi_dword; 616 } qword0; 617 struct { 618 /* status/error/pktype/length */ 619 __le64 status_error_len; 620 } qword1; 621 struct { 622 __le16 ext_status; /* extended status */ 623 __le16 rsvd; 624 __le16 l2tag2_1; 625 __le16 l2tag2_2; 626 } qword2; 627 struct { 628 union { 629 __le32 flex_bytes_lo; 630 __le32 pe_status; 631 } lo_dword; 632 union { 633 __le32 flex_bytes_hi; 634 __le32 fd_id; 635 } hi_dword; 636 } qword3; 637 } wb; /* writeback */ 638 }; 639 640 #define I40E_RXD_QW0_MIRROR_STATUS_SHIFT 8 641 #define I40E_RXD_QW0_MIRROR_STATUS_MASK (0x3FUL << \ 642 I40E_RXD_QW0_MIRROR_STATUS_SHIFT) 643 #define I40E_RXD_QW0_FCOEINDX_SHIFT 0 644 #define I40E_RXD_QW0_FCOEINDX_MASK (0xFFFUL << \ 645 I40E_RXD_QW0_FCOEINDX_SHIFT) 646 647 enum i40e_rx_desc_status_bits { 648 /* Note: These are predefined bit offsets */ 649 I40E_RX_DESC_STATUS_DD_SHIFT = 0, 650 I40E_RX_DESC_STATUS_EOF_SHIFT = 1, 651 I40E_RX_DESC_STATUS_L2TAG1P_SHIFT = 2, 652 I40E_RX_DESC_STATUS_L3L4P_SHIFT = 3, 653 I40E_RX_DESC_STATUS_CRCP_SHIFT = 4, 654 I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */ 655 I40E_RX_DESC_STATUS_TSYNVALID_SHIFT = 7, 656 I40E_RX_DESC_STATUS_PIF_SHIFT = 8, 657 I40E_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */ 658 I40E_RX_DESC_STATUS_FLM_SHIFT = 11, 659 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT = 12, /* 2 BITS */ 660 I40E_RX_DESC_STATUS_LPBK_SHIFT = 14, 661 I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15, 662 I40E_RX_DESC_STATUS_RESERVED_SHIFT = 16, /* 2 BITS */ 663 I40E_RX_DESC_STATUS_UDP_0_SHIFT = 18, 664 I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */ 665 }; 666 667 #define I40E_RXD_QW1_STATUS_SHIFT 0 668 #define I40E_RXD_QW1_STATUS_MASK (((1 << I40E_RX_DESC_STATUS_LAST) - 1) << \ 669 I40E_RXD_QW1_STATUS_SHIFT) 670 671 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT 672 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \ 673 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT) 674 675 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT I40E_RX_DESC_STATUS_TSYNVALID_SHIFT 676 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK (0x1UL << \ 677 I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT) 678 679 #define I40E_RXD_QW1_STATUS_UMBCAST_SHIFT I40E_RX_DESC_STATUS_UMBCAST 680 #define I40E_RXD_QW1_STATUS_UMBCAST_MASK (0x3UL << \ 681 I40E_RXD_QW1_STATUS_UMBCAST_SHIFT) 682 683 enum i40e_rx_desc_fltstat_values { 684 I40E_RX_DESC_FLTSTAT_NO_DATA = 0, 685 I40E_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */ 686 I40E_RX_DESC_FLTSTAT_RSV = 2, 687 I40E_RX_DESC_FLTSTAT_RSS_HASH = 3, 688 }; 689 690 #define I40E_RXD_PACKET_TYPE_UNICAST 0 691 #define I40E_RXD_PACKET_TYPE_MULTICAST 1 692 #define I40E_RXD_PACKET_TYPE_BROADCAST 2 693 #define I40E_RXD_PACKET_TYPE_MIRRORED 3 694 695 #define I40E_RXD_QW1_ERROR_SHIFT 19 696 #define I40E_RXD_QW1_ERROR_MASK (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT) 697 698 enum i40e_rx_desc_error_bits { 699 /* Note: These are predefined bit offsets */ 700 I40E_RX_DESC_ERROR_RXE_SHIFT = 0, 701 I40E_RX_DESC_ERROR_RECIPE_SHIFT = 1, 702 I40E_RX_DESC_ERROR_HBO_SHIFT = 2, 703 I40E_RX_DESC_ERROR_L3L4E_SHIFT = 3, /* 3 BITS */ 704 I40E_RX_DESC_ERROR_IPE_SHIFT = 3, 705 I40E_RX_DESC_ERROR_L4E_SHIFT = 4, 706 I40E_RX_DESC_ERROR_EIPE_SHIFT = 5, 707 I40E_RX_DESC_ERROR_OVERSIZE_SHIFT = 6, 708 I40E_RX_DESC_ERROR_PPRS_SHIFT = 7 709 }; 710 711 enum i40e_rx_desc_error_l3l4e_fcoe_masks { 712 I40E_RX_DESC_ERROR_L3L4E_NONE = 0, 713 I40E_RX_DESC_ERROR_L3L4E_PROT = 1, 714 I40E_RX_DESC_ERROR_L3L4E_FC = 2, 715 I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR = 3, 716 I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN = 4 717 }; 718 719 #define I40E_RXD_QW1_PTYPE_SHIFT 30 720 #define I40E_RXD_QW1_PTYPE_MASK (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT) 721 722 /* Packet type non-ip values */ 723 enum i40e_rx_l2_ptype { 724 I40E_RX_PTYPE_L2_RESERVED = 0, 725 I40E_RX_PTYPE_L2_MAC_PAY2 = 1, 726 I40E_RX_PTYPE_L2_TIMESYNC_PAY2 = 2, 727 I40E_RX_PTYPE_L2_FIP_PAY2 = 3, 728 I40E_RX_PTYPE_L2_OUI_PAY2 = 4, 729 I40E_RX_PTYPE_L2_MACCNTRL_PAY2 = 5, 730 I40E_RX_PTYPE_L2_LLDP_PAY2 = 6, 731 I40E_RX_PTYPE_L2_ECP_PAY2 = 7, 732 I40E_RX_PTYPE_L2_EVB_PAY2 = 8, 733 I40E_RX_PTYPE_L2_QCN_PAY2 = 9, 734 I40E_RX_PTYPE_L2_EAPOL_PAY2 = 10, 735 I40E_RX_PTYPE_L2_ARP = 11, 736 I40E_RX_PTYPE_L2_FCOE_PAY3 = 12, 737 I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3 = 13, 738 I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3 = 14, 739 I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3 = 15, 740 I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA = 16, 741 I40E_RX_PTYPE_L2_FCOE_VFT_PAY3 = 17, 742 I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA = 18, 743 I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY = 19, 744 I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP = 20, 745 I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER = 21, 746 I40E_RX_PTYPE_GRENAT4_MAC_PAY3 = 58, 747 I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4 = 87, 748 I40E_RX_PTYPE_GRENAT6_MAC_PAY3 = 124, 749 I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4 = 153 750 }; 751 752 struct i40e_rx_ptype_decoded { 753 u32 ptype:8; 754 u32 known:1; 755 u32 outer_ip:1; 756 u32 outer_ip_ver:1; 757 u32 outer_frag:1; 758 u32 tunnel_type:3; 759 u32 tunnel_end_prot:2; 760 u32 tunnel_end_frag:1; 761 u32 inner_prot:4; 762 u32 payload_layer:3; 763 }; 764 765 enum i40e_rx_ptype_outer_ip { 766 I40E_RX_PTYPE_OUTER_L2 = 0, 767 I40E_RX_PTYPE_OUTER_IP = 1 768 }; 769 770 enum i40e_rx_ptype_outer_ip_ver { 771 I40E_RX_PTYPE_OUTER_NONE = 0, 772 I40E_RX_PTYPE_OUTER_IPV4 = 0, 773 I40E_RX_PTYPE_OUTER_IPV6 = 1 774 }; 775 776 enum i40e_rx_ptype_outer_fragmented { 777 I40E_RX_PTYPE_NOT_FRAG = 0, 778 I40E_RX_PTYPE_FRAG = 1 779 }; 780 781 enum i40e_rx_ptype_tunnel_type { 782 I40E_RX_PTYPE_TUNNEL_NONE = 0, 783 I40E_RX_PTYPE_TUNNEL_IP_IP = 1, 784 I40E_RX_PTYPE_TUNNEL_IP_GRENAT = 2, 785 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3, 786 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4, 787 }; 788 789 enum i40e_rx_ptype_tunnel_end_prot { 790 I40E_RX_PTYPE_TUNNEL_END_NONE = 0, 791 I40E_RX_PTYPE_TUNNEL_END_IPV4 = 1, 792 I40E_RX_PTYPE_TUNNEL_END_IPV6 = 2, 793 }; 794 795 enum i40e_rx_ptype_inner_prot { 796 I40E_RX_PTYPE_INNER_PROT_NONE = 0, 797 I40E_RX_PTYPE_INNER_PROT_UDP = 1, 798 I40E_RX_PTYPE_INNER_PROT_TCP = 2, 799 I40E_RX_PTYPE_INNER_PROT_SCTP = 3, 800 I40E_RX_PTYPE_INNER_PROT_ICMP = 4, 801 I40E_RX_PTYPE_INNER_PROT_TIMESYNC = 5 802 }; 803 804 enum i40e_rx_ptype_payload_layer { 805 I40E_RX_PTYPE_PAYLOAD_LAYER_NONE = 0, 806 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1, 807 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2, 808 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3, 809 }; 810 811 #define I40E_RX_PTYPE_BIT_MASK 0x0FFFFFFF 812 #define I40E_RX_PTYPE_SHIFT 56 813 814 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT 38 815 #define I40E_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \ 816 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) 817 818 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT 52 819 #define I40E_RXD_QW1_LENGTH_HBUF_MASK (0x7FFULL << \ 820 I40E_RXD_QW1_LENGTH_HBUF_SHIFT) 821 822 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT 63 823 #define I40E_RXD_QW1_LENGTH_SPH_MASK (0x1ULL << \ 824 I40E_RXD_QW1_LENGTH_SPH_SHIFT) 825 826 #define I40E_RXD_QW1_NEXTP_SHIFT 38 827 #define I40E_RXD_QW1_NEXTP_MASK (0x1FFFULL << I40E_RXD_QW1_NEXTP_SHIFT) 828 829 #define I40E_RXD_QW2_EXT_STATUS_SHIFT 0 830 #define I40E_RXD_QW2_EXT_STATUS_MASK (0xFFFFFUL << \ 831 I40E_RXD_QW2_EXT_STATUS_SHIFT) 832 833 enum i40e_rx_desc_ext_status_bits { 834 /* Note: These are predefined bit offsets */ 835 I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT = 0, 836 I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT = 1, 837 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT = 2, /* 2 BITS */ 838 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT = 4, /* 2 BITS */ 839 I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT = 9, 840 I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10, 841 I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT = 11, 842 }; 843 844 #define I40E_RXD_QW2_L2TAG2_SHIFT 0 845 #define I40E_RXD_QW2_L2TAG2_MASK (0xFFFFUL << I40E_RXD_QW2_L2TAG2_SHIFT) 846 847 #define I40E_RXD_QW2_L2TAG3_SHIFT 16 848 #define I40E_RXD_QW2_L2TAG3_MASK (0xFFFFUL << I40E_RXD_QW2_L2TAG3_SHIFT) 849 850 enum i40e_rx_desc_pe_status_bits { 851 /* Note: These are predefined bit offsets */ 852 I40E_RX_DESC_PE_STATUS_QPID_SHIFT = 0, /* 18 BITS */ 853 I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT = 0, /* 16 BITS */ 854 I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT = 16, /* 8 BITS */ 855 I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT = 24, 856 I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT = 25, 857 I40E_RX_DESC_PE_STATUS_PORTV_SHIFT = 26, 858 I40E_RX_DESC_PE_STATUS_URG_SHIFT = 27, 859 I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT = 28, 860 I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT = 29 861 }; 862 863 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT 38 864 #define I40E_RX_PROG_STATUS_DESC_LENGTH 0x2000000 865 866 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2 867 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK (0x7UL << \ 868 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT) 869 870 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT 0 871 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_MASK (0x7FFFUL << \ 872 I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT) 873 874 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT 19 875 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK (0x3FUL << \ 876 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT) 877 878 enum i40e_rx_prog_status_desc_status_bits { 879 /* Note: These are predefined bit offsets */ 880 I40E_RX_PROG_STATUS_DESC_DD_SHIFT = 0, 881 I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT = 2 /* 3 BITS */ 882 }; 883 884 enum i40e_rx_prog_status_desc_prog_id_masks { 885 I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS = 1, 886 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS = 2, 887 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS = 4, 888 }; 889 890 enum i40e_rx_prog_status_desc_error_bits { 891 /* Note: These are predefined bit offsets */ 892 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT = 0, 893 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT = 1, 894 I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT = 2, 895 I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT = 3 896 }; 897 898 #define I40E_TWO_BIT_MASK 0x3 899 #define I40E_THREE_BIT_MASK 0x7 900 #define I40E_FOUR_BIT_MASK 0xF 901 #define I40E_EIGHTEEN_BIT_MASK 0x3FFFF 902 903 /* TX Descriptor */ 904 struct i40e_tx_desc { 905 __le64 buffer_addr; /* Address of descriptor's data buf */ 906 __le64 cmd_type_offset_bsz; 907 }; 908 909 #define I40E_TXD_QW1_DTYPE_SHIFT 0 910 #define I40E_TXD_QW1_DTYPE_MASK (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT) 911 912 enum i40e_tx_desc_dtype_value { 913 I40E_TX_DESC_DTYPE_DATA = 0x0, 914 I40E_TX_DESC_DTYPE_NOP = 0x1, /* same as Context desc */ 915 I40E_TX_DESC_DTYPE_CONTEXT = 0x1, 916 I40E_TX_DESC_DTYPE_FCOE_CTX = 0x2, 917 I40E_TX_DESC_DTYPE_FILTER_PROG = 0x8, 918 I40E_TX_DESC_DTYPE_DDP_CTX = 0x9, 919 I40E_TX_DESC_DTYPE_FLEX_DATA = 0xB, 920 I40E_TX_DESC_DTYPE_FLEX_CTX_1 = 0xC, 921 I40E_TX_DESC_DTYPE_FLEX_CTX_2 = 0xD, 922 I40E_TX_DESC_DTYPE_DESC_DONE = 0xF 923 }; 924 925 #define I40E_TXD_QW1_CMD_SHIFT 4 926 #define I40E_TXD_QW1_CMD_MASK (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT) 927 928 enum i40e_tx_desc_cmd_bits { 929 I40E_TX_DESC_CMD_EOP = 0x0001, 930 I40E_TX_DESC_CMD_RS = 0x0002, 931 I40E_TX_DESC_CMD_ICRC = 0x0004, 932 I40E_TX_DESC_CMD_IL2TAG1 = 0x0008, 933 I40E_TX_DESC_CMD_DUMMY = 0x0010, 934 I40E_TX_DESC_CMD_IIPT_NONIP = 0x0000, /* 2 BITS */ 935 I40E_TX_DESC_CMD_IIPT_IPV6 = 0x0020, /* 2 BITS */ 936 I40E_TX_DESC_CMD_IIPT_IPV4 = 0x0040, /* 2 BITS */ 937 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, /* 2 BITS */ 938 I40E_TX_DESC_CMD_FCOET = 0x0080, 939 I40E_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000, /* 2 BITS */ 940 I40E_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, /* 2 BITS */ 941 I40E_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, /* 2 BITS */ 942 I40E_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, /* 2 BITS */ 943 I40E_TX_DESC_CMD_L4T_EOFT_EOF_N = 0x0000, /* 2 BITS */ 944 I40E_TX_DESC_CMD_L4T_EOFT_EOF_T = 0x0100, /* 2 BITS */ 945 I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI = 0x0200, /* 2 BITS */ 946 I40E_TX_DESC_CMD_L4T_EOFT_EOF_A = 0x0300, /* 2 BITS */ 947 }; 948 949 #define I40E_TXD_QW1_OFFSET_SHIFT 16 950 #define I40E_TXD_QW1_OFFSET_MASK (0x3FFFFULL << \ 951 I40E_TXD_QW1_OFFSET_SHIFT) 952 953 enum i40e_tx_desc_length_fields { 954 /* Note: These are predefined bit offsets */ 955 I40E_TX_DESC_LENGTH_MACLEN_SHIFT = 0, /* 7 BITS */ 956 I40E_TX_DESC_LENGTH_IPLEN_SHIFT = 7, /* 7 BITS */ 957 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT = 14 /* 4 BITS */ 958 }; 959 960 #define I40E_TXD_QW1_MACLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_MACLEN_SHIFT) 961 #define I40E_TXD_QW1_IPLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_IPLEN_SHIFT) 962 #define I40E_TXD_QW1_L4LEN_MASK (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT) 963 #define I40E_TXD_QW1_FCLEN_MASK (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT) 964 965 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT 34 966 #define I40E_TXD_QW1_TX_BUF_SZ_MASK (0x3FFFULL << \ 967 I40E_TXD_QW1_TX_BUF_SZ_SHIFT) 968 969 #define I40E_TXD_QW1_L2TAG1_SHIFT 48 970 #define I40E_TXD_QW1_L2TAG1_MASK (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT) 971 972 /* Context descriptors */ 973 struct i40e_tx_context_desc { 974 __le32 tunneling_params; 975 __le16 l2tag2; 976 __le16 rsvd; 977 __le64 type_cmd_tso_mss; 978 }; 979 980 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT 0 981 #define I40E_TXD_CTX_QW1_DTYPE_MASK (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT) 982 983 #define I40E_TXD_CTX_QW1_CMD_SHIFT 4 984 #define I40E_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT) 985 986 enum i40e_tx_ctx_desc_cmd_bits { 987 I40E_TX_CTX_DESC_TSO = 0x01, 988 I40E_TX_CTX_DESC_TSYN = 0x02, 989 I40E_TX_CTX_DESC_IL2TAG2 = 0x04, 990 I40E_TX_CTX_DESC_IL2TAG2_IL2H = 0x08, 991 I40E_TX_CTX_DESC_SWTCH_NOTAG = 0x00, 992 I40E_TX_CTX_DESC_SWTCH_UPLINK = 0x10, 993 I40E_TX_CTX_DESC_SWTCH_LOCAL = 0x20, 994 I40E_TX_CTX_DESC_SWTCH_VSI = 0x30, 995 I40E_TX_CTX_DESC_SWPE = 0x40 996 }; 997 998 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT 30 999 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \ 1000 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) 1001 1002 #define I40E_TXD_CTX_QW1_MSS_SHIFT 50 1003 #define I40E_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \ 1004 I40E_TXD_CTX_QW1_MSS_SHIFT) 1005 1006 #define I40E_TXD_CTX_QW1_VSI_SHIFT 50 1007 #define I40E_TXD_CTX_QW1_VSI_MASK (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT) 1008 1009 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT 0 1010 #define I40E_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \ 1011 I40E_TXD_CTX_QW0_EXT_IP_SHIFT) 1012 1013 enum i40e_tx_ctx_desc_eipt_offload { 1014 I40E_TX_CTX_EXT_IP_NONE = 0x0, 1015 I40E_TX_CTX_EXT_IP_IPV6 = 0x1, 1016 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2, 1017 I40E_TX_CTX_EXT_IP_IPV4 = 0x3 1018 }; 1019 1020 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2 1021 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \ 1022 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT) 1023 1024 #define I40E_TXD_CTX_QW0_NATT_SHIFT 9 1025 #define I40E_TXD_CTX_QW0_NATT_MASK (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT) 1026 1027 #define I40E_TXD_CTX_UDP_TUNNELING (0x1ULL << I40E_TXD_CTX_QW0_NATT_SHIFT) 1028 #define I40E_TXD_CTX_GRE_TUNNELING (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT) 1029 1030 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT 11 1031 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK (0x1ULL << \ 1032 I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT) 1033 1034 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST I40E_TXD_CTX_QW0_EIP_NOINC_MASK 1035 1036 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT 12 1037 #define I40E_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \ 1038 I40E_TXD_CTX_QW0_NATLEN_SHIFT) 1039 1040 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT 19 1041 #define I40E_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \ 1042 I40E_TXD_CTX_QW0_DECTTL_SHIFT) 1043 1044 struct i40e_nop_desc { 1045 __le64 rsvd; 1046 __le64 dtype_cmd; 1047 }; 1048 1049 #define I40E_TXD_NOP_QW1_DTYPE_SHIFT 0 1050 #define I40E_TXD_NOP_QW1_DTYPE_MASK (0xFUL << I40E_TXD_NOP_QW1_DTYPE_SHIFT) 1051 1052 #define I40E_TXD_NOP_QW1_CMD_SHIFT 4 1053 #define I40E_TXD_NOP_QW1_CMD_MASK (0x7FUL << I40E_TXD_NOP_QW1_CMD_SHIFT) 1054 1055 enum i40e_tx_nop_desc_cmd_bits { 1056 /* Note: These are predefined bit offsets */ 1057 I40E_TX_NOP_DESC_EOP_SHIFT = 0, 1058 I40E_TX_NOP_DESC_RS_SHIFT = 1, 1059 I40E_TX_NOP_DESC_RSV_SHIFT = 2 /* 5 bits */ 1060 }; 1061 1062 struct i40e_filter_program_desc { 1063 __le32 qindex_flex_ptype_vsi; 1064 __le32 rsvd; 1065 __le32 dtype_cmd_cntindex; 1066 __le32 fd_id; 1067 }; 1068 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT 0 1069 #define I40E_TXD_FLTR_QW0_QINDEX_MASK (0x7FFUL << \ 1070 I40E_TXD_FLTR_QW0_QINDEX_SHIFT) 1071 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11 1072 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK (0x7UL << \ 1073 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) 1074 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT 17 1075 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK (0x3FUL << \ 1076 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) 1077 1078 /* Packet Classifier Types for filters */ 1079 enum i40e_filter_pctype { 1080 /* Note: Values 0-30 are reserved for future use */ 1081 I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31, 1082 /* Note: Value 32 is reserved for future use */ 1083 I40E_FILTER_PCTYPE_NONF_IPV4_TCP = 33, 1084 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34, 1085 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35, 1086 I40E_FILTER_PCTYPE_FRAG_IPV4 = 36, 1087 /* Note: Values 37-40 are reserved for future use */ 1088 I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41, 1089 I40E_FILTER_PCTYPE_NONF_IPV6_TCP = 43, 1090 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP = 44, 1091 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER = 45, 1092 I40E_FILTER_PCTYPE_FRAG_IPV6 = 46, 1093 /* Note: Value 47 is reserved for future use */ 1094 I40E_FILTER_PCTYPE_FCOE_OX = 48, 1095 I40E_FILTER_PCTYPE_FCOE_RX = 49, 1096 I40E_FILTER_PCTYPE_FCOE_OTHER = 50, 1097 /* Note: Values 51-62 are reserved for future use */ 1098 I40E_FILTER_PCTYPE_L2_PAYLOAD = 63, 1099 }; 1100 1101 enum i40e_filter_program_desc_dest { 1102 I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET = 0x0, 1103 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX = 0x1, 1104 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER = 0x2, 1105 }; 1106 1107 enum i40e_filter_program_desc_fd_status { 1108 I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE = 0x0, 1109 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID = 0x1, 1110 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES = 0x2, 1111 I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES = 0x3, 1112 }; 1113 1114 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23 1115 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \ 1116 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) 1117 1118 #define I40E_TXD_FLTR_QW1_DTYPE_SHIFT 0 1119 #define I40E_TXD_FLTR_QW1_DTYPE_MASK (0xFUL << I40E_TXD_FLTR_QW1_DTYPE_SHIFT) 1120 1121 #define I40E_TXD_FLTR_QW1_CMD_SHIFT 4 1122 #define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \ 1123 I40E_TXD_FLTR_QW1_CMD_SHIFT) 1124 1125 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT) 1126 #define I40E_TXD_FLTR_QW1_PCMD_MASK (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT) 1127 1128 enum i40e_filter_program_desc_pcmd { 1129 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE = 0x1, 1130 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE = 0x2, 1131 }; 1132 1133 #define I40E_TXD_FLTR_QW1_DEST_SHIFT (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT) 1134 #define I40E_TXD_FLTR_QW1_DEST_MASK (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT) 1135 1136 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT) 1137 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK (0x1ULL << \ 1138 I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT) 1139 1140 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \ 1141 I40E_TXD_FLTR_QW1_CMD_SHIFT) 1142 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \ 1143 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) 1144 1145 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20 1146 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \ 1147 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) 1148 1149 enum i40e_filter_type { 1150 I40E_FLOW_DIRECTOR_FLTR = 0, 1151 I40E_PE_QUAD_HASH_FLTR = 1, 1152 I40E_ETHERTYPE_FLTR, 1153 I40E_FCOE_CTX_FLTR, 1154 I40E_MAC_VLAN_FLTR, 1155 I40E_HASH_FLTR 1156 }; 1157 1158 struct i40e_vsi_context { 1159 u16 seid; 1160 u16 uplink_seid; 1161 u16 vsi_number; 1162 u16 vsis_allocated; 1163 u16 vsis_unallocated; 1164 u16 flags; 1165 u8 pf_num; 1166 u8 vf_num; 1167 u8 connection_type; 1168 struct i40e_aqc_vsi_properties_data info; 1169 }; 1170 1171 struct i40e_veb_context { 1172 u16 seid; 1173 u16 uplink_seid; 1174 u16 veb_number; 1175 u16 vebs_allocated; 1176 u16 vebs_unallocated; 1177 u16 flags; 1178 struct i40e_aqc_get_veb_parameters_completion info; 1179 }; 1180 1181 /* Statistics collected by each port, VSI, VEB, and S-channel */ 1182 struct i40e_eth_stats { 1183 u64 rx_bytes; /* gorc */ 1184 u64 rx_unicast; /* uprc */ 1185 u64 rx_multicast; /* mprc */ 1186 u64 rx_broadcast; /* bprc */ 1187 u64 rx_discards; /* rdpc */ 1188 u64 rx_unknown_protocol; /* rupp */ 1189 u64 tx_bytes; /* gotc */ 1190 u64 tx_unicast; /* uptc */ 1191 u64 tx_multicast; /* mptc */ 1192 u64 tx_broadcast; /* bptc */ 1193 u64 tx_discards; /* tdpc */ 1194 u64 tx_errors; /* tepc */ 1195 }; 1196 1197 /* Statistics collected by the MAC */ 1198 struct i40e_hw_port_stats { 1199 /* eth stats collected by the port */ 1200 struct i40e_eth_stats eth; 1201 1202 /* additional port specific stats */ 1203 u64 tx_dropped_link_down; /* tdold */ 1204 u64 crc_errors; /* crcerrs */ 1205 u64 illegal_bytes; /* illerrc */ 1206 u64 error_bytes; /* errbc */ 1207 u64 mac_local_faults; /* mlfc */ 1208 u64 mac_remote_faults; /* mrfc */ 1209 u64 rx_length_errors; /* rlec */ 1210 u64 link_xon_rx; /* lxonrxc */ 1211 u64 link_xoff_rx; /* lxoffrxc */ 1212 u64 priority_xon_rx[8]; /* pxonrxc[8] */ 1213 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */ 1214 u64 link_xon_tx; /* lxontxc */ 1215 u64 link_xoff_tx; /* lxofftxc */ 1216 u64 priority_xon_tx[8]; /* pxontxc[8] */ 1217 u64 priority_xoff_tx[8]; /* pxofftxc[8] */ 1218 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */ 1219 u64 rx_size_64; /* prc64 */ 1220 u64 rx_size_127; /* prc127 */ 1221 u64 rx_size_255; /* prc255 */ 1222 u64 rx_size_511; /* prc511 */ 1223 u64 rx_size_1023; /* prc1023 */ 1224 u64 rx_size_1522; /* prc1522 */ 1225 u64 rx_size_big; /* prc9522 */ 1226 u64 rx_undersize; /* ruc */ 1227 u64 rx_fragments; /* rfc */ 1228 u64 rx_oversize; /* roc */ 1229 u64 rx_jabber; /* rjc */ 1230 u64 tx_size_64; /* ptc64 */ 1231 u64 tx_size_127; /* ptc127 */ 1232 u64 tx_size_255; /* ptc255 */ 1233 u64 tx_size_511; /* ptc511 */ 1234 u64 tx_size_1023; /* ptc1023 */ 1235 u64 tx_size_1522; /* ptc1522 */ 1236 u64 tx_size_big; /* ptc9522 */ 1237 u64 mac_short_packet_dropped; /* mspdc */ 1238 u64 checksum_error; /* xec */ 1239 /* flow director stats */ 1240 u64 fd_atr_match; 1241 u64 fd_sb_match; 1242 /* EEE LPI */ 1243 u32 tx_lpi_status; 1244 u32 rx_lpi_status; 1245 u64 tx_lpi_count; /* etlpic */ 1246 u64 rx_lpi_count; /* erlpic */ 1247 }; 1248 1249 /* Checksum and Shadow RAM pointers */ 1250 #define I40E_SR_NVM_CONTROL_WORD 0x00 1251 #define I40E_SR_PCIE_ANALOG_CONFIG_PTR 0x03 1252 #define I40E_SR_PHY_ANALOG_CONFIG_PTR 0x04 1253 #define I40E_SR_OPTION_ROM_PTR 0x05 1254 #define I40E_SR_RO_PCIR_REGS_AUTO_LOAD_PTR 0x06 1255 #define I40E_SR_AUTO_GENERATED_POINTERS_PTR 0x07 1256 #define I40E_SR_PCIR_REGS_AUTO_LOAD_PTR 0x08 1257 #define I40E_SR_EMP_GLOBAL_MODULE_PTR 0x09 1258 #define I40E_SR_RO_PCIE_LCB_PTR 0x0A 1259 #define I40E_SR_EMP_IMAGE_PTR 0x0B 1260 #define I40E_SR_PE_IMAGE_PTR 0x0C 1261 #define I40E_SR_CSR_PROTECTED_LIST_PTR 0x0D 1262 #define I40E_SR_MNG_CONFIG_PTR 0x0E 1263 #define I40E_SR_EMP_MODULE_PTR 0x0F 1264 #define I40E_SR_PBA_BLOCK_PTR 0x16 1265 #define I40E_SR_BOOT_CONFIG_PTR 0x17 1266 #define I40E_SR_NVM_IMAGE_VERSION 0x18 1267 #define I40E_SR_NVM_WAKE_ON_LAN 0x19 1268 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27 1269 #define I40E_SR_PERMANENT_SAN_MAC_ADDRESS_PTR 0x28 1270 #define I40E_SR_NVM_EETRACK_LO 0x2D 1271 #define I40E_SR_NVM_EETRACK_HI 0x2E 1272 #define I40E_SR_VPD_PTR 0x2F 1273 #define I40E_SR_PXE_SETUP_PTR 0x30 1274 #define I40E_SR_PXE_CONFIG_CUST_OPTIONS_PTR 0x31 1275 #define I40E_SR_SW_ETHERNET_MAC_ADDRESS_PTR 0x37 1276 #define I40E_SR_POR_REGS_AUTO_LOAD_PTR 0x38 1277 #define I40E_SR_EMPR_REGS_AUTO_LOAD_PTR 0x3A 1278 #define I40E_SR_GLOBR_REGS_AUTO_LOAD_PTR 0x3B 1279 #define I40E_SR_CORER_REGS_AUTO_LOAD_PTR 0x3C 1280 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E 1281 #define I40E_SR_SW_CHECKSUM_WORD 0x3F 1282 #define I40E_SR_1ST_FREE_PROVISION_AREA_PTR 0x40 1283 #define I40E_SR_4TH_FREE_PROVISION_AREA_PTR 0x42 1284 #define I40E_SR_3RD_FREE_PROVISION_AREA_PTR 0x44 1285 #define I40E_SR_2ND_FREE_PROVISION_AREA_PTR 0x46 1286 #define I40E_SR_EMP_SR_SETTINGS_PTR 0x48 1287 1288 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */ 1289 #define I40E_SR_VPD_MODULE_MAX_SIZE 1024 1290 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024 1291 #define I40E_SR_CONTROL_WORD_1_SHIFT 0x06 1292 #define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT) 1293 1294 /* Shadow RAM related */ 1295 #define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800 1296 #define I40E_SR_BUF_ALIGNMENT 4096 1297 #define I40E_SR_WORDS_IN_1KB 512 1298 /* Checksum should be calculated such that after adding all the words, 1299 * including the checksum word itself, the sum should be 0xBABA. 1300 */ 1301 #define I40E_SR_SW_CHECKSUM_BASE 0xBABA 1302 1303 #define I40E_SRRD_SRCTL_ATTEMPTS 100000 1304 1305 enum i40e_switch_element_types { 1306 I40E_SWITCH_ELEMENT_TYPE_MAC = 1, 1307 I40E_SWITCH_ELEMENT_TYPE_PF = 2, 1308 I40E_SWITCH_ELEMENT_TYPE_VF = 3, 1309 I40E_SWITCH_ELEMENT_TYPE_EMP = 4, 1310 I40E_SWITCH_ELEMENT_TYPE_BMC = 6, 1311 I40E_SWITCH_ELEMENT_TYPE_PE = 16, 1312 I40E_SWITCH_ELEMENT_TYPE_VEB = 17, 1313 I40E_SWITCH_ELEMENT_TYPE_PA = 18, 1314 I40E_SWITCH_ELEMENT_TYPE_VSI = 19, 1315 }; 1316 1317 /* Supported EtherType filters */ 1318 enum i40e_ether_type_index { 1319 I40E_ETHER_TYPE_1588 = 0, 1320 I40E_ETHER_TYPE_FIP = 1, 1321 I40E_ETHER_TYPE_OUI_EXTENDED = 2, 1322 I40E_ETHER_TYPE_MAC_CONTROL = 3, 1323 I40E_ETHER_TYPE_LLDP = 4, 1324 I40E_ETHER_TYPE_EVB_PROTOCOL1 = 5, 1325 I40E_ETHER_TYPE_EVB_PROTOCOL2 = 6, 1326 I40E_ETHER_TYPE_QCN_CNM = 7, 1327 I40E_ETHER_TYPE_8021X = 8, 1328 I40E_ETHER_TYPE_ARP = 9, 1329 I40E_ETHER_TYPE_RSV1 = 10, 1330 I40E_ETHER_TYPE_RSV2 = 11, 1331 }; 1332 1333 /* Filter context base size is 1K */ 1334 #define I40E_HASH_FILTER_BASE_SIZE 1024 1335 /* Supported Hash filter values */ 1336 enum i40e_hash_filter_size { 1337 I40E_HASH_FILTER_SIZE_1K = 0, 1338 I40E_HASH_FILTER_SIZE_2K = 1, 1339 I40E_HASH_FILTER_SIZE_4K = 2, 1340 I40E_HASH_FILTER_SIZE_8K = 3, 1341 I40E_HASH_FILTER_SIZE_16K = 4, 1342 I40E_HASH_FILTER_SIZE_32K = 5, 1343 I40E_HASH_FILTER_SIZE_64K = 6, 1344 I40E_HASH_FILTER_SIZE_128K = 7, 1345 I40E_HASH_FILTER_SIZE_256K = 8, 1346 I40E_HASH_FILTER_SIZE_512K = 9, 1347 I40E_HASH_FILTER_SIZE_1M = 10, 1348 }; 1349 1350 /* DMA context base size is 0.5K */ 1351 #define I40E_DMA_CNTX_BASE_SIZE 512 1352 /* Supported DMA context values */ 1353 enum i40e_dma_cntx_size { 1354 I40E_DMA_CNTX_SIZE_512 = 0, 1355 I40E_DMA_CNTX_SIZE_1K = 1, 1356 I40E_DMA_CNTX_SIZE_2K = 2, 1357 I40E_DMA_CNTX_SIZE_4K = 3, 1358 I40E_DMA_CNTX_SIZE_8K = 4, 1359 I40E_DMA_CNTX_SIZE_16K = 5, 1360 I40E_DMA_CNTX_SIZE_32K = 6, 1361 I40E_DMA_CNTX_SIZE_64K = 7, 1362 I40E_DMA_CNTX_SIZE_128K = 8, 1363 I40E_DMA_CNTX_SIZE_256K = 9, 1364 }; 1365 1366 /* Supported Hash look up table (LUT) sizes */ 1367 enum i40e_hash_lut_size { 1368 I40E_HASH_LUT_SIZE_128 = 0, 1369 I40E_HASH_LUT_SIZE_512 = 1, 1370 }; 1371 1372 /* Structure to hold a per PF filter control settings */ 1373 struct i40e_filter_control_settings { 1374 /* number of PE Quad Hash filter buckets */ 1375 enum i40e_hash_filter_size pe_filt_num; 1376 /* number of PE Quad Hash contexts */ 1377 enum i40e_dma_cntx_size pe_cntx_num; 1378 /* number of FCoE filter buckets */ 1379 enum i40e_hash_filter_size fcoe_filt_num; 1380 /* number of FCoE DDP contexts */ 1381 enum i40e_dma_cntx_size fcoe_cntx_num; 1382 /* size of the Hash LUT */ 1383 enum i40e_hash_lut_size hash_lut_size; 1384 /* enable FDIR filters for PF and its VFs */ 1385 bool enable_fdir; 1386 /* enable Ethertype filters for PF and its VFs */ 1387 bool enable_ethtype; 1388 /* enable MAC/VLAN filters for PF and its VFs */ 1389 bool enable_macvlan; 1390 }; 1391 1392 /* Structure to hold device level control filter counts */ 1393 struct i40e_control_filter_stats { 1394 u16 mac_etype_used; /* Used perfect match MAC/EtherType filters */ 1395 u16 etype_used; /* Used perfect EtherType filters */ 1396 u16 mac_etype_free; /* Un-used perfect match MAC/EtherType filters */ 1397 u16 etype_free; /* Un-used perfect EtherType filters */ 1398 }; 1399 1400 enum i40e_reset_type { 1401 I40E_RESET_POR = 0, 1402 I40E_RESET_CORER = 1, 1403 I40E_RESET_GLOBR = 2, 1404 I40E_RESET_EMPR = 3, 1405 }; 1406 1407 /* Offsets into Alternate Ram */ 1408 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET 0 /* in dwords */ 1409 #define I40E_ALT_STRUCT_DWORDS_PER_PF 64 /* in dwords */ 1410 #define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET 0xD /* in dwords */ 1411 #define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET 0xC /* in dwords */ 1412 #define I40E_ALT_STRUCT_MIN_BW_OFFSET 0xE /* in dwords */ 1413 #define I40E_ALT_STRUCT_MAX_BW_OFFSET 0xF /* in dwords */ 1414 1415 /* Alternate Ram Bandwidth Masks */ 1416 #define I40E_ALT_BW_VALUE_MASK 0xFF 1417 #define I40E_ALT_BW_RELATIVE_MASK 0x40000000 1418 #define I40E_ALT_BW_VALID_MASK 0x80000000 1419 1420 /* RSS Hash Table Size */ 1421 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000 1422 #endif /* _I40E_TYPE_H_ */ 1423