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Searched refs:dmar (Results 1 – 10 of 10) sorted by relevance

/trueos/sys/x86/iommu/
HDintel_ctx.c74 dmar_ensure_ctx_page(struct dmar_unit *dmar, int bus) in dmar_ensure_ctx_page() argument
83 ctxm = dmar_pgalloc(dmar->ctx_obj, 1 + bus, DMAR_PGF_NOALLOC); in dmar_ensure_ctx_page()
94 ctxm = dmar_pgalloc(dmar->ctx_obj, 1 + bus, DMAR_PGF_ZERO | in dmar_ensure_ctx_page()
96 re = dmar_map_pgtbl(dmar->ctx_obj, 0, DMAR_PGF_NOALLOC, &sf); in dmar_ensure_ctx_page()
100 dmar_flush_root_to_ram(dmar, re); in dmar_ensure_ctx_page()
110 ctxp = dmar_map_pgtbl(ctx->dmar->ctx_obj, 1 + PCI_RID2BUS(ctx->rid), in dmar_map_ctx_entry()
141 unit = ctx->dmar; in ctx_id_entry_init()
197 ctx->dmar->unit, start, end); in ctx_init_rmrr()
216 DMAR_LOCK(ctx->dmar); in ctx_init_rmrr()
218 DMAR_UNLOCK(ctx->dmar); in ctx_init_rmrr()
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HDintel_utils.c122 sagaw = DMAR_CAP_SAGAW(ctx->dmar->hw_cap); in ctx_set_agaw()
131 device_printf(ctx->dmar->dev, in ctx_set_agaw()
133 "no agaw found, sagaw %x\n", mgaw, ctx->dmar->segment, in ctx_set_agaw()
203 cap_sps = DMAR_CAP_SPS(ctx->dmar->hw_cap); in ctx_is_sp_lvl()
532 dmar_barrier_enter(struct dmar_unit *dmar, u_int barrier_id) in dmar_barrier_enter() argument
536 DMAR_LOCK(dmar); in dmar_barrier_enter()
537 if ((dmar->barrier_flags & f_done) != 0) { in dmar_barrier_enter()
538 DMAR_UNLOCK(dmar); in dmar_barrier_enter()
542 if ((dmar->barrier_flags & f_inproc) != 0) { in dmar_barrier_enter()
543 while ((dmar->barrier_flags & f_inproc) != 0) { in dmar_barrier_enter()
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HDintel_quirks.c82 dmar_match_quirks(struct dmar_unit *dmar, in dmar_match_quirks() argument
104 device_printf(dmar->dev, in dmar_match_quirks()
108 nb_quirk->quirk(dmar); in dmar_match_quirks()
112 device_printf(dmar->dev, "cannot find northbridge\n"); in dmar_match_quirks()
131 device_printf(dmar->dev, in dmar_match_quirks()
135 cpu_quirk->quirk(dmar); in dmar_match_quirks()
178 dmar_quirks_pre_use(struct dmar_unit *dmar) in dmar_quirks_pre_use() argument
181 if (!dmar_barrier_enter(dmar, DMAR_BARRIER_USEQ)) in dmar_quirks_pre_use()
183 DMAR_LOCK(dmar); in dmar_quirks_pre_use()
184 dmar_match_quirks(dmar, pre_use_nb, nitems(pre_use_nb), in dmar_quirks_pre_use()
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HDintel_dmar.h86 struct dmar_unit *dmar; member
199 #define DMAR_LOCK(dmar) mtx_lock(&(dmar)->lock) argument
200 #define DMAR_UNLOCK(dmar) mtx_unlock(&(dmar)->lock) argument
201 #define DMAR_ASSERT_LOCKED(dmar) mtx_assert(&(dmar)->lock, MA_OWNED) argument
203 #define DMAR_FAULT_LOCK(dmar) mtx_lock_spin(&(dmar)->fault_lock) argument
204 #define DMAR_FAULT_UNLOCK(dmar) mtx_unlock_spin(&(dmar)->fault_lock) argument
205 #define DMAR_FAULT_ASSERT_LOCKED(dmar) mtx_assert(&(dmar)->fault_lock, MA_OWNED) argument
207 #define DMAR_IS_COHERENT(dmar) (((dmar)->hw_ecap & DMAR_ECAP_C) != 0) argument
208 #define DMAR_HAS_QI(dmar) (((dmar)->hw_ecap & DMAR_ECAP_QI) != 0) argument
241 bool dmar_barrier_enter(struct dmar_unit *dmar, u_int barrier_id);
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HDintel_drv.c573 DRIVER_MODULE(dmar, acpi, dmar_driver, dmar_devclass, 0, 0);
574 MODULE_DEPEND(dmar, acpi, 1, 1, 1);
851 struct dmar_unit *dmar; member
896 if (resmem->Segment != iria->dmar->segment) in dmar_inst_rmrr_iter()
899 printf("dmar%d: RMRR [%jx,%jx]\n", iria->dmar->unit, in dmar_inst_rmrr_iter()
915 dmar_print_path(iria->dmar->dev, "RMRR scope", in dmar_inst_rmrr_iter()
929 if (dev_dmar != iria->dmar) { in dmar_inst_rmrr_iter()
938 dmar_instantiate_ctx(iria->dmar, dev, true); in dmar_inst_rmrr_iter()
949 dmar_instantiate_rmrr_ctxs(struct dmar_unit *dmar) in dmar_instantiate_rmrr_ctxs() argument
954 if (!dmar_barrier_enter(dmar, DMAR_BARRIER_RMRR)) in dmar_instantiate_rmrr_ctxs()
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HDbusdma_dmar.c208 dmar_instantiate_ctx(struct dmar_unit *dmar, device_t dev, bool rmrr) in dmar_instantiate_ctx() argument
227 ctx = dmar_get_ctx(dmar, requester, rid, disabled, rmrr); in dmar_instantiate_ctx()
235 DMAR_LOCK(dmar); in dmar_instantiate_ctx()
238 DMAR_UNLOCK(dmar); in dmar_instantiate_ctx()
240 dmar_free_ctx_locked(dmar, ctx); in dmar_instantiate_ctx()
250 struct dmar_unit *dmar; in dmar_get_dma_tag() local
254 dmar = dmar_find(child); in dmar_get_dma_tag()
256 if (dmar == NULL) in dmar_get_dma_tag()
258 dmar_quirks_pre_use(dmar); in dmar_get_dma_tag()
259 dmar_instantiate_rmrr_ctxs(dmar); in dmar_get_dma_tag()
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HDintel_idpgtbl.c193 dmar_pglvl_supported(ctx->dmar, tbl->pglvl) && in ctx_get_idmap_pgtbl()
212 dmar_pglvl_supported(ctx->dmar, tbl->pglvl) && in ctx_get_idmap_pgtbl()
253 unit = ctx->dmar; in ctx_get_idmap_pgtbl()
400 dmar_flush_pte_to_ram(ctx->dmar, ptep); in ctx_pgtbl_map_pte()
480 dmar_flush_pte_to_ram(ctx->dmar, pte); in ctx_map_buf_locked()
496 unit = ctx->dmar; in ctx_map_buf()
571 dmar_flush_pte_to_ram(ctx->dmar, pte); in ctx_unmap_clear_pte()
702 KASSERT((ctx->dmar->hw_ecap & DMAR_ECAP_PT) != 0 && in ctx_free_pgtbl()
748 unit = ctx->dmar; in ctx_flush_iotlb_sync()
HDintel_qi.c221 unit = ctx->dmar; in dmar_qi_invalidate_locked()
/trueos/sys/amd64/vmm/intel/
HDvtd.c247 ACPI_TABLE_DMAR *dmar; in vtd_init() local
271 status = AcpiGetTable(ACPI_SIG_DMAR, 0, (ACPI_TABLE_HEADER **)&dmar); in vtd_init()
275 end = (char *)dmar + dmar->Header.Length; in vtd_init()
276 remaining = dmar->Header.Length - sizeof(ACPI_TABLE_DMAR); in vtd_init()
/trueos/usr.sbin/acpi/acpidump/
HDacpi.c966 ACPI_TABLE_DMAR *dmar; in acpi_handle_dmar() local
970 dmar = (ACPI_TABLE_DMAR *)sdp; in acpi_handle_dmar()
971 printf("\tHost Address Width=%d\n", dmar->Width + 1); in acpi_handle_dmar()
976 PRINTFLAG(dmar->Flags, INTR_REMAP); in acpi_handle_dmar()
977 PRINTFLAG(dmar->Flags, X2APIC_OPT_OUT); in acpi_handle_dmar()