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Searched refs:ctl_reg (Results 1 – 5 of 5) sorted by relevance

/trueos/sys/amd64/vmm/intel/
HDvmx_msr.c84 vmx_set_ctlreg(int ctl_reg, int true_ctl_reg, uint32_t ones_mask, in vmx_set_ctlreg() argument
100 val = rdmsr(ctl_reg); in vmx_set_ctlreg()
112 "truectl 0x%0x\n", i, ctl_reg, true_ctl_reg)); in vmx_set_ctlreg()
136 "0x%0x and true msr 0x%0x", i, ctl_reg, in vmx_set_ctlreg()
HDvmx_msr.h43 int vmx_set_ctlreg(int ctl_reg, int true_ctl_reg, uint32_t ones_mask,
/trueos/sys/dev/drm2/i915/
HDintel_lvds.c73 u32 ctl_reg, lvds_reg, stat_reg; in intel_lvds_enable() local
76 ctl_reg = PCH_PP_CONTROL; in intel_lvds_enable()
80 ctl_reg = PP_CONTROL; in intel_lvds_enable()
103 I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON); in intel_lvds_enable()
117 u32 ctl_reg, lvds_reg, stat_reg; in intel_lvds_disable() local
120 ctl_reg = PCH_PP_CONTROL; in intel_lvds_disable()
124 ctl_reg = PP_CONTROL; in intel_lvds_disable()
131 I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON); in intel_lvds_disable()
HDintel_hdmi.c284 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe); in hsw_write_infoframe() local
287 u32 val = I915_READ(ctl_reg); in hsw_write_infoframe()
295 I915_WRITE(ctl_reg, val); in hsw_write_infoframe()
303 I915_WRITE(ctl_reg, val); in hsw_write_infoframe()
/trueos/sys/dev/cxgbe/common/
HDt4_hw.c247 u32 ctl_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_CTRL); in t4_wr_mbox_meat() local
252 v = G_MBOWNER(t4_read_reg(adap, ctl_reg)); in t4_wr_mbox_meat()
254 v = G_MBOWNER(t4_read_reg(adap, ctl_reg)); in t4_wr_mbox_meat()
262 t4_write_reg(adap, ctl_reg, F_MBMSGVALID | V_MBOWNER(X_MBOWNER_FW)); in t4_wr_mbox_meat()
263 t4_read_reg(adap, ctl_reg); /* flush write */ in t4_wr_mbox_meat()
277 v = t4_read_reg(adap, ctl_reg); in t4_wr_mbox_meat()
282 t4_write_reg(adap, ctl_reg, in t4_wr_mbox_meat()
293 t4_write_reg(adap, ctl_reg, V_MBOWNER(X_MBOWNER_NONE)); in t4_wr_mbox_meat()