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Searched refs:csr (Results 1 – 25 of 58) sorted by relevance

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/trueos/sys/sparc64/sbus/
HDlsi64854.c128 uint32_t csr; in lsi64854_attach() local
188 csr = L64854_GCSR(sc); in lsi64854_attach()
189 sc->sc_rev = csr & L64854_DEVID; in lsi64854_attach()
213 DPRINTF(LDB_ANY, (", burst 0x%x, csr 0x%x", sc->sc_burst, csr)); in lsi64854_attach()
252 uint32_t csr; \
265 csr = L64854_GCSR(sc); \
267 csr |= D_ESC_DRAIN; \
269 csr |= L64854_INVALIDATE; \
271 L64854_SCSR(sc, csr); \
282 uint32_t csr; \
[all …]
HDlsi64854var.h68 #define L64854_SCSR(sc, csr) bus_write_4((sc)->sc_res, L64854_REG_CSR, csr) argument
79 uint32_t csr = L64854_GCSR(sc); \
80 csr |= L64854_INT_EN; \
81 L64854_SCSR(sc, csr); \
87 uint32_t csr = L64854_GCSR(sc); \
88 csr |= D_EN_DMA; \
89 L64854_SCSR(sc, csr); \
HDdma_sbus.c179 uint32_t csr; in dma_attach() local
209 csr = L64854_GCSR(lsc); in dma_attach()
213 csr |= E_TP_AUI; in dma_attach()
216 csr &= ~E_TP_AUI; in dma_attach()
218 csr |= E_TP_AUI; in dma_attach()
221 L64854_SCSR(lsc, csr); in dma_attach()
/trueos/sys/powerpc/booke/
HDmachdep_e500.c55 uint32_t csr; in booke_enable_l1_cache() local
58 csr = mfspr(SPR_L1CSR0); in booke_enable_l1_cache()
59 if ((csr & L1CSR0_DCE) == 0) { in booke_enable_l1_cache()
64 csr = mfspr(SPR_L1CSR0); in booke_enable_l1_cache()
65 if ((boothowto & RB_VERBOSE) != 0 || (csr & L1CSR0_DCE) == 0) in booke_enable_l1_cache()
67 (csr & L1CSR0_DCE) ? "en" : "dis"); in booke_enable_l1_cache()
70 csr = mfspr(SPR_L1CSR1); in booke_enable_l1_cache()
71 if ((csr & L1CSR1_ICE) == 0) { in booke_enable_l1_cache()
76 csr = mfspr(SPR_L1CSR1); in booke_enable_l1_cache()
77 if ((boothowto & RB_VERBOSE) != 0 || (csr & L1CSR1_ICE) == 0) in booke_enable_l1_cache()
[all …]
HDmp_cpudep.c53 uint32_t msr, sp, csr; in cpudep_ap_bootstrap() local
56 csr = mfspr(SPR_L1CSR0); in cpudep_ap_bootstrap()
57 if ((csr & L1CSR0_DCE) == 0) { in cpudep_ap_bootstrap()
62 csr = mfspr(SPR_L1CSR1); in cpudep_ap_bootstrap()
63 if ((csr & L1CSR1_ICE) == 0) { in cpudep_ap_bootstrap()
/trueos/sys/dev/usb/controller/
HDmusb_otg.c374 uint8_t csr; in musbotg_dev_ctrl_setup_rx() local
392 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); in musbotg_dev_ctrl_setup_rx()
394 DPRINTFN(4, "csr=0x%02x\n", csr); in musbotg_dev_ctrl_setup_rx()
400 if (csr & MUSB2_MASK_CSR0L_DATAEND) { in musbotg_dev_ctrl_setup_rx()
408 if (csr & MUSB2_MASK_CSR0L_SENTSTALL) { in musbotg_dev_ctrl_setup_rx()
412 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); in musbotg_dev_ctrl_setup_rx()
416 if (csr & MUSB2_MASK_CSR0L_SETUPEND) { in musbotg_dev_ctrl_setup_rx()
421 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); in musbotg_dev_ctrl_setup_rx()
429 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) { in musbotg_dev_ctrl_setup_rx()
500 uint8_t csr, csrh; in musbotg_host_ctrl_setup_tx() local
[all …]
HDat91dci.c128 #define AT91_CSR_ACK(csr, what) do { \ argument
129 (csr) &= ~((AT91_UDP_CSR_FORCESTALL| \
132 (csr) |= ((AT91_UDP_CSR_RX_DATA_BK0| \
305 uint32_t csr; in at91dci_setup_rx() local
310 csr = AT91_UDP_READ_4(sc, td->status_reg); in at91dci_setup_rx()
312 DPRINTFN(5, "csr=0x%08x rem=%u\n", csr, td->remainder); in at91dci_setup_rx()
314 temp = csr; in at91dci_setup_rx()
321 if (!(csr & AT91_UDP_CSR_RXSETUP)) { in at91dci_setup_rx()
328 count = (csr & AT91_UDP_CSR_RXBYTECNT) >> 16; in at91dci_setup_rx()
361 csr |= AT91_UDP_CSR_DIR; in at91dci_setup_rx()
[all …]
/trueos/sys/sparc64/pci/
HDpsychoreg.h218 #define PSYCHO_GCSR_IMPL(csr) ((u_int)(((csr) >> 60) & 0xf)) argument
219 #define PSYCHO_GCSR_VERS(csr) ((u_int)(((csr) >> 56) & 0xf)) argument
220 #define PSYCHO_GCSR_MID(csr) ((u_int)(((csr) >> 51) & 0x1f)) argument
221 #define PSYCHO_GCSR_IGN(csr) ((u_int)(((csr) >> 46) & 0x1f)) argument
HDpsycho.c294 uint64_t csr, dr; in psycho_attach() local
371 csr = PSYCHO_READ8(sc, PSR_CS); in psycho_attach()
372 ver = PSYCHO_GCSR_VERS(csr); in psycho_attach()
375 sc->sc_ign = PSYCHO_GCSR_IGN(csr); in psycho_attach()
381 desc->pd_name, (u_int)PSYCHO_GCSR_IMPL(csr), ver, sc->sc_ign, in psycho_attach()
386 csr = PCICTL_READ8(sc, PCR_CS); in psycho_attach()
387 csr &= ~PCICTL_ARB_PARK; in psycho_attach()
389 csr |= PCICTL_ARB_PARK; in psycho_attach()
400 csr &= ~PCICTL_ARB_PARK; in psycho_attach()
411 csr |= PCICTL_ERRINTEN | PCICTL_ARB_4; in psycho_attach()
[all …]
/trueos/sys/dev/mk48txx/
HDmk48txx.c163 uint8_t csr; in mk48txx_gettime() local
170 csr = (*sc->sc_nvrd)(dev, clkoff + MK48TXX_ICSR); in mk48txx_gettime()
171 csr |= MK48TXX_CSR_READ; in mk48txx_gettime()
172 (*sc->sc_nvwr)(dev, clkoff + MK48TXX_ICSR, csr); in mk48txx_gettime()
205 csr = (*sc->sc_nvrd)(dev, clkoff + MK48TXX_ICSR); in mk48txx_gettime()
206 csr &= ~MK48TXX_CSR_READ; in mk48txx_gettime()
207 (*sc->sc_nvwr)(dev, clkoff + MK48TXX_ICSR, csr); in mk48txx_gettime()
223 uint8_t csr; in mk48txx_settime() local
237 csr = (*sc->sc_nvrd)(dev, clkoff + MK48TXX_ICSR); in mk48txx_settime()
238 csr |= MK48TXX_CSR_WRITE; in mk48txx_settime()
[all …]
/trueos/sys/dev/sound/sbus/
HDcs4231.c739 u_int32_t csr; in cs4231_sbus_intr() local
745 csr = APC_READ(sc, APC_CSR); in cs4231_sbus_intr()
746 if ((csr & APC_CSR_GI) == 0) { in cs4231_sbus_intr()
750 APC_WRITE(sc, APC_CSR, csr); in cs4231_sbus_intr()
752 if ((csr & APC_CSR_EIE) && (csr & APC_CSR_EI)) { in cs4231_sbus_intr()
759 if ((csr & APC_CSR_PMIE) && (csr & APC_CSR_PMI)) { in cs4231_sbus_intr()
774 if ((csr & APC_CSR_CIE) && (csr & APC_CSR_CI) && (csr & APC_CSR_CD)) { in cs4231_sbus_intr()
801 u_int32_t csr; in cs4231_ebus_pintr() local
807 csr = EBDMA_P_READ(sc, EBDMA_DCSR); in cs4231_ebus_pintr()
808 if ((csr & EBDCSR_INT) == 0) { in cs4231_ebus_pintr()
[all …]
/trueos/sys/contrib/octeon-sdk/
HDcvmx-helper.h95 chcsr_type csr; \
97 csr.u64 = cvmx_read_csr(chcsr_csr); \
99 csr.u64 = (chcsr_init); \
100 csr.chcsr_chip.chcsr_fld = (chcsr_val); \
101 cvmx_write_csr((chcsr_csr), csr.u64); \
/trueos/sys/arm/at91/
HDuart_dev_at91usart.c652 uint32_t csr; in at91_usart_bus_ipend() local
657 csr = RD4(&sc->sc_bas, USART_CSR); in at91_usart_bus_ipend()
659 if (csr & USART_CSR_OVRE) { in at91_usart_bus_ipend()
664 if (csr & USART_DCE_CHANGE_BITS) in at91_usart_bus_ipend()
667 if (csr & USART_CSR_ENDTX) { in at91_usart_bus_ipend()
672 if (csr & (USART_CSR_TXRDY | USART_CSR_ENDTX)) { in at91_usart_bus_ipend()
675 WR4(&sc->sc_bas, USART_IDR, csr & (USART_CSR_TXRDY | in at91_usart_bus_ipend()
686 if (csr & USART_CSR_RXBUFF) { in at91_usart_bus_ipend()
713 } else if (csr & USART_CSR_ENDRX) { in at91_usart_bus_ipend()
732 } else if (csr & USART_CSR_TIMEOUT) { in at91_usart_bus_ipend()
[all …]
HDat91_spi.c120 uint32_t csr; in at91_spi_attach() local
171 csr = SPI_CSR_CPOL | (4 << 16) | (0xff << 8); in at91_spi_attach()
172 WR4(sc, SPI_CSR0, csr); in at91_spi_attach()
173 WR4(sc, SPI_CSR1, csr); in at91_spi_attach()
174 WR4(sc, SPI_CSR2, csr); in at91_spi_attach()
175 WR4(sc, SPI_CSR3, csr); in at91_spi_attach()
/trueos/sys/dev/pdq/
HDpdq_freebsd.h146 #define PDQ_CSR_WRITE(csr, name, data) PDQ_OS_IOWR_32((csr)->csr_bus, (csr)->csr_base, (csr)->name… argument
147 #define PDQ_CSR_READ(csr, name) PDQ_OS_IORD_32((csr)->csr_bus, (csr)->csr_base, (csr)->name) argument
HDpdqvar.h149 #define PDQ_CSR_WRITE(csr, name, data) PDQ_OS_MEMWR_32((csr)->csr_bus, (csr)->name, 0, data) argument
150 #define PDQ_CSR_READ(csr, name) PDQ_OS_MEMRD_32((csr)->csr_bus, (csr)->name, 0) argument
/trueos/sys/dev/lmc/
HDif_lmc.h1217 # define READ_CSR(csr) bus_space_read_4 (sc->csr_tag, sc->csr_handle, csr) argument
1218 # define WRITE_CSR(csr, val) bus_space_write_4(sc->csr_tag, sc->csr_handle, csr, val) argument
1273 # define READ_CSR(csr) bus_space_read_4 (sc->csr_tag, sc->csr_handle, csr) argument
1274 # define WRITE_CSR(csr, val) bus_space_write_4(sc->csr_tag, sc->csr_handle, csr, val) argument
1302 # define READ_CSR(csr) bus_space_read_4 (sc->csr_tag, sc->csr_handle, csr) argument
1303 # define WRITE_CSR(csr, val) bus_space_write_4(sc->csr_tag, sc->csr_handle, csr, val) argument
1332 # define READ_CSR(csr) inl(sc->csr_iobase+(csr)) argument
1333 # define WRITE_CSR(csr, val) outl(sc->csr_iobase+(csr), (val)) argument
1336 # define READ_CSR(csr) (0 + *(sc->csr_membase+(csr))) argument
1337 # define WRITE_CSR(csr, val) ((void)(*(sc->csr_membase+(csr)) = (val))) argument
[all …]
HDif_lmc.c328 u_int32_t csr = READ_CSR(TLP_SROM_MII); in shift_srom_bits() local
332 csr |= TLP_SROM_DIN; /* DIN setup */ in shift_srom_bits()
334 csr &= ~TLP_SROM_DIN; /* DIN setup */ in shift_srom_bits()
335 WRITE_CSR(TLP_SROM_MII, csr); in shift_srom_bits()
336 csr |= TLP_SROM_CLK; /* CLK rising edge */ in shift_srom_bits()
337 WRITE_CSR(TLP_SROM_MII, csr); in shift_srom_bits()
338 csr &= ~TLP_SROM_CLK; /* CLK falling edge */ in shift_srom_bits()
339 WRITE_CSR(TLP_SROM_MII, csr); in shift_srom_bits()
348 u_int32_t csr; in read_srom() local
352 csr = (TLP_SROM_SEL | TLP_SROM_RD | TLP_MII_MDOE); in read_srom()
[all …]
/trueos/sys/dev/mii/
HDlxtphy.c204 int bmcr, bmsr, csr; in lxtphy_status() local
214 csr = PHY_READ(sc, MII_LXTPHY_CSR); in lxtphy_status()
215 if (csr & CSR_LINK) in lxtphy_status()
235 if (csr & CSR_SPEED) in lxtphy_status()
239 if (csr & CSR_DUPLEX) in lxtphy_status()
/trueos/sys/dev/de/
HDif_de.c1700 u_int32_t csr = TULIP_CSR_READ(sc, csr_gp); in tulip_21140_smc9332_media_probe() local
1701 …if ((csr & (TULIP_GP_SMC_9332_OK10|TULIP_GP_SMC_9332_OK100)) == (TULIP_GP_SMC_9332_OK10|TULIP_GP_S… in tulip_21140_smc9332_media_probe()
1704 } else if ((csr & TULIP_GP_SMC_9332_OK10) == 0) { in tulip_21140_smc9332_media_probe()
1802 u_int32_t csr = TULIP_CSR_READ(sc, csr_gp); in tulip_21140_znyx_zx34x_media_probe() local
1803 …if ((csr & (TULIP_GP_ZX34X_LNKFAIL|TULIP_GP_ZX34X_SYMDET|TULIP_GP_ZX34X_SIGDET)) == (TULIP_GP_ZX34… in tulip_21140_znyx_zx34x_media_probe()
1806 } else if ((csr & TULIP_GP_ZX34X_LNKFAIL) == 0) { in tulip_21140_znyx_zx34x_media_probe()
1863 #define EMIT do { TULIP_CSR_WRITE(sc, csr_srom_mii, csr); DELAY(1); } while (0)
1868 unsigned bit, csr; in tulip_srom_idle() local
1870 csr = SROMSEL ; EMIT; in tulip_srom_idle()
1871 csr = SROMSEL | SROMRD; EMIT; in tulip_srom_idle()
[all …]
/trueos/sys/arm/ti/
HDti_sdma.c220 uint32_t csr; in ti_sdma_intr() local
240 csr = ti_sdma_read_4(sc, DMA4_CSR(ch)); in ti_sdma_intr()
241 if (csr == 0) { in ti_sdma_intr()
255 if (csr & DMA4_CSR_DROP) in ti_sdma_intr()
259 if (csr & DMA4_CSR_SECURE_ERR) in ti_sdma_intr()
262 if (csr & DMA4_CSR_MISALIGNED_ADRS_ERR) in ti_sdma_intr()
265 if (csr & DMA4_CSR_TRANS_ERR) { in ti_sdma_intr()
282 channel->callback(ch, csr, channel->callback_data); in ti_sdma_intr()
586 uint32_t csr; in ti_sdma_get_channel_status() local
601 csr = ti_sdma_read_4(sc, DMA4_CSR(ch)); in ti_sdma_get_channel_status()
[all …]
/trueos/sys/dev/ppc/
HDppc.c711 int csr = SMC66x_CSR; /* initial value is 0x3F0 */ in ppc_smc37c66xgt_detect() local
716 #define cio csr+1 /* config IO port is either 0x3F1 or 0x371 */ in ppc_smc37c66xgt_detect()
722 outb(csr, SMC665_iCODE); in ppc_smc37c66xgt_detect()
723 outb(csr, SMC665_iCODE); in ppc_smc37c66xgt_detect()
726 outb(csr, 0xd); in ppc_smc37c66xgt_detect()
734 outb(csr, SMC666_iCODE); in ppc_smc37c66xgt_detect()
735 outb(csr, SMC666_iCODE); in ppc_smc37c66xgt_detect()
738 outb(csr, 0xd); in ppc_smc37c66xgt_detect()
745 csr = SMC666_CSR; in ppc_smc37c66xgt_detect()
753 outb(csr, 0xaa); /* end config mode */ in ppc_smc37c66xgt_detect()
[all …]
/trueos/sys/dev/le/
HDif_le_ledma.c219 uint32_t aui_bit, csr; in le_dma_hwreset() local
224 csr = L64854_GCSR(dma); in le_dma_hwreset()
225 aui_bit = csr & E_TP_AUI; in le_dma_hwreset()
238 csr = L64854_GCSR(dma); in le_dma_hwreset()
239 csr |= (E_DSBL_WR_INVAL | aui_bit); in le_dma_hwreset()
240 L64854_SCSR(dma, csr); in le_dma_hwreset()
/trueos/sys/arm/xscale/i80321/
HDi80321_aau.c167 int csr; in aau_bzero() local
262 while ((csr = AAU_REG_READ(sc, 0x4)) & (1 << 10)); in aau_bzero()
264 if (csr & (1 << 5)) /* error */ in aau_bzero()
269 AAU_REG_WRITE(sc, 0x4, csr); in aau_bzero()
/trueos/sys/dev/oce/
HDoce_hw.c57 post_status.dw0 = OCE_READ_CSR_MPU(sc, csr, MPU_EP_SEMAPHORE(sc)); in oce_POST()
62 OCE_WRITE_CSR_MPU(sc, csr, MPU_EP_SEMAPHORE(sc), post_status.dw0); in oce_POST()
72 post_status.dw0 = OCE_READ_CSR_MPU(sc, csr, MPU_EP_SEMAPHORE(sc)); in oce_POST()
458 ctrl.dw0 = OCE_READ_CSR_MPU(sc, csr, MPU_EP_CONTROL); in oce_pci_soft_reset()
460 OCE_WRITE_CSR_MPU(sc, csr, MPU_EP_CONTROL, ctrl.dw0); in oce_pci_soft_reset()

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