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Searched refs:clkdiv (Results 1 – 11 of 11) sorted by relevance

/trueos/sys/contrib/octeon-sdk/
HDcvmx-mpi-defs.h124 …uint64_t clkdiv : 13; /**< Fspi_clk = Fsclk / (2 * CLKDIV) … member
190 uint64_t clkdiv : 13;
197 uint64_t clkdiv : 13; /**< Fsclk = Feclk / (2 * CLKDIV) member
244 uint64_t clkdiv : 13;
251 uint64_t clkdiv : 13; /**< Fsclk = Feclk / (2 * CLKDIV) member
294 uint64_t clkdiv : 13;
302 …uint64_t clkdiv : 13; /**< Fspi_clk = Fsclk / (2 * CLKDIV) … member
361 uint64_t clkdiv : 13;
368 …uint64_t clkdiv : 13; /**< Fspi_clk = Fsclk / (2 * CLKDIV) … member
427 uint64_t clkdiv : 13;
HDcvmx-llm.c351 int clkdiv = 2; /* CN38XX is fixed at 2, CN58XX supports 2,3,4 */ in rld_csr_config_generate() local
412 clkdiv = eclk_mhz/max_llm_clock_mhz; in rld_csr_config_generate()
413 if (clkdiv * max_llm_clock_mhz < eclk_mhz) in rld_csr_config_generate()
414 clkdiv++; in rld_csr_config_generate()
416 if (clkdiv > 4) in rld_csr_config_generate()
421 if (clkdiv < 2) in rld_csr_config_generate()
422 clkdiv = 2; in rld_csr_config_generate()
424 …tf("Using llm clock divisor: %d, llm clock is: %lu MHz\n", clkdiv, (unsigned long)eclk_mhz/clkdiv); in rld_csr_config_generate()
431 if (clkdiv == 2) in rld_csr_config_generate()
434 clkdiv_enc = clkdiv - 1; in rld_csr_config_generate()
[all …]
HDcvmx-dfa-defs.h3499 uint64_t clkdiv : 2; /**< RLDCLK Divisor Select member
3774 uint64_t clkdiv : 2;
/trueos/sys/arm/ti/am335x/
HDam335x_pwm.c255 int clkdiv; in am335x_pwm_freq() local
257 clkdiv = am335x_pwm_clkdiv[sc->sc_pwm_clkdiv]; in am335x_pwm_freq()
258 sc->sc_pwm_freq = PWM_CLOCK / (1 * clkdiv) / sc->sc_pwm_period; in am335x_pwm_freq()
264 int clkdiv, error, freq, i, period; in am335x_pwm_sysctl_freq() local
284 clkdiv = am335x_pwm_clkdiv[i]; in am335x_pwm_sysctl_freq()
285 period = PWM_CLOCK / clkdiv / freq; in am335x_pwm_sysctl_freq()
313 int error, i, clkdiv; in am335x_pwm_sysctl_clkdiv() local
320 clkdiv = am335x_pwm_clkdiv[sc->sc_pwm_clkdiv]; in am335x_pwm_sysctl_clkdiv()
323 error = sysctl_handle_int(oidp, &clkdiv, sizeof(clkdiv), req); in am335x_pwm_sysctl_clkdiv()
328 if (clkdiv != am335x_pwm_clkdiv[sc->sc_pwm_clkdiv]) { in am335x_pwm_sysctl_clkdiv()
[all …]
/trueos/sys/arm/ti/
HDti_sdhci.c164 uint32_t clkdiv, val32; in ti_sdhci_read_2() local
181 clkdiv = ((val32 >> MMCHS_SYSCTL_CLKD_SHIFT) & in ti_sdhci_read_2()
184 val32 |= (clkdiv & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT; in ti_sdhci_read_2()
186 val32 |= ((clkdiv >> SDHCI_DIVIDER_MASK_LEN) & in ti_sdhci_read_2()
255 uint32_t clkdiv, val32; in ti_sdhci_write_2() local
263 clkdiv = (val >> SDHCI_DIVIDER_SHIFT) & SDHCI_DIVIDER_MASK; in ti_sdhci_write_2()
265 clkdiv |= ((val >> SDHCI_DIVIDER_HI_SHIFT) & in ti_sdhci_write_2()
267 clkdiv *= 2; in ti_sdhci_write_2()
268 if (clkdiv > MMCHS_SYSCTL_CLKD_MASK) in ti_sdhci_write_2()
269 clkdiv = MMCHS_SYSCTL_CLKD_MASK; in ti_sdhci_write_2()
[all …]
HDti_mmchs.c967 uint32_t clkdiv; in ti_mmchs_update_ios() local
1077 clkdiv = 0; in ti_mmchs_update_ios()
1079 clkdiv = sc->sc_ref_freq / ios->clock; in ti_mmchs_update_ios()
1080 if (clkdiv < 1) in ti_mmchs_update_ios()
1081 clkdiv = 1; in ti_mmchs_update_ios()
1082 if ((sc->sc_ref_freq / clkdiv) > ios->clock) in ti_mmchs_update_ios()
1083 clkdiv += 1; in ti_mmchs_update_ios()
1084 if (clkdiv > 250) in ti_mmchs_update_ios()
1085 clkdiv = 250; in ti_mmchs_update_ios()
1090 sysctl_reg |= MMCHS_SYSCTL_CLKD(clkdiv); in ti_mmchs_update_ios()
/trueos/sys/arm/lpc/
HDlpc_mmc.c641 uint32_t clkdiv = 0, pwr = 0; in lpc_mmc_update_ios() local
644 clkdiv |= LPC_SD_CLOCK_WIDEBUS; in lpc_mmc_update_ios()
647 clkdiv = (LPC_SD_CLK / (2 * ios->clock)) - 1; in lpc_mmc_update_ios()
650 if ((LPC_SD_CLK / (2 * (clkdiv + 1))) > ios->clock) in lpc_mmc_update_ios()
651 clkdiv++; in lpc_mmc_update_ios()
653 debugf("clock: %dHz, clkdiv: %d\n", ios->clock, clkdiv); in lpc_mmc_update_ios()
657 clkdiv |= LPC_SD_CLOCK_WIDEBUS; in lpc_mmc_update_ios()
660 lpc_mmc_write_4(sc, LPC_SD_CLOCK, clkdiv | LPC_SD_CLOCK_ENABLE); in lpc_mmc_update_ios()
/trueos/sys/gnu/dts/arm/
HDemev2.dtsi77 compatible = "renesas,emev2-smu-clkdiv";
83 compatible = "renesas,emev2-smu-clkdiv";
89 compatible = "renesas,emev2-smu-clkdiv";
95 compatible = "renesas,emev2-smu-clkdiv";
/trueos/sys/arm/at91/
HDat91_mci.c561 uint32_t clkdiv; in at91_mci_update_ios() local
581 clkdiv = 0; in at91_mci_update_ios()
585 clkdiv = ((at91_master_clock / ios->clock) / 2) - 1; in at91_mci_update_ios()
587 clkdiv = (at91_master_clock / ios->clock) / 2; in at91_mci_update_ios()
588 freq = at91_master_clock / ((clkdiv+1) * 2); in at91_mci_update_ios()
589 if (clkdiv == 1 && ios->clock == 25000000 && freq <= 15000000) { in at91_mci_update_ios()
591 clkdiv = 0; in at91_mci_update_ios()
592 freq = at91_master_clock / ((clkdiv+1) * 2); in at91_mci_update_ios()
601 WR4(sc, MCI_MR, (RD4(sc, MCI_MR) & ~MCI_MR_CLKDIV) | clkdiv); in at91_mci_update_ios()
/trueos/sys/arm/freescale/imx/
HDimx_i2c.c91 struct clkdiv { struct
95 static struct clkdiv clkdiv_table[] = { argument
/trueos/sys/dev/cxgb/common/
HDcxgb_t3_hw.c252 u32 clkdiv = adap->params.vpd.cclk / (2 * adap->params.vpd.mdc) - 1; in mi1_init() local
253 u32 val = F_PREEN | V_CLKDIV(clkdiv); in mi1_init()