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Searched refs:cfg1 (Results 1 – 17 of 17) sorted by relevance

/trueos/sys/mips/mips/
HDcpu.c75 u_int32_t cfg1; in mips_get_identity() local
101 cfg1 = mips_rd_config1(); in mips_get_identity()
121 ((cfg1 & MIPS_CONFIG1_TLBSZ_MASK) >> MIPS_CONFIG1_TLBSZ_SHIFT) + 1; in mips_get_identity()
134 tmp = (cfg1 & MIPS_CONFIG1_IL_MASK) >> MIPS_CONFIG1_IL_SHIFT; in mips_get_identity()
137 cpuinfo->l1.ic_nways = (((cfg1 & MIPS_CONFIG1_IA_MASK) >> MIPS_CONFIG1_IA_SHIFT)) + 1; in mips_get_identity()
139 1 << (((cfg1 & MIPS_CONFIG1_IS_MASK) >> MIPS_CONFIG1_IS_SHIFT) + 6); in mips_get_identity()
148 tmp = (cfg1 & MIPS_CONFIG1_DL_MASK) >> MIPS_CONFIG1_DL_SHIFT; in mips_get_identity()
152 (((cfg1 & MIPS_CONFIG1_DA_MASK) >> MIPS_CONFIG1_DA_SHIFT)) + 1; in mips_get_identity()
154 1 << (((cfg1 & MIPS_CONFIG1_DS_MASK) >> MIPS_CONFIG1_DS_SHIFT) + 6); in mips_get_identity()
212 uint32_t cfg0, cfg1, cfg2, cfg3; in cpu_identify() local
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/trueos/sys/dev/ata/chipsets/
HData-nvidia.c184 if ((ctlr->chip->cfg1 & NVAHCI) && in ata_nvidia_probe()
185 ((force_ahci == 1 && (ctlr->chip->cfg1 & NVNOFORCE) == 0) || in ata_nvidia_probe()
201 if (ctlr->chip->cfg1 & NVAHCI) { in ata_nvidia_chipinit()
212 int offset = ctlr->chip->cfg1 & NV4 ? 0x0440 : 0x0010; in ata_nvidia_chipinit()
222 if (ctlr->chip->cfg1 & NVQ) { in ata_nvidia_chipinit()
291 int offset = ctlr->chip->cfg1 & NV4 ? 0x0440 : 0x0010; in ata_nvidia_status()
292 int shift = ch->unit << (ctlr->chip->cfg1 & NVQ ? 4 : 2); in ata_nvidia_status()
296 if (ctlr->chip->cfg1 & NVQ) in ata_nvidia_status()
306 if (ctlr->chip->cfg1 & NVQ) in ata_nvidia_status()
HData-highpoint.c96 if (idx->cfg1 == HPT_374) { in ata_highpoint_probe()
130 if (ctlr->chip->cfg1 < HPT_372) in ata_highpoint_chipinit()
153 if (ctlr->chip->cfg1 == HPT_366) in ata_highpoint_ch_attach()
193 timings33[ata_mode2idx(mode)][ctlr->chip->cfg1], 4); in ata_highpoint_setmode()
205 if (ctlr->chip->cfg1 == HPT_374 && pci_get_function(parent) == 1) { in ata_highpoint_check_80pin()
HData-sis.c124 id[0].cfg1 = SIS_133NEW; in ata_sis_probe()
138 id[0].cfg1 = SIS_133OLD; in ata_sis_probe()
141 id[0].cfg1 = SIS_100NEW; in ata_sis_probe()
168 switch (ctlr->chip->cfg1) { in ata_sis_chipinit()
248 if (ctlr->chip->cfg1 == SIS_133NEW) { in ata_sis_setmode()
262 switch (ctlr->chip->cfg1) { in ata_sis_setmode()
HData-amd.c97 if (ctlr->chip->cfg1 & AMD_BUG) in ata_amd_chipinit()
122 if (ctlr->chip->cfg1 & AMD_CABLE) { in ata_amd_setmode()
152 if (ctlr->chip->cfg1 & AMD_CABLE) in ata_amd_ch_attach()
HData-serverworks.c132 if (ctlr->chip->cfg1 == SWKS_MIO) { in ata_serverworks_chipinit()
147 else if (ctlr->chip->cfg1 == SWKS_33) { in ata_serverworks_chipinit()
167 (ctlr->chip->cfg1 == SWKS_100) ? 0x03 : 0x02, 1); in ata_serverworks_chipinit()
360 if (ctlr->chip->cfg1 != SWKS_33) { in ata_serverworks_setmode()
HData-intel.c333 if ((ctlr->chip->cfg1 & INTEL_AHCI) && in ata_intel_chipinit()
339 if ((ctlr->chip->cfg1 & INTEL_ICH7)) { in ata_intel_chipinit()
361 (ctlr->chip->cfg1 & INTEL_ICH5)) in ata_intel_chipinit()
408 if (ctlr->chip->cfg1 & INTEL_ICH5) { in ata_intel_ch_attach()
424 } else if (ctlr->chip->cfg1 & INTEL_6CH2) { in ata_intel_ch_attach()
446 if ((ctlr->chip->cfg1 & INTEL_ICH5)) { in ata_intel_ch_attach()
450 if ((ctlr->chip->cfg1 & INTEL_ICH7)) { in ata_intel_ch_attach()
501 if (ctlr->chip->cfg1 & (INTEL_6CH | INTEL_6CH2)) in ata_intel_reset()
HData-via.c256 ch->r_io[ATA_SSTATUS].offset = (ch->unit << ctlr->chip->cfg1); in ata_via_ch_attach()
258 ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << ctlr->chip->cfg1); in ata_via_ch_attach()
260 ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << ctlr->chip->cfg1); in ata_via_ch_attach()
370 modes[ctlr->chip->cfg1][mode & ATA_MODE_MASK], 1); in ata_via_old_setmode()
HData-ati.c109 switch (ctlr->chip->cfg1) { in ata_ati_probe()
139 if (ctlr->chip->cfg1 == ATI_AHCI) { in ata_ati_chipinit()
HData-jmicron.c119 if (ctlr->chip->cfg1) { in ata_jmicron_chipinit()
HData-marvell.c154 if (ctlr->chip->cfg1) { in ata_marvell_chipinit()
233 ctlr->channels = ctlr->chip->cfg1; in ata_marvell_edma_chipinit()
237 if (ctlr->chip->cfg1 > 4) in ata_marvell_edma_chipinit()
HData-acard.c99 if (ctlr->chip->cfg1 == ATP_OLD) { in ata_acard_chipinit()
HData-promise.c224 switch (ctlr->chip->cfg1) { in ata_promise_chipinit()
375 if (ctlr->chip->cfg1 == PR_NEW) { in ata_promise_ch_attach()
480 switch (ctlr->chip->cfg1) { in ata_promise_setmode()
511 if (ctlr->chip->cfg1 < PR_TX) in ata_promise_setmode()
513 timings[ata_mode2idx(mode)][ctlr->chip->cfg1], 4); in ata_promise_setmode()
HData-acerlabs.c114 ctlr->channels = ctlr->chip->cfg1; in ata_ali_chipinit()
HData-siliconimage.c127 switch (ctlr->chip->cfg1) { in ata_sii_chipinit()
/trueos/sys/dev/et/
HDif_et.c504 uint32_t cfg1, cfg2, ctrl; in et_miibus_statchg() local
537 cfg1 = CSR_READ_4(sc, ET_MAC_CFG1); in et_miibus_statchg()
538 cfg1 &= ~(ET_MAC_CFG1_TXFLOW | ET_MAC_CFG1_RXFLOW | in et_miibus_statchg()
569 cfg1 |= ET_MAC_CFG1_TXFLOW; in et_miibus_statchg()
572 cfg1 |= ET_MAC_CFG1_RXFLOW; in et_miibus_statchg()
578 cfg1 |= ET_MAC_CFG1_TXEN | ET_MAC_CFG1_RXEN; in et_miibus_statchg()
579 CSR_WRITE_4(sc, ET_MAC_CFG1, cfg1); in et_miibus_statchg()
584 cfg1 = CSR_READ_4(sc, ET_MAC_CFG1); in et_miibus_statchg()
585 if ((cfg1 & (ET_MAC_CFG1_SYNC_TXEN | ET_MAC_CFG1_SYNC_RXEN)) == in et_miibus_statchg()
/trueos/sys/dev/ata/
HData-pci.h33 int cfg1; member