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/trueos/contrib/gcc/config/i386/
HDathlon.md3 ;; The Athlon does contain three pipelined FP units, three integer units and
10 ;; Three DirectPath instructions decoders and only one VectorPath decoder
15 ;; it to the specialized integer (18 entry) and fp (36 entry) schedulers.
23 (and (eq_attr "type" "push")
26 (and (eq_attr "type" "fmov")
27 (and (eq_attr "memory" "load,store")
54 ;; to decode when decoder2 and decoder0 in next cycle
59 ;; and other units, we model decoder as two stage fully pipelined unit
60 ;; and only double decoded instruction may occupy unit in the first cycle.
66 ;; We solve that by specialized vector decoder unit and exclusion set.
[all …]
HDppro.md6 ;; GCC is free software; you can redistribute it and/or modify
22 ;; and Xeon lines of CPUs. The DFA scheduler description in this file is
39 ;; So, the P6 CPUs have out-of-order cores, but the instruction decoder and
62 ;; - Figure out where the p0 and p1 reservations come from. These
67 ;; The ppro_idiv and ppro_fdiv automata are used to model issue
68 ;; latencies of idiv and fdiv type insns.
73 ;; two uops, and simple read-modify instructions also take two uops.
82 ;; decoder 0, and this takes an unspecified number of cycles.
91 ;; decoder1 and decoder2 from being reserved until decoder 0 is
127 ;; reg-reg operation, 1 uop per load on port 2. and 2 uops per store
[all …]
HDk6.md7 ;; GCC is free software; you can redistribute it and/or modify
23 ;; that there are only two decoders and they seems to be much slower than
40 ;; completely and it is only used to model lea operation.
51 ;; The fp unit is not pipelined, and it can only do one operation per two
55 ;; the old description, and a lot easier to extend to something more
66 ;; purposes, the long and vector decoder can be modelled as one decoder.
80 ;; Shift instructions and certain arithmetic are issued only on Integer X.
82 (and (eq_attr "cpu" "k6")
83 (and (eq_attr "type" "ishift,ishift1,rotate,rotate1,alu1,negnot,cld")
88 (and (eq_attr "cpu" "k6")
[all …]
HDpentium.md6 ;; GCC is free software; you can redistribute it and/or modify
36 ;; and doesn't hurt much on MMX. (Prefixed instructions are not very
43 (and (eq_attr "type" "pop,push")
50 (and (eq_attr "type" "ishift")
53 (and (eq_attr "type" "rotate")
56 (and (eq_attr "type" "ishift1")
59 (and (eq_attr "type" "rotate1")
62 (and (eq_attr "type" "call")
65 (and (eq_attr "type" "callv")
73 ;; Pentium do have U and V pipes. Instruction to both pipes
[all …]
HDgeode.md7 ;; GCC is free software; you can redistribute it and/or modify
40 ;; There is also memory management unit and execution pipeline for
41 ;; load/store operations. We ignore it and difference between insns
42 ;; using memory and registers.
49 (and (eq_attr "cpu" "geode")
54 (and (eq_attr "cpu" "geode")
59 (and (eq_attr "cpu" "geode")
64 (and (eq_attr "cpu" "geode")
70 (and (eq_attr "cpu" "geode")
75 (and (eq_attr "cpu" "geode")
[all …]
/trueos/contrib/dialog/samples/
HDwheel27 --begin `scaley 27` `scalex 98` --infobox "pushd /var/log >/dev/null" 0 0 --and-widget \
28 --begin `scaley 35` `scalex 95` --infobox "mkdir -p news -m 755" 0 0 --and-widget \
29 --begin `scaley 45` `scalex 86` --infobox "chown news.news news" 0 0 --and-widget \
30 --begin `scaley 48` `scalex 78` --infobox "cd /var/log/news" 0 0 --and-widget \
31 --begin `scaley 51` `scalex 61` --infobox "mkdir -p OLD -m 755" 0 0 --and-widget \
32 --begin `scaley 52` `scalex 47` --infobox "chown news.news OLD" 0 0 --and-widget \
33 --begin `scaley 51` `scalex 40` --infobox "cd /var/spool" 0 0 --and-widget \
34 --begin `scaley 48` `scalex 25` --infobox "mkdir -p news -m 775" 0 0 --and-widget \
35 --begin `scaley 42` `scalex 13` --infobox "chown news.news news" 0 0 --and-widget \
36 --begin `scaley 35` `scalex 4` --infobox "cd /var/spool/news" 0 0 --and-widget \
[all …]
/trueos/contrib/gcc/config/mips/
HD5500.md19 (and (eq_attr "cpu" "r5500")
25 (and (eq_attr "cpu" "r5500")
30 (and (eq_attr "cpu" "r5500")
40 (and (eq_attr "cpu" "r5500")
47 (and (eq_attr "cpu" "r5500")
53 (and (eq_attr "cpu" "r5500")
58 (and (eq_attr "cpu" "r5500")
68 (and (eq_attr "cpu" "r5500")
73 (and (eq_attr "cpu" "r5500")
80 (and (eq_attr "cpu" "r5500")
[all …]
HD5400.md17 (and (eq_attr "cpu" "r5400")
23 (and (eq_attr "cpu" "r5400")
28 (and (eq_attr "cpu" "r5400")
33 (and (eq_attr "cpu" "r5400")
38 (and (eq_attr "cpu" "r5400")
46 (and (eq_attr "cpu" "r5400")
52 (and (eq_attr "cpu" "r5400")
57 (and (eq_attr "cpu" "r5400")
62 (and (eq_attr "cpu" "r5400")
67 (and (eq_attr "cpu" "r5400")
[all …]
HDsb1.md7 ;; pipes, and 1 MDMX pipes. It can issue 2 ls insns and 2 exe/fpu/mdmx insns
13 ;; simple alu operations issue to ls1 if it is still available, and their
21 ;; In 32-bit mode, dependent FP can't co-issue with load, and only one FP exe
44 ;; The divide unit is not pipelined, and blocks hi/lo reads and writes.
53 ;; Can only issue to one of the ex and fp pipes at a time.
58 ;; We can use 2 FP pipes only if we have 64-bit FP code, and exceptions are
62 (cond [(and (ne (symbol_ref "TARGET_FLOAT64") (const_int 0))
78 ;; ??? Try limiting scheduler to 2 long latency operations, and see if this
79 ;; results in a usable DFA, and whether it helps code performance.
93 (and (eq_attr "cpu" "sb1,sb1a")
[all …]
HD5k.md3 ;; and Nigel Stephens (nigel@mips.com)
17 ;; GCC is free software; you can redistribute it and/or modify it
40 (and (eq_attr "cpu" "5kc,5kf")
45 (and (eq_attr "cpu" "5kc,5kf")
50 (and (eq_attr "cpu" "5kc,5kf")
56 (and (eq_attr "cpu" "5kc,5kf")
57 (and (eq_attr "type" "idiv")
62 (and (eq_attr "cpu" "5kc,5kf")
63 (and (eq_attr "type" "idiv")
70 (and (eq_attr "cpu" "5kc,5kf")
[all …]
HD9000.md6 ;; GCC is free software; you can redistribute it and/or modify it
29 ;; F and M pipe units, for instructions that must be issued by a
44 (and (eq_attr "cpu" "r9000")
49 (and (eq_attr "cpu" "r9000")
54 (and (eq_attr "cpu" "r9000")
59 (and (eq_attr "cpu" "r9000")
60 (and (eq_attr "type" "condmove")
64 ;; This applies to both 'mul' and 'mult'.
66 (and (eq_attr "cpu" "r9000")
67 (and (eq_attr "type" "imul,imul3,imadd")
[all …]
HD24k.md3 ;; and David Ung (davidu@mips.com)
15 ;; GCC is free software; you can redistribute it and/or modify it
45 (and (eq_attr "cpu" "24k,24kx")
50 ;; 2. Arithmetic: add, addi, addiu, addiupc, addu, and, andi, clo, clz,
57 (and (eq_attr "cpu" "24k,24kx")
65 (and (eq_attr "cpu" "24k,24kx")
71 (and (eq_attr "cpu" "24k,24kx")
79 (and (eq_attr "cpu" "24k,24kx")
85 (and (eq_attr "cpu" "24k,24kx")
91 (and (eq_attr "cpu" "24k,24kx")
[all …]
HD7000.md6 ;; GCC is free software; you can redistribute it and/or modify it
90 (and (eq_attr "cpu" "r7000")
95 (and (eq_attr "cpu" "r7000")
100 (and (eq_attr "cpu" "r7000")
105 (and (eq_attr "cpu" "r7000")
106 (and (eq_attr "type" "idiv")
111 (and (eq_attr "cpu" "r7000")
112 (and (eq_attr "type" "idiv")
117 (and (eq_attr "cpu" "r7000")
118 (and (eq_attr "type" "imul,imadd")
[all …]
HDsr71k.md14 ;; published latencies. Emulation of out-of-order issue and the insn
34 ;; Yes, all the instructions in Table 19-1 only go to ALUX, and all the
48 ;; Floating point stores go to Ld/St and go to MOV in the floating point
51 ;; Floating point loads go to Ld/St and go to LOAD in the floating point
58 ;; RH> What about for RSQRT single and double?
60 ;; The latency/repeat for RECIP and RSQRT are correct.
64 ;; Use four automata to isolate long latency operations, and to
69 ;; feeders for CPU function units and feeders for fpu (CP1 interface)
128 (and (eq_attr "cpu" "sr71000")
135 (and (eq_attr "cpu" "sr71000")
[all …]
HD4300.md6 ;; GCC is free software; you can redistribute it and/or modify it
26 (and (eq_attr "cpu" "r4300")
31 (and (eq_attr "cpu" "r4300")
32 (and (eq_attr "type" "imul,imul3,imadd")
37 (and (eq_attr "cpu" "r4300")
38 (and (eq_attr "type" "imul,imul3,imadd")
43 (and (eq_attr "cpu" "r4300")
44 (and (eq_attr "type" "idiv")
49 (and (eq_attr "cpu" "r4300")
50 (and (eq_attr "type" "idiv")
[all …]
HD4k.md3 ;; and David Ung (davidu@mips.com)
9 ;; 4Kc - pipelined multiplier and translation lookaside buffer (TLB)
10 ;; 4km - pipelined multiplier and block address translator (BAT)
11 ;; 4kp - non-pipelined multiplier and block address translator (BAT)
17 ;; GCC is free software; you can redistribute it and/or modify it
39 (and (eq_attr "cpu" "4kc,4kp")
44 (and (eq_attr "cpu" "4kc,4kp")
49 (and (eq_attr "cpu" "4kc,4kp")
57 (and (eq_attr "cpu" "4kc")
58 (and (eq_attr "type" "idiv")
[all …]
/trueos/contrib/gcc/config/arm/
HDarm-generic.md6 ;; GCC is free software; you can redistribute it and/or modify it
28 ; There is room in the buffer for up to two addresses and up to eight words
32 ; It is normally the case that FCLK and MCLK will be in the ratio 2:1, so
33 ; writes will take 2 FCLK cycles per word, if FCLK and MCLK are asynchronous
42 ; The f_mem_r and r_mem_f could also block, but they are to the stack,
51 (and (eq_attr "generic_sched" "yes")
52 (and (eq_attr "model_wbuf" "yes")
57 (and (eq_attr "generic_sched" "yes")
58 (and (eq_attr "model_wbuf" "yes")
63 (and (eq_attr "generic_sched" "yes")
[all …]
/trueos/contrib/gcc/doc/
HDcontrib.texi21 and iterators.
24 John David Anglin for threading-related fixes and improvements to
25 libstdc++-v3, and the HP-UX port.
32 Abramo and Roberto Bagnara for the SysV68 Motorola 3300 Delta Series
49 Godmar Back for his Java improvements and encouragement.
65 Geoff Berry for his Java object serialization work and various patches.
68 Uros Bizjak for the implementation of x87 math built-in functions and
69 for various middle end and i386 back end improvements and bugfixes.
72 Eric Blake for helping to make GCJ and libgcj conform to the
83 garbage collector}, IA-64 libffi port, and other Java work.
[all …]
/trueos/contrib/gcc/config/rs6000/
HD6xx.md2 ;; and PowerPC 630 processors.
7 ;; GCC is free software; you can redistribute it and/or modify it
30 ;; MCIU used for imul/idiv and moves from/to spr
35 ;; PPC604e is PPC604 with larger caches and a CRU. In the 604
52 (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u")
57 (and (eq_attr "type" "fpload,fpload_ux,fpload_u")
62 (and (eq_attr "type" "store,fpstore,store_ux,store_u,fpstore_ux,fpstore_u")
67 (and (eq_attr "type" "load_l,store_c")
72 (and (eq_attr "type" "load_l,store_c")
77 (and (eq_attr "type" "integer,insert_word")
[all …]
HDrios1.md6 ;; GCC is free software; you can redistribute it and/or modify it
29 (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\
35 (and (eq_attr "type" "store,store_ux,store_u")
40 (and (eq_attr "type" "fpload,fpload_ux,fpload_u")
45 (and (eq_attr "type" "fpload,fpload_ux,fpload_u")
50 (and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u")
55 (and (eq_attr "type" "integer,insert_word")
60 (and (eq_attr "type" "two")
65 (and (eq_attr "type" "three")
70 (and (eq_attr "type" "imul,imul_compare")
[all …]
HDrs64.md6 ;; GCC is free software; you can redistribute it and/or modify it
30 (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u")
35 (and (eq_attr "type" "store,store_ux,store_u,fpstore,fpstore_ux,fpstore_u")
40 (and (eq_attr "type" "fpload,fpload_ux,fpload_u")
45 (and (eq_attr "type" "load_l,store_c")
50 (and (eq_attr "type" "integer,insert_word")
55 (and (eq_attr "type" "two")
60 (and (eq_attr "type" "three")
65 (and (eq_attr "type" "imul,imul_compare")
70 (and (eq_attr "type" "imul2")
[all …]
/trueos/contrib/gcc/config/sparc/
HDultra1_2.md6 ;; GCC is free software; you can redistribute it and/or modify
21 ;; UltraSPARC-I and II are quad-issue processors. Interesting features
27 ;; - Two integer units. Only one of them can do shifts, and the other
31 ;; setting instruction and one that does set the condition codes. The
61 ;; If we have to schedule an ieu1 specific instruction and we want
74 ;; execute in the first three slots, FPU and branches can go into
82 (and (eq_attr "cpu" "ultrasparc")
87 (and (eq_attr "cpu" "ultrasparc")
92 (and (eq_attr "cpu" "ultrasparc")
97 (and (eq_attr "cpu" "ultrasparc")
[all …]
/trueos/contrib/binutils/gas/
HDCONTRIBUTORS3 If you've contributed to gas and your name isn't listed here, it is
5 nickc@redhat.com and I'll correct the situation.
8 the documentation, and info on specific files will go into an AUTHORS
16 gdb-specific debug information and the 68k series machines, most of
17 the preprocessing pass, and extensive changes in messages.c,
21 enhancements and many bug fixes, including merging support for several
24 and b.out backends), adding configuration including heavy testing and
25 verification of cross assemblers and file splits and renaming,
29 sparc opcode file rewrite, decstation, rs6000, and hp300hpux host
30 ports, updated "know" assertions and made them work, much other
[all …]
/trueos/contrib/nvi/docs/internals/
HDautowrite11 ^Z Y Y Write file and suspend.
16 ^^ Y Y Write file and jump.
21 # This behavior is identical to :tag, :tagpop, and :tagpush with
23 ^] Y Y Write file and jump.
28 :! Y Y Write file and execute.
29 :! Y N Warn (if warn option) and execute.
33 Commands that are affected by both autowrite and force:
42 # In nvi, :next and :prev commands behave identically to :rewind.
43 :next Y Y Y Write changes and jump.
44 :next Y Y N Write changes and jump.
[all …]
/trueos/crypto/openssl/
HDNEWS8 Major changes between OpenSSL 1.0.1n and OpenSSL 1.0.1o [12 Jun 2015]
12 Major changes between OpenSSL 1.0.1m and OpenSSL 1.0.1n [11 Jun 2015]
20 Major changes between OpenSSL 1.0.1l and OpenSSL 1.0.1m [19 Mar 2015]
30 Major changes between OpenSSL 1.0.1k and OpenSSL 1.0.1l [15 Jan 2015]
32 o Build fixes for the Windows and OpenVMS platforms
34 Major changes between OpenSSL 1.0.1j and OpenSSL 1.0.1k [8 Jan 2015]
45 Major changes between OpenSSL 1.0.1i and OpenSSL 1.0.1j [15 Oct 2014]
52 Major changes between OpenSSL 1.0.1h and OpenSSL 1.0.1i [6 Aug 2014]
64 Major changes between OpenSSL 1.0.1g and OpenSSL 1.0.1h [5 Jun 2014]
73 Major changes between OpenSSL 1.0.1f and OpenSSL 1.0.1g [7 Apr 2014]
[all …]

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