Searched refs:Tmp6 (Results 1 – 5 of 5) sorted by relevance
| /trueos/contrib/llvm/lib/CodeGen/ |
| HD | IntrinsicLowering.cpp | 208 Value *Tmp6 = Builder.CreateShl(V, ConstantInt::get(V->getType(), 24), in LowerBSWAP() local
227 Tmp6 = Builder.CreateAnd(Tmp6, in LowerBSWAP()
248 Tmp6 = Builder.CreateOr(Tmp6, Tmp5, "bswap.or2"); in LowerBSWAP()
251 Tmp8 = Builder.CreateOr(Tmp8, Tmp6, "bswap.or5"); in LowerBSWAP()
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| /trueos/contrib/llvm/tools/clang/lib/CodeGen/ |
| HD | CGExprComplex.cpp | 589 llvm::Value *Tmp6 = Builder.CreateFAdd(Tmp4, Tmp5); // cc+dd in EmitBinDiv() local
595 DSTr = Builder.CreateFDiv(Tmp3, Tmp6); in EmitBinDiv()
596 DSTi = Builder.CreateFDiv(Tmp9, Tmp6); in EmitBinDiv()
605 llvm::Value *Tmp6 = Builder.CreateAdd(Tmp4, Tmp5); // cc+dd in EmitBinDiv() local
612 DSTr = Builder.CreateUDiv(Tmp3, Tmp6); in EmitBinDiv()
613 DSTi = Builder.CreateUDiv(Tmp9, Tmp6); in EmitBinDiv()
615 DSTr = Builder.CreateSDiv(Tmp3, Tmp6); in EmitBinDiv()
616 DSTi = Builder.CreateSDiv(Tmp9, Tmp6); in EmitBinDiv()
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| /trueos/contrib/llvm/lib/Transforms/Utils/ |
| HD | IntegerDivision.cpp | 268 Value *Tmp6 = Builder.CreateLShr(Q_2, ThirtyOne); in generateUnsignedDivisionCode() local
269 Value *Tmp7 = Builder.CreateOr(Tmp5, Tmp6); in generateUnsignedDivisionCode()
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| /trueos/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| HD | LegalizeDAG.cpp | 2533 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; in ExpandBSWAP() local
2553 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT)); in ExpandBSWAP()
2560 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT)); in ExpandBSWAP()
2566 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5); in ExpandBSWAP()
2569 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6); in ExpandBSWAP()
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| /trueos/contrib/llvm/lib/Target/PowerPC/ |
| HD | PPCISelLowering.cpp | 5075 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5); in LowerSHL_PARTS() local
5076 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6); in LowerSHL_PARTS()
5104 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5); in LowerSRL_PARTS() local
5105 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6); in LowerSRL_PARTS()
5132 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5); in LowerSRA_PARTS() local
5135 Tmp4, Tmp6, ISD::SETLE); in LowerSRA_PARTS()
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