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Searched refs:T8XS (Results 1 – 8 of 8) sorted by relevance

/trueos/contrib/llvm/utils/TableGen/
HDX86RecognizableInstr.cpp82 A6 = 15, A7 = 16, T8XD = 17, T8XS = 18, TAXD = 19, enumerator
325 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS) in insnContext()
336 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS) in insnContext()
348 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS) in insnContext()
362 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS) in insnContext()
371 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS) in insnContext()
385 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS) in insnContext()
394 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS) in insnContext()
408 (Prefix == X86Local::XS || Prefix == X86Local::T8XS)) in insnContext()
415 (Prefix == X86Local::XS || Prefix == X86Local::T8XS)) in insnContext()
[all …]
/trueos/contrib/llvm/lib/Target/X86/MCTargetDesc/
HDX86BaseInfo.h346 T8XS = 18 << Op0Shift, enumerator
HDX86MCCodeEmitter.cpp645 case X86II::T8XS: // F3 0F 38 in EmitVEXOpcodePrefix()
1127 case X86II::T8XS: // F3 0F 38 in EmitOpcodePrefix()
1170 case X86II::T8XS: // F3 0F 38 in EmitOpcodePrefix()
/trueos/contrib/llvm/lib/Target/X86/
HDX86CodeEmitter.cpp703 case X86II::T8XS: // F3 0F 38 in emitOpcodePrefix()
736 case X86II::T8XS: // F3 0F 38 in emitOpcodePrefix()
899 case X86II::T8XS: // F3 0F 38 in emitVEXOpcodePrefix()
HDX86InstrArithmetic.td1379 [], IIC_BIN_NONMEM>, T8XS;
1383 [], IIC_BIN_NONMEM>, T8XS, REX_W, Requires<[In64BitMode]>;
1389 [], IIC_BIN_MEM>, T8XS;
1393 [], IIC_BIN_MEM>, T8XS, REX_W, Requires<[In64BitMode]>;
HDX86InstrFormats.td138 class T8XS { bits<5> Prefix = 18; }
621 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8XS,
HDX86InstrShiftRotate.td904 defm SARX32 : bmi_shift<"sarx{l}", GR32, i32mem>, T8XS;
905 defm SARX64 : bmi_shift<"sarx{q}", GR64, i64mem>, T8XS, VEX_W;
HDX86InstrInfo.td1915 int_x86_bmi_pext_32, loadi32>, T8XS;
1917 int_x86_bmi_pext_64, loadi64>, T8XS, VEX_W;