Searched refs:SubReg1 (Results 1 – 3 of 3) sorted by relevance
| /trueos/contrib/llvm/lib/Target/R600/ |
| HD | AMDGPUISelDAGToDAG.cpp | 291 SDValue RC, SubReg0, SubReg1; in Select() local
299 SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub2_sub3, MVT::i32); in Select()
303 SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub1, MVT::i32); in Select()
308 N->getOperand(1), SubReg1 }; in Select()
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| /trueos/contrib/llvm/lib/CodeGen/ |
| HD | TargetInstrInfo.cpp | 140 unsigned SubReg1 = MI->getOperand(Idx1).getSubReg(); in commuteInstruction() local
155 SubReg0 = SubReg1; in commuteInstruction()
170 MI->getOperand(Idx2).setSubReg(SubReg1); in commuteInstruction()
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| /trueos/contrib/llvm/lib/Target/ARM/ |
| HD | ARMISelDAGToDAG.cpp | 1575 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::gsub_1, MVT::i32); in createGPRPairNode() local
1576 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createGPRPairNode()
1586 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32); in createSRegPairNode() local
1587 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createSRegPairNode()
1596 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32); in createDRegPairNode() local
1597 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createDRegPairNode()
1606 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32); in createQRegPairNode() local
1607 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createQRegPairNode()
1618 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32); in createQuadSRegsNode() local
1621 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1, in createQuadSRegsNode()
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