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Searched refs:SPR_L3CR (Results 1 – 4 of 4) sorted by relevance

/trueos/sys/powerpc/aim/
HDmp_cpudep.c142 ccr = mfspr(SPR_L3CR); in mpc745x_l3_enable()
148 mtspr(SPR_L3CR, ccr); in mpc745x_l3_enable()
150 mtspr(SPR_L3CR, ccr); in mpc745x_l3_enable()
152 mtspr(SPR_L3CR, ccr); in mpc745x_l3_enable()
153 mtspr(SPR_L3CR, ccr | L3CR_L3I); in mpc745x_l3_enable()
154 while (mfspr(SPR_L3CR) & L3CR_L3I) in mpc745x_l3_enable()
156 mtspr(SPR_L3CR, ccr & ~L3CR_L3CLKEN); in mpc745x_l3_enable()
159 mtspr(SPR_L3CR, ccr); in mpc745x_l3_enable()
163 mtspr(SPR_L3CR, ccr); in mpc745x_l3_enable()
254 bsp_state[3] = mfspr(SPR_L3CR); in cpudep_save_config()
HDmachdep.c863 cache_reg = mfspr(SPR_L3CR); in flush_disable_caches()
866 mtspr(SPR_L3CR, cache_reg); in flush_disable_caches()
868 mtspr(SPR_L3CR, cache_reg | L3CR_L3HWF); in flush_disable_caches()
869 while (mfspr(SPR_L3CR) & L3CR_L3HWF) in flush_disable_caches()
873 mtspr(SPR_L3CR, cache_reg); in flush_disable_caches()
875 mtspr(SPR_L3CR, cache_reg | L3CR_L3I); in flush_disable_caches()
877 while (mfspr(SPR_L3CR) & L3CR_L3I) in flush_disable_caches()
/trueos/sys/powerpc/powerpc/
HDcpu.c469 if (mfspr(SPR_L3CR) & L3CR_L3E) in cpu_6xx_print_cacheinfo()
471 mfspr(SPR_L3CR) & L3CR_L3SIZ ? '2' : '1'); in cpu_6xx_print_cacheinfo()
/trueos/sys/powerpc/include/
HDspr.h572 #define SPR_L3CR 0x3fa /* .6. L3 Control Register */ macro