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Searched refs:SPR_L2CR (Results 1 – 4 of 4) sorted by relevance

/trueos/sys/powerpc/aim/
HDmp_cpudep.c120 ccr = mfspr(SPR_L2CR); in mpc74xx_l2_enable()
126 mtspr(SPR_L2CR, ccr | L2CR_L2I); in mpc74xx_l2_enable()
128 ccr = mfspr(SPR_L2CR); in mpc74xx_l2_enable()
131 mtspr(SPR_L2CR, l2cr_config); in mpc74xx_l2_enable()
261 bsp_state[2] = mfspr(SPR_L2CR); in cpudep_save_config()
HDmachdep.c844 cache_reg = mfspr(SPR_L2CR); in flush_disable_caches()
847 mtspr(SPR_L2CR, cache_reg); in flush_disable_caches()
849 mtspr(SPR_L2CR, cache_reg | L2CR_L2HWF); in flush_disable_caches()
850 while (mfspr(SPR_L2CR) & L2CR_L2HWF) in flush_disable_caches()
854 mtspr(SPR_L2CR, cache_reg); in flush_disable_caches()
856 mtspr(SPR_L2CR, cache_reg | L2CR_L2I); in flush_disable_caches()
858 while (mfspr(SPR_L2CR) & L2CR_L2I) in flush_disable_caches()
/trueos/sys/powerpc/powerpc/
HDcpu.c463 if (mfspr(SPR_L2CR) & L2CR_L2E) { in cpu_6xx_print_cacheinfo()
480 switch (mfspr(SPR_L2CR) & L2CR_L2SIZ) { in cpu_6xx_print_cacheinfo()
491 printf("write-%s", (mfspr(SPR_L2CR) & L2CR_L2WT) in cpu_6xx_print_cacheinfo()
493 if (mfspr(SPR_L2CR) & L2CR_L2PE) in cpu_6xx_print_cacheinfo()
/trueos/sys/powerpc/include/
HDspr.h531 #define SPR_L2CR 0x3f9 /* .6. L2 Control Register */ macro