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Searched refs:SPI_PS_IN_CONTROL_0 (Results 1 – 8 of 8) sorted by relevance

/trueos/sys/dev/drm2/radeon/
HDrv770d.h239 #define SPI_PS_IN_CONTROL_0 0x286CC macro
HDrv770.c784 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2)); in rv770_gpu_init()
HDevergreend.h593 #define SPI_PS_IN_CONTROL_0 0x286CC macro
HDr600d.h445 #define SPI_PS_IN_CONTROL_0 0x286CC macro
HDr600.c1886 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2)); in r600_gpu_init()
/trueos/sys/dev/drm2/radeon/reg_srcs/
HDevergreen436 0x000286CC SPI_PS_IN_CONTROL_0
HDcayman422 0x000286CC SPI_PS_IN_CONTROL_0
HDr600426 0x000286CC SPI_PS_IN_CONTROL_0