Home
last modified time | relevance | path

Searched refs:SHL (Results 1 – 25 of 56) sorted by relevance

123

/trueos/contrib/llvm/lib/Target/X86/
HDX86TargetTransformInfo.cpp183 { ISD::SHL, MVT::v4i32, 1 }, in getArithmeticInstrCost()
186 { ISD::SHL, MVT::v8i32, 1 }, in getArithmeticInstrCost()
189 { ISD::SHL, MVT::v2i64, 1 }, in getArithmeticInstrCost()
191 { ISD::SHL, MVT::v4i64, 1 }, in getArithmeticInstrCost()
194 { ISD::SHL, MVT::v32i8, 42 }, // cmpeqb sequence. in getArithmeticInstrCost()
195 { ISD::SHL, MVT::v16i16, 16*10 }, // Scalarized. in getArithmeticInstrCost()
227 { ISD::SHL, MVT::v16i8, 1 }, // psllw. in getArithmeticInstrCost()
228 { ISD::SHL, MVT::v8i16, 1 }, // psllw. in getArithmeticInstrCost()
229 { ISD::SHL, MVT::v4i32, 1 }, // pslld in getArithmeticInstrCost()
230 { ISD::SHL, MVT::v2i64, 1 }, // psllq. in getArithmeticInstrCost()
[all …]
HDX86ISelDAGToDAG.cpp794 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, And, ShlCount); in FoldMaskAndShiftToExtract()
820 if (Shift.getOpcode() != ISD::SHL || in FoldMaskedShiftToScaledMask()
839 SDValue NewShift = DAG.getNode(ISD::SHL, DL, VT, NewAnd, Shift.getOperand(1)); in FoldMaskedShiftToScaledMask()
946 SDValue NewSHL = DAG.getNode(ISD::SHL, DL, VT, NewSRL, NewSHLAmt); in FoldMaskAndShiftToScale()
1020 case ISD::SHL: in MatchAddressRecursively()
1243 if (Shift.getOpcode() != ISD::SRL && Shift.getOpcode() != ISD::SHL) break; in MatchAddressRecursively()
2170 if (N0->getOpcode() != ISD::SHL || !N0->hasOneUse()) in Select()
HDX86ISelLowering.cpp843 setOperationAction(ISD::SHL, VT, Expand); in resetOperationActions()
1096 setOperationAction(ISD::SHL, MVT::v8i16, Custom); in resetOperationActions()
1097 setOperationAction(ISD::SHL, MVT::v16i8, Custom); in resetOperationActions()
1107 setOperationAction(ISD::SHL, MVT::v2i64, Custom); in resetOperationActions()
1108 setOperationAction(ISD::SHL, MVT::v4i32, Custom); in resetOperationActions()
1169 setOperationAction(ISD::SHL, MVT::v16i16, Custom); in resetOperationActions()
1170 setOperationAction(ISD::SHL, MVT::v32i8, Custom); in resetOperationActions()
1254 setOperationAction(ISD::SHL, MVT::v4i64, Custom); in resetOperationActions()
1255 setOperationAction(ISD::SHL, MVT::v8i32, Custom); in resetOperationActions()
1396 setOperationAction(ISD::SHL, MVT::v8i64, Custom); in resetOperationActions()
[all …]
/trueos/crypto/openssl/crypto/bn/asm/
HDppc.pl120 $SHL= "slw"; # shift left
144 $SHL= "sld"; # shift left
1648 $SHL r3,r3,r7 # h = (h<< i)
1650 $SHL r5,r5,r7 # d<<=i
1652 $SHL r4,r4,r7 # l <<=i
/trueos/contrib/llvm/lib/CodeGen/SelectionDAG/
HDLegalizeIntegerTypes.cpp71 case ISD::SHL: Res = PromoteIntRes_SHL(N); break; in PromoteIntegerResult()
546 return DAG.getNode(ISD::SHL, SDLoc(N), Res.getValueType(), Res, Amt); in PromoteIntRes_SHL()
738 Part = DAG.getNode(ISD::SHL, dl, NVT, Part, in PromoteIntRes_VAARG()
804 case ISD::SHL: in PromoteIntegerOperand()
909 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi, in PromoteIntOp_BUILD_PAIR()
1158 case ISD::SHL: in ExpandIntegerResult()
1283 if (N->getOpcode() == ISD::SHL) { in ExpandShiftByConstant()
1288 Hi = DAG.getNode(ISD::SHL, DL, in ExpandShiftByConstant()
1303 Lo = DAG.getNode(ISD::SHL, DL, NVT, InL, DAG.getConstant(Amt, ShTy)); in ExpandShiftByConstant()
1305 DAG.getNode(ISD::SHL, DL, NVT, InH, in ExpandShiftByConstant()
[all …]
HDLegalizeVectorOps.cpp208 case ISD::SHL: in LegalizeOp()
470 Hi = DAG.getNode(ISD::SHL, dl, WideVT, LoadVals[WideIdx], ShAmt); in ExpandLoad()
489 Lo = DAG.getNode(ISD::SHL, dl, WideVT, Lo, ShAmt); in ExpandLoad()
640 TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Expand) in ExpandSEXTINREG()
651 Op = DAG.getNode(ISD::SHL, DL, VT, Op, ShiftSz); in ExpandSEXTINREG()
HDTargetLowering.cpp597 case ISD::SHL: in SimplifyDemandedBits()
613 unsigned Opc = ISD::SHL; in SimplifyDemandedBits()
639 isTypeDesirableForOp(ISD::SHL, InnerVT)) { in SimplifyDemandedBits()
644 TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp, in SimplifyDemandedBits()
672 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, VT, in SimplifyDemandedBits()
698 if (InOp.getOpcode() == ISD::SHL && in SimplifyDemandedBits()
706 Opc = ISD::SHL; in SimplifyDemandedBits()
802 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, in SimplifyDemandedBits()
1016 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, in SimplifyDemandedBits()
1092 if (Val.getOpcode() == ISD::SHL) in ValueHasExactlyOneBitSet()
[all …]
HDDAGCombiner.cpp1148 case ISD::SHL: return visitSHL(N); in visit()
1231 case ISD::SHL: in combine()
1391 DAG.getNode(ISD::SHL, SDLoc(N00), VT, in combineShlAddConstant()
1393 DAG.getNode(ISD::SHL, SDLoc(N01), VT, in combineShlAddConstant()
1516 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { in visitADD()
1520 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { in visitADD()
1526 if (N1.getOpcode() == ISD::SHL && in visitADD()
1532 DAG.getNode(ISD::SHL, SDLoc(N), VT, in visitADD()
1535 if (N0.getOpcode() == ISD::SHL && in visitADD()
1541 DAG.getNode(ISD::SHL, SDLoc(N), VT, in visitADD()
[all …]
HDLegalizeDAG.cpp567 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount); in ExpandUnalignedLoad()
1018 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi, in LegalizeLoadOps()
1048 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi, in LegalizeLoadOps()
1285 case ISD::SHL: in LegalizeOp()
1544 SignBit = DAG.getNode(ISD::SHL, dl, LoadTy, SignBit, in ExpandFCOPYSIGN()
2537 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); in ExpandBSWAP()
2541 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT)); in ExpandBSWAP()
2542 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); in ExpandBSWAP()
2551 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT)); in ExpandBSWAP()
2552 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT)); in ExpandBSWAP()
[all …]
HDFastISel.cpp1007 return SelectBinaryOp(I, ISD::SHL); in SelectOperator()
1170 Opcode = ISD::SHL; in FastEmit_ri_()
1180 if ((Opcode == ISD::SHL || Opcode == ISD::SRA || Opcode == ISD::SRL) && in FastEmit_ri_()
/trueos/crypto/openssl/crypto/sha/asm/
HDsha512-ppc.pl46 $SHL="sldi";
54 $SHL="slwi";
187 $SHL $num,$num,`log(16*$SZ)/log(2)`
/trueos/contrib/llvm/lib/Target/ARM/
HDARMSelectionDAGInfo.h26 case ISD::SHL: return ARM_AM::lsl; in getShiftOpcForNode()
/trueos/usr.bin/xlint/lint1/
HDop.h79 SHL, enumerator
HDtree.c131 { SHL, { 1,0,1,0,0,1,1,0,0,0,0,0,1,0,0,1,1, in initmtab()
614 if (mp->m_balance || (tflag && (op == SHL || op == SHR))) in build()
646 case SHL: in build()
812 if (op == SHL || op == SHR || op == SHLASS || op == SHRASS) { in typeok()
967 case SHL: in typeok()
2809 case SHL: in fold()
3608 case SHL: in chkmisc()
3944 case SHL: in precconf()
/trueos/contrib/llvm/lib/Target/PowerPC/
HDPPCISelDAGToDAG.cpp371 if (Opcode == ISD::SHL) { in isRotateAndMask()
422 if (Op0.getOperand(0).getOpcode() == ISD::SHL || in SelectBitfieldInsert()
424 if (Op1.getOperand(0).getOpcode() != ISD::SHL && in SelectBitfieldInsert()
431 } else if (Op0Opc == ISD::SHL || Op0Opc == ISD::SRL) { in SelectBitfieldInsert()
432 if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL && in SelectBitfieldInsert()
444 if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) && in SelectBitfieldInsert()
447 SH = (Op1Opc == ISD::SHL) ? Value : 32 - Value; in SelectBitfieldInsert()
451 if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) && in SelectBitfieldInsert()
456 SH = (SHOpc == ISD::SHL) ? Value : 32 - Value; in SelectBitfieldInsert()
1158 case ISD::SHL: { in Select()
HDPPCISelLowering.h101 SRL, SRA, SHL, enumerator
/trueos/contrib/llvm/patches/
HDpatch-r262265-llvm-r201718-sparc.diff3 Expand 64bit {SHL,SHR,SRA}_PARTS on sparcv9.
HDpatch-r262261-llvm-r200960-sparc.diff46 H44 = DAG.getNode(ISD::SHL, DL, VT, H44, DAG.getConstant(12, MVT::i32));
57 Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, DAG.getConstant(32, MVT::i32));
/trueos/contrib/llvm/lib/Target/MSP430/
HDMSP430ISelLowering.cpp96 setOperationAction(ISD::SHL, MVT::i8, Custom); in MSP430TargetLowering()
99 setOperationAction(ISD::SHL, MVT::i16, Custom); in MSP430TargetLowering()
190 case ISD::SHL: // FALLTHROUGH in LowerOperation()
753 case ISD::SHL: in LowerShifts()
754 return DAG.getNode(MSP430ISD::SHL, dl, in LowerShifts()
779 Victim = DAG.getNode((Opc == ISD::SHL ? MSP430ISD::RLA : MSP430ISD::RRA), in LowerShifts()
1159 case MSP430ISD::SHL: return "MSP430ISD::SHL"; in getTargetNodeName()
HDMSP430ISelLowering.h65 SHL, SRA, SRL enumerator
/trueos/contrib/llvm/include/llvm/CodeGen/
HDISDOpcodes.h306 SHL, SRA, SRL, ROTL, ROTR, enumerator
/trueos/contrib/llvm/lib/Target/Mips/
HDMipsSEISelLowering.cpp77 setTargetDAGCombine(ISD::SHL); in MipsSETargetLowering()
182 setOperationAction(ISD::SHL, Ty, Legal); in addMSAIntType()
712 return DAG.getNode(ISD::SHL, DL, VT, X, in genConstMult()
808 if (Op0->getOpcode() == ISD::SHL && Op1 == Op0->getOperand(1)) { in performSRACombine()
984 case ISD::SHL: in PerformDAGCombine()
1370 DAG.getNode(ISD::SHL, DL, VecTy, DAG.getConstant(1, VecTy), Exp2Imm); in lowerMSABinaryBitImmIntr()
1380 SDValue Bit = DAG.getNode(ISD::SHL, DL, ResTy, One, Op->getOperand(2)); in lowerMSABitClear()
1509 DAG.getNode(ISD::SHL, DL, VecTy, One, in lowerINTRINSIC_WO_CHAIN()
1543 DAG.getNode(ISD::SHL, DL, VecTy, One, in lowerINTRINSIC_WO_CHAIN()
1809 DAG.getNode(ISD::SHL, SDLoc(Op), ResTy, in lowerINTRINSIC_WO_CHAIN()
[all …]
HDMipsISelLowering.cpp628 if (Shl.getOpcode() != ISD::SHL) in performORCombine()
1651 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); in lowerFCOPYSIGN32()
1654 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31); in lowerFCOPYSIGN32()
1699 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1); in lowerFCOPYSIGN64()
1709 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY, in lowerFCOPYSIGN64()
1741 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); in lowerFABS32()
1767 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i64, X, Const1); in lowerFABS64()
1870 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi, Shamt); in lowerShiftLeftParts()
1872 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, MVT::i32, Lo, Shamt); in lowerShiftLeftParts()
1904 SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi, in lowerShiftRightParts()
[all …]
/trueos/contrib/llvm/lib/Target/SystemZ/
HDSystemZISelDAGToDAG.cpp780 case ISD::SHL: { in expandRxSBG()
1065 case ISD::SHL: in Select()
/trueos/contrib/llvm/lib/Target/R600/
HDR600ISelLowering.cpp1077 SDValue Shift = DAG.getNode(ISD::SHL, DL, VT, ByteIndex, in LowerSTORE()
1079 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, VT, TruncValue, Shift); in LowerSTORE()
1080 SDValue Mask = DAG.getNode(ISD::SHL, DL, VT, MaskConstant, Shift); in LowerSTORE()
1279 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, NewLoad, ShiftAmount); in LowerLOAD()

123