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Searched refs:SETUGE (Results 1 – 25 of 30) sorted by relevance

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/trueos/contrib/llvm/include/llvm/CodeGen/
HDISDOpcodes.h732 SETUGE, // 1 0 1 1 True if unordered, greater than, or equal enumerator
759 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE; in isUnsignedIntSetCC()
/trueos/contrib/llvm/lib/CodeGen/
HDAnalysis.cpp163 case FCmpInst::FCMP_UGE: return ISD::SETUGE; in getFCmpCondCode()
179 case ISD::SETOGE: case ISD::SETUGE: return ISD::SETGE; in getFCmpCodeWithoutNaN()
194 case ICmpInst::ICMP_UGE: return ISD::SETUGE; in getICmpCondCode()
/trueos/contrib/llvm/lib/CodeGen/SelectionDAG/
HDTargetLowering.cpp177 case ISD::SETUGE: in softenSetCCOperands()
1305 case ISD::SETUGE: in SimplifySetCC()
1328 case ISD::SETUGE: in SimplifySetCC()
1469 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { in SimplifySetCC()
1487 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal) in SimplifySetCC()
1577 } else if (Cond == ISD::SETULT || Cond == ISD::SETUGE || in SimplifySetCC()
1590 NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; in SimplifySetCC()
1661 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE); in SimplifySetCC()
1879 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X in SimplifySetCC()
HDSelectionDAGDumper.cpp298 case ISD::SETUGE: return "setuge"; in getOperationName()
HDLegalizeIntegerTypes.cpp837 case ISD::SETUGE: in PromoteSetCCOperands()
2569 case ISD::SETUGE: LowCC = ISD::SETUGE; break; in IntegerExpandSetCCOperands()
2597 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) || in IntegerExpandSetCCOperands()
HDSelectionDAG.cpp263 case ISD::SETUGE: return 2; in isSignedOp()
1674 case ISD::SETUGE: return getConstant(C1.uge(C2), VT); in FoldSetCC()
1724 case ISD::SETUGE: return getConstant(R!=APFloat::cmpLessThan, VT); in FoldSetCC()
HDLegalizeDAG.cpp1659 case ISD::SETUGE: in LegalizeSetCCCondCode()
2381 ISD::SETUGE); in ExpandLegalINT_TO_FP()
/trueos/contrib/llvm/lib/Target/Hexagon/
HDHexagonSelectCCInfo.td68 IntRegs:$fval, SETUGE)),
HDHexagonISelLowering.cpp1139 setCondCodeAction(ISD::SETUGE, MVT::f32, Legal); in HexagonTargetLowering()
1140 setCondCodeAction(ISD::SETUGE, MVT::f64, Legal); in HexagonTargetLowering()
/trueos/contrib/llvm/lib/Target/R600/
HDAMDGPUISelLowering.cpp474 case ISD::SETUGE: in LowerMinMax()
661 ISD::SETUGE); in LowerUDIVREM()
667 ISD::SETUGE); in LowerUDIVREM()
HDAMDGPUInstructions.td82 def COND_UGE : PatLeaf <(cond), [{return N->get() == ISD::SETUGE;}]>;
HDAMDILISelLowering.cpp125 setOperationAction(ISD::SETUGE, VT, Expand); in InitAMDILLowering()
HDSIISelLowering.cpp62 setCondCodeAction(ISD::SETUGE, MVT::f32, Expand); in SITargetLowering()
69 setCondCodeAction(ISD::SETUGE, MVT::f64, Expand); in SITargetLowering()
HDR600ISelLowering.cpp50 setCondCodeAction(ISD::SETUGE, MVT::f32, Expand); in R600TargetLowering()
HDR600Instructions.td810 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETUGE))]
/trueos/contrib/llvm/lib/Target/PowerPC/
HDPPCISelDAGToDAG.cpp587 case ISD::SETUGE: in getPredicateForSetCC()
611 case ISD::SETUGE: in getCRIdxForSetCC()
663 case ISD::SETUGE: in getVCmpInst()
822 case ISD::SETUGE: { in SelectSETCC()
/trueos/contrib/llvm/lib/Target/AArch64/
HDAArch64ISelLowering.cpp1788 case ISD::SETUGE: return A64CC::HS; in IntCCToA64CC()
1838 case ISD::SETUGE: in getSelectableIntSetCC()
1854 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; in getSelectableIntSetCC()
1888 case ISD::SETUGE: CondCode = A64CC::PL; break; in FPCCToA64CC()
2575 case ISD::SETUGE: in LowerVectorSETCC()
2665 case ISD::SETUGE: in LowerVectorSETCC()
/trueos/contrib/llvm/include/llvm/Target/
HDTargetSelectionDAG.td502 def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode;
850 (setcc node:$lhs, node:$rhs, SETUGE)>;
/trueos/contrib/llvm/lib/Target/ARM/
HDARMISelLowering.cpp1228 case ISD::SETUGE: return ARMCC::HS; in IntCCToARMCC()
1253 case ISD::SETUGE: CondCode = ARMCC::PL; break; in FPCCToARMCC()
3154 case ISD::SETUGE: in getARMCmp()
3170 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; in getARMCmp()
3289 if (CC == ISD::SETUGE || CC == ISD::SETOGE || CC == ISD::SETOLE || in checkVSELConstraints()
3312 if (CC == ISD::SETULE || CC == ISD::SETULT || CC == ISD::SETUGE || in checkVSELConstraints()
4197 case ISD::SETUGE: Swap = true; // Fallthrough in LowerVSETCC()
4233 case ISD::SETUGE: Opc = ARMISD::VCGEU; break; in LowerVSETCC()
10060 case ISD::SETUGE: in PerformSELECT_CCCombine()
10064 IsUnordered = (CC == ISD::SETUGT || CC == ISD::SETUGE); in PerformSELECT_CCCombine()
[all …]
/trueos/contrib/llvm/lib/Target/Mips/
HDMipsDSPInstrInfo.td1370 def : DSPSetCCPatInv<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETUGE>;
1383 def : DSPSelectCCPatInv<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETUGE>;
HDMipsSEISelLowering.cpp203 setCondCodeAction(ISD::SETUGE, Ty, Expand); in addMSAIntType()
239 setCondCodeAction(ISD::SETUGE, Ty, Expand); in addMSAFloatType()
865 case ISD::SETUGE: return !IsV216; in isLegalDSPCondCode()
/trueos/contrib/llvm/lib/Target/MSP430/
HDMSP430ISelLowering.cpp841 case ISD::SETUGE: in EmitCMP()
/trueos/contrib/llvm/lib/Target/X86/
HDX86ISelLowering.cpp3452 case ISD::SETUGE: return X86::COND_AE; in TranslateX86CC()
3470 case ISD::SETUGE: in TranslateX86CC()
3494 case ISD::SETUGE: // flipped in TranslateX86CC()
9804 case ISD::SETUGE: SSECC = 5; break; in translateX86FSETCC()
9870 case ISD::SETUGE: Unsigned = true; in LowerIntVSETCC_AVX512()
9965 case ISD::SETUGE: Swap = true; in LowerVSETCC()
9980 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break; in LowerVSETCC()
16568 case ISD::SETUGE: in matchIntegerMINMAX()
16586 case ISD::SETUGE: in matchIntegerMINMAX()
16679 case ISD::SETUGE: in PerformSELECTCombine()
[all …]
/trueos/contrib/llvm/lib/Target/Sparc/
HDSparcISelLowering.cpp1337 case ISD::SETUGE: return SPCC::ICC_CC; in IntCondCCodeToICC()
1361 case ISD::SETUGE: return SPCC::FCC_UGE; in FPCondCCodeToFCC()
/trueos/contrib/llvm/lib/Target/NVPTX/
HDNVPTXVector.td972 (setcc node:$lhs, node:$rhs, SETUGE)>;

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