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Searched refs:Rt (Results 1 – 16 of 16) sorted by relevance

/trueos/contrib/llvm/lib/Target/AArch64/Disassembler/
HDAArch64Disassembler.cpp776 unsigned Rt = fieldFromInstruction(Insn, 0, 5); in DecodeLDSTPairInstruction() local
795 if (L && Rt == Rt2) in DecodeLDSTPairInstruction()
800 if (Indexed && V == 0 && Rn != 31 && (Rt == Rn || Rt2 == Rn)) in DecodeLDSTPairInstruction()
811 DecodeFPR32RegisterClass(Inst, Rt, Address, Decoder); in DecodeLDSTPairInstruction()
815 DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder); in DecodeLDSTPairInstruction()
819 DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder); in DecodeLDSTPairInstruction()
827 DecodeGPR32RegisterClass(Inst, Rt, Address, Decoder); in DecodeLDSTPairInstruction()
832 DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder); in DecodeLDSTPairInstruction()
836 DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder); in DecodeLDSTPairInstruction()
859 unsigned Rt = fieldFromInstruction(Val, 0, 5); in DecodeLoadPairExclusiveInstruction() local
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/trueos/contrib/llvm/lib/Target/ARM/
HDARMInstrThumb2.td975 def i12 : T2Ii12<(outs target:$Rt), (ins t2addrmode_imm12:$addr), iii,
976 opc, ".w\t$Rt, $addr",
977 [(set target:$Rt, (opnode t2addrmode_imm12:$addr))]> {
978 bits<4> Rt;
986 let Inst{15-12} = Rt;
991 def i8 : T2Ii8 <(outs target:$Rt), (ins t2addrmode_negimm8:$addr), iii,
992 opc, "\t$Rt, $addr",
993 [(set target:$Rt, (opnode t2addrmode_negimm8:$addr))]> {
994 bits<4> Rt;
1003 let Inst{15-12} = Rt;
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HDARMInstrInfo.td1540 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1541 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1542 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1543 bits<4> Rt;
1547 let Inst{15-12} = Rt;
1550 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1551 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1552 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1553 bits<4> Rt;
1558 let Inst{15-12} = Rt;
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HDARMInstrVFP.td742 (outs GPR:$Rt), (ins SPR:$Sn),
743 IIC_fpMOVSI, "vmov", "\t$Rt, $Sn",
744 [(set GPR:$Rt, (bitconvert SPR:$Sn))]> {
746 bits<4> Rt;
752 let Inst{15-12} = Rt;
764 (outs SPR:$Sn), (ins GPR:$Rt),
765 IIC_fpMOVIS, "vmov", "\t$Sn, $Rt",
766 [(set SPR:$Sn, (bitconvert GPR:$Rt))]>,
770 bits<4> Rt;
775 let Inst{15-12} = Rt;
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HDARMInstrThumb.td591 (outs tGPR:$Rt), (ins AddrMode_r:$addr),
592 am, itin_r, asm, "\t$Rt, $addr",
593 [(set tGPR:$Rt, (opnode AddrMode_r:$addr))]>;
596 (outs tGPR:$Rt), (ins AddrMode_i:$addr),
597 am, itin_i, asm, "\t$Rt, $addr",
598 [(set tGPR:$Rt, (opnode AddrMode_i:$addr))]>;
608 (outs), (ins tGPR:$Rt, AddrMode_r:$addr),
609 am, itin_r, asm, "\t$Rt, $addr",
610 [(opnode tGPR:$Rt, AddrMode_r:$addr)]>;
613 (outs), (ins tGPR:$Rt, AddrMode_i:$addr),
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HDARMInstrFormats.td509 bits<4> Rt;
515 let Inst{15-12} = Rt;
524 bits<4> Rt;
533 let Inst{3-0} = Rt;
563 : AI<oops, iops, MiscFrm, NoItinerary, opc, "\t$Rt, $Rt2, $addr", pattern> {
564 bits<4> Rt;
571 let Inst{15-12} = Rt;
635 bits<4> Rt;
641 let Inst{15-12} = Rt;
703 bits<4> Rt;
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HDARMBaseInstrInfo.cpp2625 unsigned Rt = MI->getOperand(0).getReg(); in getNumMicroOpsSwiftLdSt() local
2627 return (Rt == Rm) ? 4 : 3; in getNumMicroOpsSwiftLdSt()
2632 unsigned Rt = MI->getOperand(0).getReg(); in getNumMicroOpsSwiftLdSt() local
2634 if (Rt == Rm) in getNumMicroOpsSwiftLdSt()
2662 unsigned Rt = MI->getOperand(0).getReg(); in getNumMicroOpsSwiftLdSt() local
2666 if (Rt == Rm) in getNumMicroOpsSwiftLdSt()
2675 unsigned Rt = MI->getOperand(0).getReg(); in getNumMicroOpsSwiftLdSt() local
2677 return (Rt == Rm) ? 3 : 2; in getNumMicroOpsSwiftLdSt()
2698 unsigned Rt = MI->getOperand(0).getReg(); in getNumMicroOpsSwiftLdSt() local
2699 if (Rt == Rm) in getNumMicroOpsSwiftLdSt()
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/trueos/contrib/llvm/lib/Target/AArch64/
HDAArch64InstrInfo.td1409 (ins GPR64:$Rt, bcc_target:$Label),
1410 !strconcat(asmop,"\t$Rt, $Label"),
1411 [(A64br_cc (A64cmp i64:$Rt, 0), SETOP, bb:$Label)],
1416 (ins GPR32:$Rt, bcc_target:$Label),
1417 !strconcat(asmop,"\t$Rt, $Label"),
1418 [(A64br_cc (A64cmp i32:$Rt, 0), SETOP, bb:$Label)],
2513 : A64I_LDRlit<opc, v, (outs OutReg:$Rt), (ins ldrlit_label:$Imm19),
2514 "ldr\t$Rt, $Imm19", patterns, NoItinerary>;
2533 (outs GPR64:$Rt),
2535 "ldrsw\t$Rt, $Imm19",
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HDAArch64InstrFormats.td82 bits<5> Rt;
84 let Inst{4-0} = Rt;
106 // Instructions taking Rt,Rt2,Rn
235 // Inherit Rt in 4-0
589 // Inherit Rt in 4-0
645 // Inherit Rt in 4-0
665 // Inherit Rt in 4-0
685 // Inherit Rt in 4-0
704 // Inherit Rt in 4-0
748 // Inherits Rt in 4-0
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HDAArch64InstrNEON.td3080 (outs VecList:$Rt), (ins GPR64xsp:$Rn),
3081 asmop # "\t$Rt, [$Rn]",
3134 (outs), (ins GPR64xsp:$Rn, VecList:$Rt),
3135 asmop # "\t$Rt, [$Rn]",
3351 (outs VecList:$Rt, GPR64xsp:$wb),
3353 asmop # "\t$Rt, [$Rn], $amt",
3360 (outs VecList:$Rt, GPR64xsp:$wb),
3362 asmop # "\t$Rt, [$Rn], $Rm",
3435 (ins GPR64xsp:$Rn, ImmTy:$amt, VecList:$Rt),
3436 asmop # "\t$Rt, [$Rn], $amt",
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/trueos/contrib/llvm/lib/Target/Hexagon/
HDHexagonInstrInfoV4.td136 // Rd=cmp.eq(Rs,Rt)
139 (ins IntRegs:$Rs, IntRegs:$Rt),
140 "$Rd = cmp.eq($Rs, $Rt)",
143 IntRegs:$Rt)))))]>,
146 // Rd=cmp.ne(Rs,Rt)
149 (ins IntRegs:$Rs, IntRegs:$Rt),
150 "$Rd = !cmp.eq($Rs, $Rt)",
153 IntRegs:$Rt)))))]>,
741 // memb(Rx++#s4:0:circ(Mu))=Rt
742 // memb(Rx++I:circ(Mu))=Rt
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HDHexagonInstrInfo.td1206 // Rd=mpyi(Rs,Rt)
1224 // Rx+=mpyi(Rs,Rt)
1245 // Rd=mpy(Rs,Rt.H):<<1:rnd:sat
1246 // Rd=mpy(Rs,Rt.L):<<1:rnd:sat
1247 // Rd=mpy(Rs,Rt)
1253 // Rd=mpy(Rs,Rt):rnd
1254 // Rd=mpyu(Rs,Rt)
1261 // Rdd=mpyu(Rs,Rt)
1268 // Rdd=mpy(Rs,Rt)
1276 // Rxx[+-]=mpy(Rs,Rt)
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HDHexagonIntrinsics.td2349 // Rdd[-+]=cmpy(Rs, Rt:<<1]:sat
2565 //Rd=mpy(Rs.[H|L],Rt.[H|L:<<0|:<<1]|
2635 //Rdd=mpy(Rs.[H|L],Rt.[H|L])[[:<<0|:<<1]|[:<<0:rnd|:<<1:rnd]]
2672 //Rx+=mpy(Rs.[H|L],Rt.[H|L])[[[:<<0|:<<1]|[:<<0:sat|:<<1:sat]]
2709 //Rx-=mpy(Rs.[H|L],Rt.[H|L])[[[:<<0|:<<1]|[:<<0:sat|:<<1:sat]]
2746 //Rx+=mpy(Rs.[H|L],Rt.[H|L:<<0|:<<1]
2767 //Rx-=mpy(Rs.[H|L],Rt.[H|L:<<0|:<<1]
2789 //Rd=mpyu(Rs.[H|L],Rt.[H|L])[:<<0|:<<1]
2807 //Rdd=mpyu(Rs.[H|L],Rt.[H|L])[:<<0|:<<1]
2825 //Rd+=mpyu(Rs.[H|L],Rt.[H|L])[:<<0|:<<1]
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/trueos/contrib/llvm/lib/Target/ARM/Disassembler/
HDARMDisassembler.cpp1470 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeAddrMode2IdxInstruction() local
1495 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) in DecodeAddrMode2IdxInstruction()
1529 if (writeback && (Rn == 15 || Rn == Rt)) in DecodeAddrMode2IdxInstruction()
1618 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeAddrMode3Instruction() local
1627 unsigned Rt2 = Rt + 1; in DecodeAddrMode3Instruction()
1639 if (Rt & 0x1) S = MCDisassembler::SoftFail; in DecodeAddrMode3Instruction()
1651 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) in DecodeAddrMode3Instruction()
1663 if (Rt == 15) in DecodeAddrMode3Instruction()
1665 if (writeback && (Rn == 15 || Rn == Rt)) in DecodeAddrMode3Instruction()
1680 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) in DecodeAddrMode3Instruction()
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/trueos/contrib/llvm/tools/lldb/source/Plugins/Instruction/ARM/
HDEmulateInstructionARM.cpp395 uint32_t Rt; // the source register in EmulatePUSH() local
414 Rt = Bits32(opcode, 15, 12); in EmulatePUSH()
416 if (BadReg(Rt)) in EmulatePUSH()
418 registers = (1u << Rt); in EmulatePUSH()
427 Rt = Bits32(opcode, 15, 12); in EmulatePUSH()
429 if (Rt == dwarf_sp) in EmulatePUSH()
431 registers = (1u << Rt); in EmulatePUSH()
518 uint32_t Rt; // the destination register in EmulatePOP() local
540 Rt = Bits32(opcode, 15, 12); in EmulatePOP()
542 if (Rt == 13) in EmulatePOP()
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/trueos/contrib/llvm/lib/Target/ARM/AsmParser/
HDARMAsmParser.cpp5238 unsigned Rt = MRI->getEncodingValue(Reg1); in ParseInstruction() local
5242 if (Rt + 1 != Rt2 || (Rt & 1)) { in ParseInstruction()
5373 const unsigned Rt = MRI->getEncodingValue(RtReg); in validateInstruction() local
5375 if ((Rt & 1) == 1) in validateInstruction()
5381 if (Rt2 != Rt + 1) in validateInstruction()
5389 if (Rn == Rt || Rn == Rt2) in validateInstruction()
5401 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg()); in validateInstruction() local
5403 if (Rt2 == Rt) in validateInstruction()
5410 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg()); in validateInstruction() local
5412 if (Rt2 != Rt + 1) in validateInstruction()
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