| /trueos/contrib/llvm/utils/TableGen/ |
| HD | CallingConvEmitter.cpp | 110 ListInit *RegList = Action->getValueAsListInit("RegList"); in EmitAction() local
111 if (RegList->getSize() == 1) { in EmitAction()
113 O << getQualifiedName(RegList->getElementAsRecord(0)) << ")) {\n"; in EmitAction()
118 for (unsigned i = 0, e = RegList->getSize(); i != e; ++i) { in EmitAction()
120 O << getQualifiedName(RegList->getElementAsRecord(i)); in EmitAction()
124 << Counter << ", " << RegList->getSize() << ")) {\n"; in EmitAction()
131 ListInit *RegList = Action->getValueAsListInit("RegList"); in EmitAction() local
134 ShadowRegList->getSize() != RegList->getSize()) in EmitAction()
137 if (RegList->getSize() == 1) { in EmitAction()
139 O << getQualifiedName(RegList->getElementAsRecord(0)); in EmitAction()
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| /trueos/contrib/llvm/lib/Target/ARM/MCTargetDesc/ |
| HD | ARMELFStreamer.cpp | 79 virtual void emitRegSave(const SmallVectorImpl<unsigned> &RegList,
115 void ARMTargetAsmStreamer::emitRegSave(const SmallVectorImpl<unsigned> &RegList, in emitRegSave() argument
117 assert(RegList.size() && "RegList should not be empty"); in emitRegSave()
123 InstPrinter.printRegName(OS, RegList[0]); in emitRegSave()
125 for (unsigned i = 1, e = RegList.size(); i != e; ++i) { in emitRegSave()
127 InstPrinter.printRegName(OS, RegList[i]); in emitRegSave()
247 virtual void emitRegSave(const SmallVectorImpl<unsigned> &RegList,
301 void emitRegSave(const SmallVectorImpl<unsigned> &RegList, bool isVector);
469 void ARMTargetELFStreamer::emitRegSave(const SmallVectorImpl<unsigned> &RegList, in emitRegSave() argument
471 getStreamer().emitRegSave(RegList, isVector); in emitRegSave()
[all …]
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| /trueos/contrib/llvm/lib/Target/ARM/ |
| HD | ARMCallingConv.h | 31 static const uint16_t RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAPCS() local
34 if (unsigned Reg = State.AllocateReg(RegList, 4)) in f64AssignAPCS()
49 if (unsigned Reg = State.AllocateReg(RegList, 4)) in f64AssignAPCS()
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| HD | ARMBaseRegisterInfo.cpp | 54 const uint16_t *RegList = (STI.isTargetIOS() && !STI.isAAPCS_ABI()) in getCalleeSavedRegs() local
58 if (!MF) return RegList; in getCalleeSavedRegs()
81 return RegList; in getCalleeSavedRegs()
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| HD | ARMAsmPrinter.cpp | 997 SmallVector<unsigned, 4> RegList; in EmitUnwindingInstruction() local
1022 RegList.push_back(MO.getReg()); in EmitUnwindingInstruction()
1030 RegList.push_back(SrcReg); in EmitUnwindingInstruction()
1033 ATS.emitRegSave(RegList, Opc == ARM::VSTMDDB_UPD); in EmitUnwindingInstruction()
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| HD | ARMBaseInstrInfo.cpp | 1910 SmallVector<MachineOperand, 4> RegList; in tryFoldSPUpdateIntoPushPop() local
1912 RegList.push_back(MI->getOperand(i)); in tryFoldSPUpdateIntoPushPop()
1925 RegList.push_back(MachineOperand::CreateReg(CurReg, false, false, in tryFoldSPUpdateIntoPushPop()
1947 RegList.push_back(MachineOperand::CreateReg(CurReg, true, false, false, in tryFoldSPUpdateIntoPushPop()
1963 for (int i = RegList.size() - 1; i >= 0; --i) in tryFoldSPUpdateIntoPushPop()
1964 MIB.addOperand(RegList[i]); in tryFoldSPUpdateIntoPushPop()
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| HD | ARMInstrInfo.td | 440 def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; }
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| /trueos/contrib/llvm/include/llvm/Target/ |
| HD | TargetCallingConv.td | 72 list<Register> RegList = regList;
79 list<Register> RegList = regList;
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| /trueos/contrib/llvm/lib/Target/AArch64/ |
| HD | AArch64RegisterInfo.td | 259 RegisterClass RegList> {
268 def _operand : RegisterOperand<RegList,
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| HD | AArch64InstrNEON.td | 3620 RegisterClass RegList> {
3621 defm B : VectorList_operands<PREFIX, "B", Count, RegList>;
3622 defm H : VectorList_operands<PREFIX, "H", Count, RegList>;
3623 defm S : VectorList_operands<PREFIX, "S", Count, RegList>;
3624 defm D : VectorList_operands<PREFIX, "D", Count, RegList>;
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| /trueos/contrib/llvm/include/llvm/MC/ |
| HD | MCStreamer.h | 89 virtual void emitRegSave(const SmallVectorImpl<unsigned> &RegList,
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| /trueos/contrib/llvm/lib/Target/MSP430/ |
| HD | MSP430ISelLowering.cpp | 287 static const uint16_t RegList[] = { in AnalyzeArguments() local
290 static const unsigned NbRegs = array_lengthof(RegList); in AnalyzeArguments()
332 unsigned Reg = State.AllocateReg(RegList, NbRegs); in AnalyzeArguments()
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| /trueos/contrib/llvm/lib/Target/Hexagon/ |
| HD | HexagonISelLowering.cpp | 185 static const uint16_t RegList[] = { in CC_Hexagon32() local
189 if (unsigned Reg = State.AllocateReg(RegList, 6)) { in CC_Hexagon32()
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| /trueos/contrib/llvm/lib/Target/ARM/AsmParser/ |
| HD | ARMAsmParser.cpp | 1609 const SmallVectorImpl<unsigned> &RegList = getRegList(); in addRegListOperands() local
1611 I = RegList.begin(), E = RegList.end(); I != E; ++I) in addRegListOperands()
2596 const SmallVectorImpl<unsigned> &RegList = getRegList(); in print() local
2598 I = RegList.begin(), E = RegList.end(); I != E; ) { in print()
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| /trueos/contrib/llvm/lib/Target/Sparc/ |
| HD | SparcISelLowering.cpp | 56 static const uint16_t RegList[] = { in CC_Sparc_Assign_f64() local
60 if (unsigned Reg = State.AllocateReg(RegList, 6)) { in CC_Sparc_Assign_f64()
71 if (unsigned Reg = State.AllocateReg(RegList, 6)) in CC_Sparc_Assign_f64()
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