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Searched refs:RL_COMMAND (Results 1 – 3 of 3) sorted by relevance

/trueos/sys/pci/
HDif_rl.c567 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); in rl_reset()
571 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) in rl_reset()
1143 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) { in rl_rxeof()
1735 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); in rl_init_locked()
1762 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); in rl_init_locked()
1925 CSR_WRITE_1(sc, RL_COMMAND, 0x00); in rl_stop()
1929 if ((CSR_READ_1(sc, RL_COMMAND) & in rl_stop()
HDif_rlreg.h67 #define RL_COMMAND 0x0037 /* command register */ macro
/trueos/sys/dev/re/
HDif_re.c724 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); in re_reset()
728 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) in re_reset()
3200 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); in re_init_locked()
3253 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); in re_init_locked()
3596 CSR_WRITE_1(sc, RL_COMMAND, 0x00); in re_stop()
3598 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_STOPREQ | RL_CMD_TX_ENB | in re_stop()
3612 CSR_WRITE_1(sc, RL_COMMAND, 0x00); in re_stop()
3841 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RX_ENB); in re_setwol()