| /trueos/contrib/llvm/lib/CodeGen/ |
| HD | RegisterClassInfo.cpp | 79 RCInfo &RCI = RegClass[RC->getID()]; in compute() local
84 if (!RCI.Order) in compute()
85 RCI.Order.reset(new MCPhysReg[NumRegs]); in compute()
110 RCI.Order[N++] = PhysReg; in compute()
114 RCI.NumRegs = N + CSRAlias.size(); in compute()
115 assert (RCI.NumRegs <= NumRegs && "Allocation order larger than regclass"); in compute()
123 RCI.Order[N++] = PhysReg; in compute()
128 if (StressRA && RCI.NumRegs > StressRA) in compute()
129 RCI.NumRegs = StressRA; in compute()
133 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs) in compute()
[all …]
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| HD | TargetRegisterInfo.cpp | 192 for (SuperRegClassIterator RCI(B, this); RCI.isValid(); ++RCI) in getMatchingSuperRegClass() local
193 if (RCI.getSubReg() == Idx) in getMatchingSuperRegClass()
196 return firstCommonClass(RCI.getMask(), A->getSubClassMask(), this); in getMatchingSuperRegClass()
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| HD | RegisterPressure.cpp | 188 RCI = rci; in init()
619 const RegisterClassInfo *RCI, in computeExcessPressureDelta() argument
629 unsigned Limit = RCI->getRegPressureSetLimit(i); in computeExcessPressureDelta()
761 computeExcessPressureDelta(SavedPressure, CurrSetPressure, Delta, RCI, in getMaxUpwardPressureDelta()
827 unsigned Limit = RCI->getRegPressureSetLimit(PSetID); in getUpwardPressureDelta()
955 computeExcessPressureDelta(SavedPressure, CurrSetPressure, Delta, RCI, in getMaxDownwardPressureDelta()
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| HD | AggressiveAntiDepBreaker.h | 134 const RegisterClassInfo &RCI,
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| HD | PostRASchedulerList.cpp | 205 AliasAnalysis *AA, const RegisterClassInfo &RCI, in SchedulePostRATDList() argument
221 (AntiDepBreaker *)new AggressiveAntiDepBreaker(MF, RCI, CriticalPathRCs) : in SchedulePostRATDList()
223 (AntiDepBreaker *)new CriticalAntiDepBreaker(MF, RCI) : NULL)); in SchedulePostRATDList()
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| HD | CriticalAntiDepBreaker.cpp | 30 CriticalAntiDepBreaker(MachineFunction& MFi, const RegisterClassInfo &RCI) : in CriticalAntiDepBreaker() argument
35 RegClassInfo(RCI), in CriticalAntiDepBreaker()
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| HD | TargetLoweringBase.cpp | 908 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI) in findRepresentativeClass() local
909 SuperRegRC.setBitsInMask(RCI.getMask()); in findRepresentativeClass()
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| HD | AggressiveAntiDepBreaker.cpp | 117 const RegisterClassInfo &RCI, in AggressiveAntiDepBreaker() argument
123 RegClassInfo(RCI), in AggressiveAntiDepBreaker()
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| /trueos/contrib/llvm/include/llvm/CodeGen/ |
| HD | RegisterClassInfo.h | 72 const RCInfo &RCI = RegClass[RC->getID()]; in get() local
73 if (Tag != RCI.Tag) in get()
75 return RCI; in get()
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| HD | RegisterPressure.h | 253 const RegisterClassInfo *RCI;
288 MF(0), TRI(0), RCI(0), LIS(0), MBB(0), P(rp), RequireIntervals(true),
292 MF(0), TRI(0), RCI(0), LIS(0), MBB(0), P(rp), RequireIntervals(false),
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| /trueos/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| HD | TargetLowering.cpp | 2076 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(), in getRegForInlineAsmConstraint() local
2077 E = RI->regclass_end(); RCI != E; ++RCI) { in getRegForInlineAsmConstraint()
2078 const TargetRegisterClass *RC = *RCI; in getRegForInlineAsmConstraint()
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