Home
last modified time | relevance | path

Searched refs:RADEON_GMC_DST_PITCH_OFFSET_CNTL (Results 1 – 8 of 8) sorted by relevance

/trueos/sys/dev/drm/
HDradeon_state.c394 | RADEON_GMC_DST_PITCH_OFFSET_CNTL)) { in radeon_check_and_fixup_packet3()
405 (cmd[1] & RADEON_GMC_DST_PITCH_OFFSET_CNTL)) { in radeon_check_and_fixup_packet3()
775 OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL | in radeon_clear_box()
911 OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL | in radeon_cp_dispatch_clear()
933 OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL | in radeon_cp_dispatch_clear()
1379 RADEON_GMC_DST_PITCH_OFFSET_CNTL | in radeon_cp_dispatch_swap()
1865 RADEON_GMC_DST_PITCH_OFFSET_CNTL | in radeon_cp_dispatch_texture()
HDr300_cmdbuf.c563 | RADEON_GMC_DST_PITCH_OFFSET_CNTL)) { in r300_emit_bitblt_multi()
573 (cmd[1] & RADEON_GMC_DST_PITCH_OFFSET_CNTL)) { in r300_emit_bitblt_multi()
HDradeon_drv.h790 # define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) macro
/trueos/sys/dev/drm2/radeon/
HDradeon_state.c414 | RADEON_GMC_DST_PITCH_OFFSET_CNTL)) { in radeon_check_and_fixup_packet3()
426 (*cmd & RADEON_GMC_DST_PITCH_OFFSET_CNTL)) { in radeon_check_and_fixup_packet3()
798 OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL | in radeon_clear_box()
942 OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL | in radeon_cp_dispatch_clear()
964 OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL | in radeon_cp_dispatch_clear()
1411 RADEON_GMC_DST_PITCH_OFFSET_CNTL | in radeon_cp_dispatch_swap()
1903 RADEON_GMC_DST_PITCH_OFFSET_CNTL | in radeon_cp_dispatch_texture()
HDr300_cmdbuf.c546 | RADEON_GMC_DST_PITCH_OFFSET_CNTL)) { in r300_emit_bitblt_multi()
558 (*cmd1 & RADEON_GMC_DST_PITCH_OFFSET_CNTL)) { in r300_emit_bitblt_multi()
HDradeon_drv.h712 # define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) macro
HDradeon_reg.h753 # define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) macro
HDr100.c923 RADEON_GMC_DST_PITCH_OFFSET_CNTL | in r100_copy_blit()