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Searched refs:R2 (Results 1 – 25 of 89) sorted by relevance

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/trueos/contrib/binutils/opcodes/
HDia64-opc-a.c94 {"add", A, OpX2aVeX4X2b (8, 0, 0, 0, 0), {R1, R2, R3}, EMPTY},
95 {"add", A, OpX2aVeX4X2b (8, 0, 0, 0, 1), {R1, R2, R3, C1}, EMPTY},
96 {"sub", A, OpX2aVeX4X2b (8, 0, 0, 1, 1), {R1, R2, R3}, EMPTY},
97 {"sub", A, OpX2aVeX4X2b (8, 0, 0, 1, 0), {R1, R2, R3, C1}, EMPTY},
98 {"addp4", A, OpX2aVeX4X2b (8, 0, 0, 2, 0), {R1, R2, R3}, EMPTY},
99 {"and", A, OpX2aVeX4X2b (8, 0, 0, 3, 0), {R1, R2, R3}, EMPTY},
100 {"andcm", A, OpX2aVeX4X2b (8, 0, 0, 3, 1), {R1, R2, R3}, EMPTY},
101 {"or", A, OpX2aVeX4X2b (8, 0, 0, 3, 2), {R1, R2, R3}, EMPTY},
102 {"xor", A, OpX2aVeX4X2b (8, 0, 0, 3, 3), {R1, R2, R3}, EMPTY},
103 {"shladd", A, OpX2aVeX4 (8, 0, 0, 4), {R1, R2, CNT2a, R3}, EMPTY},
[all …]
HDia64-opc-i.c117 {"chk.s.i", I0, OpX3 (0, 1), {R2, TGT25b}, EMPTY},
119 {"mov", I, OpX3XbIhWhTag13 (0, 7, 0, 0, 1, 0), {B1, R2}, PSEUDO, 0, NULL},
121 I, OpX3XbIhWh (0, a, b, c, d), {B1, R2, TAG13b}, EMPTY
136 {"mov", I, OpX3 (0, 3), {PR, R2, IMM17}, EMPTY},
138 {"mov", I, FULL17 | OpX3 (0, 3) | FULL17, {PR, R2}, PSEUDO, 0, NULL},
142 {"mov.i", I, OpX3X6 (0, 0, 0x2a), {AR3, R2}, EMPTY},
156 {"dep", I, Op (4), {R1, R2, R3, CPOS6c, LEN4}, EMPTY},
158 {"shrp", I, OpX2X (5, 3, 0), {R1, R2, R3, CNT6}, EMPTY},
168 {"shl", I, OpX2XYb (5, 1, 1, 0), {R1, R2, CPOS6a},
170 {"dep.z", I, OpX2XYb (5, 1, 1, 0), {R1, R2, CPOS6a, LEN6}, EMPTY},
[all …]
HDia64-opc-m.c107 {"mov.m", M, OpX3X6b (1, 0, 0x2a), {AR3, R2}, EMPTY},
109 {"mov", M, OpX3X6b (1, 0, 0x2c), {CR3, R2}, PRIV, 0, NULL},
115 {"mov", M, OpX3X6b (1, 0, 0x2d), {PSR_L, R2}, PRIV, 0, NULL},
116 {"mov", M, OpX3X6b (1, 0, 0x29), {PSR_UM, R2}, EMPTY},
119 {"probe.r", M, OpX3X6b (1, 0, 0x38), {R1, R3, R2}, EMPTY},
120 {"probe.w", M, OpX3X6b (1, 0, 0x39), {R1, R3, R2}, EMPTY},
126 {"itc.d", M0, OpX3X6b (1, 0, 0x2e), {R2}, LAST | PRIV, 0, NULL},
127 {"itc.i", M0, OpX3X6b (1, 0, 0x2f), {R2}, LAST | PRIV, 0, NULL},
129 {"mov", M, OpX3X6b (1, 0, 0x00), {RR_R3, R2}, PRIV, 0, NULL},
130 {"mov", M, OpX3X6b (1, 0, 0x01), {DBR_R3, R2}, PRIV, 0, NULL},
[all …]
/trueos/crypto/openssl/crypto/md4/
HDmd4_dgst.c176 R2(A, B, C, D, X(0), 3, 0x6ED9EBA1L); in md4_block_data_order()
177 R2(D, A, B, C, X(8), 9, 0x6ED9EBA1L); in md4_block_data_order()
178 R2(C, D, A, B, X(4), 11, 0x6ED9EBA1L); in md4_block_data_order()
179 R2(B, C, D, A, X(12), 15, 0x6ED9EBA1L); in md4_block_data_order()
180 R2(A, B, C, D, X(2), 3, 0x6ED9EBA1L); in md4_block_data_order()
181 R2(D, A, B, C, X(10), 9, 0x6ED9EBA1L); in md4_block_data_order()
182 R2(C, D, A, B, X(6), 11, 0x6ED9EBA1L); in md4_block_data_order()
183 R2(B, C, D, A, X(14), 15, 0x6ED9EBA1L); in md4_block_data_order()
184 R2(A, B, C, D, X(1), 3, 0x6ED9EBA1L); in md4_block_data_order()
185 R2(D, A, B, C, X(9), 9, 0x6ED9EBA1L); in md4_block_data_order()
[all …]
/trueos/crypto/openssl/crypto/md5/
HDmd5_dgst.c176 R2(A, B, C, D, X(5), 4, 0xfffa3942L); in md5_block_data_order()
177 R2(D, A, B, C, X(8), 11, 0x8771f681L); in md5_block_data_order()
178 R2(C, D, A, B, X(11), 16, 0x6d9d6122L); in md5_block_data_order()
179 R2(B, C, D, A, X(14), 23, 0xfde5380cL); in md5_block_data_order()
180 R2(A, B, C, D, X(1), 4, 0xa4beea44L); in md5_block_data_order()
181 R2(D, A, B, C, X(4), 11, 0x4bdecfa9L); in md5_block_data_order()
182 R2(C, D, A, B, X(7), 16, 0xf6bb4b60L); in md5_block_data_order()
183 R2(B, C, D, A, X(10), 23, 0xbebfbc70L); in md5_block_data_order()
184 R2(A, B, C, D, X(13), 4, 0x289b7ec6L); in md5_block_data_order()
185 R2(D, A, B, C, X(0), 11, 0xeaa127faL); in md5_block_data_order()
[all …]
/trueos/contrib/wpa/src/crypto/
HDsha1-internal.c145 #define R2(v,w,x,y,z,i) \ macro
198 R2(a,b,c,d,e,20); R2(e,a,b,c,d,21); R2(d,e,a,b,c,22); R2(c,d,e,a,b,23); in SHA1Transform()
199 R2(b,c,d,e,a,24); R2(a,b,c,d,e,25); R2(e,a,b,c,d,26); R2(d,e,a,b,c,27); in SHA1Transform()
200 R2(c,d,e,a,b,28); R2(b,c,d,e,a,29); R2(a,b,c,d,e,30); R2(e,a,b,c,d,31); in SHA1Transform()
201 R2(d,e,a,b,c,32); R2(c,d,e,a,b,33); R2(b,c,d,e,a,34); R2(a,b,c,d,e,35); in SHA1Transform()
202 R2(e,a,b,c,d,36); R2(d,e,a,b,c,37); R2(c,d,e,a,b,38); R2(b,c,d,e,a,39); in SHA1Transform()
/trueos/contrib/ldns/
HDsha1.c40 #define R2(v,w,x,y,z,i) z+=(w^x^y)+blk(i)+0x6ED9EBA1+rol(v,5);w=rol(w,30); macro
76 R2(a,b,c,d,e,20); R2(e,a,b,c,d,21); R2(d,e,a,b,c,22); R2(c,d,e,a,b,23); in ldns_sha1_transform()
77 R2(b,c,d,e,a,24); R2(a,b,c,d,e,25); R2(e,a,b,c,d,26); R2(d,e,a,b,c,27); in ldns_sha1_transform()
78 R2(c,d,e,a,b,28); R2(b,c,d,e,a,29); R2(a,b,c,d,e,30); R2(e,a,b,c,d,31); in ldns_sha1_transform()
79 R2(d,e,a,b,c,32); R2(c,d,e,a,b,33); R2(b,c,d,e,a,34); R2(a,b,c,d,e,35); in ldns_sha1_transform()
80 R2(e,a,b,c,d,36); R2(d,e,a,b,c,37); R2(c,d,e,a,b,38); R2(b,c,d,e,a,39); in ldns_sha1_transform()
/trueos/crypto/openssl/crypto/md5/asm/
HDmd5-586.pl94 sub R2 subroutine
239 &R2( 0,-1,$A,$B,$C,$D,$X,32, 4,0xfffa3942);
240 &R2( 1, 0,$D,$A,$B,$C,$X,33,11,0x8771f681);
241 &R2( 2, 0,$C,$D,$A,$B,$X,34,16,0x6d9d6122);
242 &R2( 3, 0,$B,$C,$D,$A,$X,35,23,0xfde5380c);
243 &R2( 4, 0,$A,$B,$C,$D,$X,36, 4,0xa4beea44);
244 &R2( 5, 0,$D,$A,$B,$C,$X,37,11,0x4bdecfa9);
245 &R2( 6, 0,$C,$D,$A,$B,$X,38,16,0xf6bb4b60);
246 &R2( 7, 0,$B,$C,$D,$A,$X,39,23,0xbebfbc70);
247 &R2( 8, 0,$A,$B,$C,$D,$X,40, 4,0x289b7ec6);
[all …]
/trueos/contrib/llvm/lib/Target/R600/
HDAMDGPUISelDAGToDAG.cpp58 bool SelectADDRParam(SDValue Addr, SDValue& R1, SDValue& R2);
59 bool SelectADDR(SDValue N, SDValue &R1, SDValue &R2);
60 bool SelectADDR64(SDValue N, SDValue &R1, SDValue &R2);
142 SDValue Addr, SDValue& R1, SDValue& R2) { in SelectADDRParam() argument
147 R2 = CurDAG->getTargetConstant(0, MVT::i32); in SelectADDRParam()
150 R2 = CurDAG->getTargetConstant(0, MVT::i32); in SelectADDRParam()
154 R2 = Addr.getOperand(1); in SelectADDRParam()
157 R2 = CurDAG->getTargetConstant(0, MVT::i32); in SelectADDRParam()
162 bool AMDGPUDAGToDAGISel::SelectADDR(SDValue Addr, SDValue& R1, SDValue& R2) { in SelectADDR() argument
167 return SelectADDRParam(Addr, R1, R2); in SelectADDR()
[all …]
/trueos/contrib/llvm/lib/Target/SystemZ/
HDSystemZInstrFormats.td178 bits<4> R2;
184 let Inst{35-32} = R2;
232 bits<4> R2;
239 let Inst{35-32} = R2;
266 bits<4> R2;
270 let Inst{3-0} = R2;
280 bits<4> R2;
286 let Inst{3-0} = R2;
295 bits<4> R2;
300 let Inst{3-0} = R2;
[all …]
HDSystemZInstrInfo.td42 def BR : InstRR<0x07, (outs), (ins ADDR64:$R2),
43 "br\t$R2", [(brind ADDR64:$R2)]>;
70 def AsmBCR : InstRR<0x07, (outs), (ins uimm8zx4:$R1, GR64:$R2),
71 "bcr\t$R1, $R2", []>;
84 def RJ : InstRIEb<0xEC76, (outs), (ins GR32:$R1, GR32:$R2, ccmask:$M3,
86 "crj"##pos1##"\t$R1, $R2, "##pos2##"$RI4", []>;
87 def GRJ : InstRIEb<0xEC64, (outs), (ins GR64:$R1, GR64:$R2, ccmask:$M3,
89 "cgrj"##pos1##"\t$R1, $R2, "##pos2##"$RI4", []>;
96 def LRJ : InstRIEb<0xEC77, (outs), (ins GR32:$R1, GR32:$R2, ccmask:$M3,
98 "clrj"##pos1##"\t$R1, $R2, "##pos2##"$RI4", []>;
[all …]
/trueos/contrib/llvm/tools/clang/lib/Analysis/
HDReachableCode.cpp186 SourceRange &R2) { in GetUnreachableLoc() argument
187 R1 = R2 = SourceRange(); in GetUnreachableLoc()
205 R2 = CAO->getRHS()->getSourceRange(); in GetUnreachableLoc()
222 R2 = ASE->getRHS()->getSourceRange(); in GetUnreachableLoc()
251 SourceRange R1, R2; in reportDeadCode() local
252 SourceLocation Loc = GetUnreachableLoc(S, R1, R2); in reportDeadCode()
253 CB.HandleUnreachable(Loc, R1, R2); in reportDeadCode()
/trueos/contrib/llvm/lib/Target/XCore/
HDXCoreCallingConv.td16 // i32 are returned in registers R0, R1, R2, R3
17 CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>
31 CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>,
HDXCoreRegisterInfo.td28 def R2 : Ri< 2, "r2">, DwarfRegNum<[2]>;
47 (add R0, R1, R2, R3,
55 (add R0, R1, R2, R3,
/trueos/contrib/llvm/lib/Target/ARM/
HDARMCallingConv.h31 static const uint16_t RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAPCS()
74 static const uint16_t HiRegList[] = { ARM::R0, ARM::R2 }; in f64AssignAAPCS()
77 static const uint16_t GPRArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAAPCS()
126 static const uint16_t HiRegList[] = { ARM::R0, ARM::R2 }; in f64RetAssign()
HDARMCallingConv.td34 CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>,
51 CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>,
52 CCIfType<[i64], CCAssignToRegWithShadow<[R0, R2], [R1, R3]>>
98 // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, SpLim
113 CCIfType<[i32], CCIfAlign<"8", CCAssignToRegWithShadow<[R0, R2], [R0, R1]>>>,
115 CCAssignToReg<[R0, R1, R2, R3]>>>,
125 CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>,
126 CCIfType<[i64], CCAssignToRegWithShadow<[R0, R2], [R1, R3]>>
/trueos/contrib/llvm/lib/Target/Sparc/
HDSparcISelDAGToDAG.cpp47 bool SelectADDRrr(SDValue N, SDValue &R1, SDValue &R2);
118 bool SparcDAGToDAGISel::SelectADDRrr(SDValue Addr, SDValue &R1, SDValue &R2) { in SelectADDRrr() argument
133 R2 = Addr.getOperand(1); in SelectADDRrr()
138 R2 = CurDAG->getRegister(SP::G0, getTargetLowering()->getPointerTy()); in SelectADDRrr()
/trueos/contrib/libc++/include/
Dratio30 template <class R1, class R2> using ratio_add = ...;
31 template <class R1, class R2> using ratio_subtract = ...;
32 template <class R1, class R2> using ratio_multiply = ...;
33 template <class R1, class R2> using ratio_divide = ...;
36 template <class R1, class R2> struct ratio_equal;
37 template <class R1, class R2> struct ratio_not_equal;
38 template <class R1, class R2> struct ratio_less;
39 template <class R1, class R2> struct ratio_less_equal;
40 template <class R1, class R2> struct ratio_greater;
41 template <class R1, class R2> struct ratio_greater_equal;
/trueos/contrib/gcc/
HDconflict.c115 #define CONFLICT_HASH_FN(R1, R2) ((R2) * ((R2) - 1) / 2 + (R1)) argument
/trueos/contrib/llvm/lib/Target/Hexagon/
HDHexagonCallingConv.td20 CCIfType<[i32, f32], CCAssignToReg<[R0, R1, R2, R3, R4, R5]>>,
30 CCIfType<[f32, i32, i16, i8], CCAssignToReg<[R0, R1, R2, R3, R4, R5]>>,
HDHexagonVarargsCallingConvention.h53 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4, in CC_Hexagon32_VarArgs()
109 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4, in RetCC_Hexagon32_VarArgs()
/trueos/contrib/llvm/patches/
HDpatch-r262261-llvm-r198910-sparc.diff116 ; CHECK: or %g0, 2, [[R2:%[go][0-7]]]
117 ; CHECK: st [[R2]], [%sp+100]
203 ; abs44: add %[[R1]], %m44(.LCPI0_0), %[[R2:[gilo][0-7]]]
204 ; abs44: sllx %[[R2]], 12, %[[R3:[gilo][0-7]]]
216 ; abs64: ld [%[[R5]]+%[[R2]]], %f1
252 ; abs44: add %[[R1]], %m44(G), %[[R2:[gilo][0-7]]]
253 ; abs44: sllx %[[R2]], 12, %[[R3:[gilo][0-7]]]
265 ; abs64: ldub [%[[R5]]+%[[R2]]], %o0
HDpatch-r262261-llvm-r199028-sparc.diff58 ; abs44: add %[[R1]], %m44(.LCPI0_0), %[[R2:[gilo][0-7]]]
59 ; abs44: sllx %[[R2]], 12, %[[R3:[gilo][0-7]]]
70 -; abs64: ld [%[[R5]]+%[[R2]]], %f1
71 +; abs64: ld [%[[R5]]+%[[R2]]], %f0
HDpatch-r262261-llvm-r199775-sparc.diff189 ; v8abs: add [[R1]], %tie_lo10(extern_symbol), %[[R2:[goli][0-7]]]
190 ; v8abs: ld [%[[GOTBASE]]+%[[R2]]], [[R3:%[goli][0-7]]], %tie_ld(extern_symbol)
199 ; v9abs: add [[R1]], %tie_lo10(extern_symbol), %[[R2:[goli][0-7]]]
200 ; v9abs: ldx [%[[GOTBASE]]+%[[R2]]], [[R3:%[goli][0-7]]], %tie_ldx(extern_symbol)
/trueos/contrib/llvm/include/llvm/Support/
HDMathExtras.h229 #define R2(n) n, n + 2 * 64, n + 1 * 64, n + 3 * 64 macro
230 #define R4(n) R2(n), R2(n + 2 * 16), R2(n + 1 * 16), R2(n + 3 * 16)

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