1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 2 * All Rights Reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the 13 * next paragraph) shall be included in all copies or substantial portions 14 * of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <sys/cdefs.h> 26 __FBSDID("$FreeBSD$"); 27 28 #ifndef _I915_REG_H_ 29 #define _I915_REG_H_ 30 31 #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a))) 32 33 #define _PORT(port, a, b) ((a) + (port)*((b)-(a))) 34 35 #define _MASKED_BIT_ENABLE(a) (((a) << 16) | (a)) 36 #define _MASKED_BIT_DISABLE(a) ((a) << 16) 37 38 /* 39 * The Bridge device's PCI config space has information about the 40 * fb aperture size and the amount of pre-reserved memory. 41 * This is all handled in the intel-gtt.ko module. i915.ko only 42 * cares about the vga bit for the vga rbiter. 43 */ 44 #define INTEL_GMCH_CTRL 0x52 45 #define INTEL_GMCH_VGA_DISABLE (1 << 1) 46 47 /* PCI config space */ 48 49 #define HPLLCC 0xc0 /* 855 only */ 50 #define GC_CLOCK_CONTROL_MASK (0xf << 0) 51 #define GC_CLOCK_133_200 (0 << 0) 52 #define GC_CLOCK_100_200 (1 << 0) 53 #define GC_CLOCK_100_133 (2 << 0) 54 #define GC_CLOCK_166_250 (3 << 0) 55 #define GCFGC2 0xda 56 #define GCFGC 0xf0 /* 915+ only */ 57 #define GC_LOW_FREQUENCY_ENABLE (1 << 7) 58 #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) 59 #define GC_DISPLAY_CLOCK_333_MHZ (4 << 4) 60 #define GC_DISPLAY_CLOCK_MASK (7 << 4) 61 #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0) 62 #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0) 63 #define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0) 64 #define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0) 65 #define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0) 66 #define I965_GC_RENDER_CLOCK_MASK (0xf << 0) 67 #define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0) 68 #define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0) 69 #define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0) 70 #define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0) 71 #define I945_GC_RENDER_CLOCK_MASK (7 << 0) 72 #define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0) 73 #define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0) 74 #define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0) 75 #define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0) 76 #define I915_GC_RENDER_CLOCK_MASK (7 << 0) 77 #define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0) 78 #define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0) 79 #define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0) 80 #define LBB 0xf4 81 82 /* Graphics reset regs */ 83 #define I965_GDRST 0xc0 /* PCI config register */ 84 #define ILK_GDSR 0x2ca4 /* MCHBAR offset */ 85 #define GRDOM_FULL (0<<2) 86 #define GRDOM_RENDER (1<<2) 87 #define GRDOM_MEDIA (3<<2) 88 #define GRDOM_RESET_ENABLE (1<<0) 89 90 #define GEN6_MBCUNIT_SNPCR 0x900c /* for LLC config */ 91 #define GEN6_MBC_SNPCR_SHIFT 21 92 #define GEN6_MBC_SNPCR_MASK (3<<21) 93 #define GEN6_MBC_SNPCR_MAX (0<<21) 94 #define GEN6_MBC_SNPCR_MED (1<<21) 95 #define GEN6_MBC_SNPCR_LOW (2<<21) 96 #define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */ 97 98 #define GEN6_MBCTL 0x0907c 99 #define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4) 100 #define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3) 101 #define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2) 102 #define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1) 103 #define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0) 104 105 #define GEN6_GDRST 0x941c 106 #define GEN6_GRDOM_FULL (1 << 0) 107 #define GEN6_GRDOM_RENDER (1 << 1) 108 #define GEN6_GRDOM_MEDIA (1 << 2) 109 #define GEN6_GRDOM_BLT (1 << 3) 110 111 /* PPGTT stuff */ 112 #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) 113 114 #define GEN6_PDE_VALID (1 << 0) 115 #define GEN6_PDE_LARGE_PAGE (2 << 0) /* use 32kb pages */ 116 /* gen6+ has bit 11-4 for physical addr bit 39-32 */ 117 #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 118 119 #define GEN6_PTE_VALID (1 << 0) 120 #define GEN6_PTE_UNCACHED (1 << 1) 121 #define GEN6_PTE_CACHE_LLC (2 << 1) 122 #define GEN6_PTE_CACHE_LLC_MLC (3 << 1) 123 #define GEN6_PTE_CACHE_BITS (3 << 1) 124 #define GEN6_PTE_GFDT (1 << 3) 125 #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 126 127 #define RING_PP_DIR_BASE(ring) ((ring)->mmio_base+0x228) 128 #define RING_PP_DIR_BASE_READ(ring) ((ring)->mmio_base+0x518) 129 #define RING_PP_DIR_DCLV(ring) ((ring)->mmio_base+0x220) 130 #define PP_DIR_DCLV_2G 0xffffffff 131 132 #define GAM_ECOCHK 0x4090 133 #define ECOCHK_SNB_BIT (1<<10) 134 #define ECOCHK_PPGTT_CACHE64B (0x3<<3) 135 #define ECOCHK_PPGTT_CACHE4B (0x0<<3) 136 137 #define GAC_ECO_BITS 0x14090 138 #define ECOBITS_PPGTT_CACHE64B (3<<8) 139 #define ECOBITS_PPGTT_CACHE4B (0<<8) 140 141 #define GAB_CTL 0x24000 142 #define GAB_CTL_CONT_AFTER_PAGEFAULT (1<<8) 143 144 /* VGA stuff */ 145 146 #define VGA_ST01_MDA 0x3ba 147 #define VGA_ST01_CGA 0x3da 148 149 #define VGA_MSR_WRITE 0x3c2 150 #define VGA_MSR_READ 0x3cc 151 #define VGA_MSR_MEM_EN (1<<1) 152 #define VGA_MSR_CGA_MODE (1<<0) 153 154 #define VGA_SR_INDEX 0x3c4 155 #define VGA_SR_DATA 0x3c5 156 157 #define VGA_AR_INDEX 0x3c0 158 #define VGA_AR_VID_EN (1<<5) 159 #define VGA_AR_DATA_WRITE 0x3c0 160 #define VGA_AR_DATA_READ 0x3c1 161 162 #define VGA_GR_INDEX 0x3ce 163 #define VGA_GR_DATA 0x3cf 164 /* GR05 */ 165 #define VGA_GR_MEM_READ_MODE_SHIFT 3 166 #define VGA_GR_MEM_READ_MODE_PLANE 1 167 /* GR06 */ 168 #define VGA_GR_MEM_MODE_MASK 0xc 169 #define VGA_GR_MEM_MODE_SHIFT 2 170 #define VGA_GR_MEM_A0000_AFFFF 0 171 #define VGA_GR_MEM_A0000_BFFFF 1 172 #define VGA_GR_MEM_B0000_B7FFF 2 173 #define VGA_GR_MEM_B0000_BFFFF 3 174 175 #define VGA_DACMASK 0x3c6 176 #define VGA_DACRX 0x3c7 177 #define VGA_DACWX 0x3c8 178 #define VGA_DACDATA 0x3c9 179 180 #define VGA_CR_INDEX_MDA 0x3b4 181 #define VGA_CR_DATA_MDA 0x3b5 182 #define VGA_CR_INDEX_CGA 0x3d4 183 #define VGA_CR_DATA_CGA 0x3d5 184 185 /* 186 * Memory interface instructions used by the kernel 187 */ 188 #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags)) 189 190 #define MI_NOOP MI_INSTR(0, 0) 191 #define MI_USER_INTERRUPT MI_INSTR(0x02, 0) 192 #define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0) 193 #define MI_WAIT_FOR_OVERLAY_FLIP (1<<16) 194 #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6) 195 #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) 196 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) 197 #define MI_FLUSH MI_INSTR(0x04, 0) 198 #define MI_READ_FLUSH (1 << 0) 199 #define MI_EXE_FLUSH (1 << 1) 200 #define MI_NO_WRITE_FLUSH (1 << 2) 201 #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */ 202 #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */ 203 #define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */ 204 #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0) 205 #define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0) 206 #define MI_SUSPEND_FLUSH_EN (1<<0) 207 #define MI_REPORT_HEAD MI_INSTR(0x07, 0) 208 #define MI_OVERLAY_FLIP MI_INSTR(0x11, 0) 209 #define MI_OVERLAY_CONTINUE (0x0<<21) 210 #define MI_OVERLAY_ON (0x1<<21) 211 #define MI_OVERLAY_OFF (0x2<<21) 212 #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0) 213 #define MI_DISPLAY_FLIP MI_INSTR(0x14, 2) 214 #define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1) 215 #define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20) 216 #define MI_ARB_ON_OFF MI_INSTR(0x08, 0) 217 #define MI_ARB_ENABLE (1<<0) 218 #define MI_ARB_DISABLE (0<<0) 219 220 #define MI_SET_CONTEXT MI_INSTR(0x18, 0) 221 #define MI_MM_SPACE_GTT (1<<8) 222 #define MI_MM_SPACE_PHYSICAL (0<<8) 223 #define MI_SAVE_EXT_STATE_EN (1<<3) 224 #define MI_RESTORE_EXT_STATE_EN (1<<2) 225 #define MI_FORCE_RESTORE (1<<1) 226 #define MI_RESTORE_INHIBIT (1<<0) 227 #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1) 228 #define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */ 229 #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1) 230 #define MI_STORE_DWORD_INDEX_SHIFT 2 231 /* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM: 232 * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw 233 * simply ignores the register load under certain conditions. 234 * - One can actually load arbitrary many arbitrary registers: Simply issue x 235 * address/value pairs. Don't overdue it, though, x <= 2^4 must hold! 236 */ 237 #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*x-1) 238 #define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */ 239 #define MI_INVALIDATE_TLB (1<<18) 240 #define MI_INVALIDATE_BSD (1<<7) 241 #define MI_BATCH_BUFFER MI_INSTR(0x30, 1) 242 #define MI_BATCH_NON_SECURE (1) 243 #define MI_BATCH_NON_SECURE_I965 (1<<8) 244 #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0) 245 #define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */ 246 #define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6+ */ 247 #define MI_SEMAPHORE_GLOBAL_GTT (1<<22) 248 #define MI_SEMAPHORE_UPDATE (1<<21) 249 #define MI_SEMAPHORE_COMPARE (1<<20) 250 #define MI_SEMAPHORE_REGISTER (1<<18) 251 #define MI_SEMAPHORE_SYNC_RV (2<<16) 252 #define MI_SEMAPHORE_SYNC_RB (0<<16) 253 #define MI_SEMAPHORE_SYNC_VR (0<<16) 254 #define MI_SEMAPHORE_SYNC_VB (2<<16) 255 #define MI_SEMAPHORE_SYNC_BR (2<<16) 256 #define MI_SEMAPHORE_SYNC_BV (0<<16) 257 #define MI_SEMAPHORE_SYNC_INVALID (1<<0) 258 /* 259 * 3D instructions used by the kernel 260 */ 261 #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags)) 262 263 #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24)) 264 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 265 #define SC_UPDATE_SCISSOR (0x1<<1) 266 #define SC_ENABLE_MASK (0x1<<0) 267 #define SC_ENABLE (0x1<<0) 268 #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16)) 269 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1)) 270 #define SCI_YMIN_MASK (0xffff<<16) 271 #define SCI_XMIN_MASK (0xffff<<0) 272 #define SCI_YMAX_MASK (0xffff<<16) 273 #define SCI_XMAX_MASK (0xffff<<0) 274 #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 275 #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1) 276 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0) 277 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) 278 #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4) 279 #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0) 280 #define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1) 281 #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3)) 282 #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2) 283 #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4) 284 #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) 285 #define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5) 286 #define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21) 287 #define XY_SRC_COPY_BLT_WRITE_RGB (1<<20) 288 #define BLT_DEPTH_8 (0<<24) 289 #define BLT_DEPTH_16_565 (1<<24) 290 #define BLT_DEPTH_16_1555 (2<<24) 291 #define BLT_DEPTH_32 (3<<24) 292 #define BLT_ROP_GXCOPY (0xcc<<16) 293 #define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */ 294 #define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */ 295 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2) 296 #define ASYNC_FLIP (1<<22) 297 #define DISPLAY_PLANE_A (0<<20) 298 #define DISPLAY_PLANE_B (1<<20) 299 #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2)) 300 #define PIPE_CONTROL_CS_STALL (1<<20) 301 #define PIPE_CONTROL_QW_WRITE (1<<14) 302 #define PIPE_CONTROL_DEPTH_STALL (1<<13) 303 #define PIPE_CONTROL_WRITE_FLUSH (1<<12) 304 #define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */ 305 #define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on Ironlake */ 306 #define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */ 307 #define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9) 308 #define PIPE_CONTROL_NOTIFY (1<<8) 309 #define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4) 310 #define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3) 311 #define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2) 312 #define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1) 313 #define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0) 314 #define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */ 315 316 317 /* 318 * Reset registers 319 */ 320 #define DEBUG_RESET_I830 0x6070 321 #define DEBUG_RESET_FULL (1<<7) 322 #define DEBUG_RESET_RENDER (1<<8) 323 #define DEBUG_RESET_DISPLAY (1<<9) 324 325 /* 326 * DPIO - a special bus for various display related registers to hide behind: 327 * 0x800c: m1, m2, n, p1, p2, k dividers 328 * 0x8014: REF and SFR select 329 * 0x8014: N divider, VCO select 330 * 0x801c/3c: core clock bits 331 * 0x8048/68: low pass filter coefficients 332 * 0x8100: fast clock controls 333 */ 334 #define DPIO_PKT 0x2100 335 #define DPIO_RID (0<<24) 336 #define DPIO_OP_WRITE (1<<16) 337 #define DPIO_OP_READ (0<<16) 338 #define DPIO_PORTID (0x12<<8) 339 #define DPIO_BYTE (0xf<<4) 340 #define DPIO_BUSY (1<<0) /* status only */ 341 #define DPIO_DATA 0x2104 342 #define DPIO_REG 0x2108 343 #define DPIO_CTL 0x2110 344 #define DPIO_MODSEL1 (1<<3) /* if ref clk b == 27 */ 345 #define DPIO_MODSEL0 (1<<2) /* if ref clk a == 27 */ 346 #define DPIO_SFR_BYPASS (1<<1) 347 #define DPIO_RESET (1<<0) 348 349 #define _DPIO_DIV_A 0x800c 350 #define DPIO_POST_DIV_SHIFT (28) /* 3 bits */ 351 #define DPIO_K_SHIFT (24) /* 4 bits */ 352 #define DPIO_P1_SHIFT (21) /* 3 bits */ 353 #define DPIO_P2_SHIFT (16) /* 5 bits */ 354 #define DPIO_N_SHIFT (12) /* 4 bits */ 355 #define DPIO_ENABLE_CALIBRATION (1<<11) 356 #define DPIO_M1DIV_SHIFT (8) /* 3 bits */ 357 #define DPIO_M2DIV_MASK 0xff 358 #define _DPIO_DIV_B 0x802c 359 #define DPIO_DIV(pipe) _PIPE(pipe, _DPIO_DIV_A, _DPIO_DIV_B) 360 361 #define _DPIO_REFSFR_A 0x8014 362 #define DPIO_REFSEL_OVERRIDE 27 363 #define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */ 364 #define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */ 365 #define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */ 366 #define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */ 367 #define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */ 368 #define _DPIO_REFSFR_B 0x8034 369 #define DPIO_REFSFR(pipe) _PIPE(pipe, _DPIO_REFSFR_A, _DPIO_REFSFR_B) 370 371 #define _DPIO_CORE_CLK_A 0x801c 372 #define _DPIO_CORE_CLK_B 0x803c 373 #define DPIO_CORE_CLK(pipe) _PIPE(pipe, _DPIO_CORE_CLK_A, _DPIO_CORE_CLK_B) 374 375 #define _DPIO_LFP_COEFF_A 0x8048 376 #define _DPIO_LFP_COEFF_B 0x8068 377 #define DPIO_LFP_COEFF(pipe) _PIPE(pipe, _DPIO_LFP_COEFF_A, _DPIO_LFP_COEFF_B) 378 379 #define DPIO_FASTCLK_DISABLE 0x8100 380 381 /* 382 * Fence registers 383 */ 384 #define FENCE_REG_830_0 0x2000 385 #define FENCE_REG_945_8 0x3000 386 #define I830_FENCE_START_MASK 0x07f80000 387 #define I830_FENCE_TILING_Y_SHIFT 12 388 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8) 389 #define I830_FENCE_PITCH_SHIFT 4 390 #define I830_FENCE_REG_VALID (1<<0) 391 #define I915_FENCE_MAX_PITCH_VAL 4 392 #define I830_FENCE_MAX_PITCH_VAL 6 393 #define I830_FENCE_MAX_SIZE_VAL (1<<8) 394 395 #define I915_FENCE_START_MASK 0x0ff00000 396 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8) 397 398 #define FENCE_REG_965_0 0x03000 399 #define I965_FENCE_PITCH_SHIFT 2 400 #define I965_FENCE_TILING_Y_SHIFT 1 401 #define I965_FENCE_REG_VALID (1<<0) 402 #define I965_FENCE_MAX_PITCH_VAL 0x0400 403 404 #define FENCE_REG_SANDYBRIDGE_0 0x100000 405 #define SANDYBRIDGE_FENCE_PITCH_SHIFT 32 406 407 /* control register for cpu gtt access */ 408 #define TILECTL 0x101000 409 #define TILECTL_SWZCTL (1 << 0) 410 #define TILECTL_TLB_PREFETCH_DIS (1 << 2) 411 #define TILECTL_BACKSNOOP_DIS (1 << 3) 412 413 /* 414 * Instruction and interrupt control regs 415 */ 416 #define PGTBL_ER 0x02024 417 #define RENDER_RING_BASE 0x02000 418 #define BSD_RING_BASE 0x04000 419 #define GEN6_BSD_RING_BASE 0x12000 420 #define BLT_RING_BASE 0x22000 421 #define RING_TAIL(base) ((base)+0x30) 422 #define RING_HEAD(base) ((base)+0x34) 423 #define RING_START(base) ((base)+0x38) 424 #define RING_CTL(base) ((base)+0x3c) 425 #define RING_SYNC_0(base) ((base)+0x40) 426 #define RING_SYNC_1(base) ((base)+0x44) 427 #define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE)) 428 #define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE)) 429 #define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE)) 430 #define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE)) 431 #define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE)) 432 #define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE)) 433 #define RING_MAX_IDLE(base) ((base)+0x54) 434 #define RING_HWS_PGA(base) ((base)+0x80) 435 #define RING_HWS_PGA_GEN6(base) ((base)+0x2080) 436 #define ARB_MODE 0x04030 437 #define ARB_MODE_SWIZZLE_SNB (1<<4) 438 #define ARB_MODE_SWIZZLE_IVB (1<<5) 439 #define RENDER_HWS_PGA_GEN7 (0x04080) 440 #define RING_FAULT_REG(ring) (0x4094 + 0x100*(ring)->id) 441 #define DONE_REG 0x40b0 442 #define BSD_HWS_PGA_GEN7 (0x04180) 443 #define BLT_HWS_PGA_GEN7 (0x04280) 444 #define RING_ACTHD(base) ((base)+0x74) 445 #define RING_NOPID(base) ((base)+0x94) 446 #define RING_IMR(base) ((base)+0xa8) 447 #define TAIL_ADDR 0x001FFFF8 448 #define HEAD_WRAP_COUNT 0xFFE00000 449 #define HEAD_WRAP_ONE 0x00200000 450 #define HEAD_ADDR 0x001FFFFC 451 #define RING_NR_PAGES 0x001FF000 452 #define RING_REPORT_MASK 0x00000006 453 #define RING_REPORT_64K 0x00000002 454 #define RING_REPORT_128K 0x00000004 455 #define RING_NO_REPORT 0x00000000 456 #define RING_VALID_MASK 0x00000001 457 #define RING_VALID 0x00000001 458 #define RING_INVALID 0x00000000 459 #define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */ 460 #define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */ 461 #define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */ 462 #if 0 463 #define PRB0_TAIL 0x02030 464 #define PRB0_HEAD 0x02034 465 #define PRB0_START 0x02038 466 #define PRB0_CTL 0x0203c 467 #define PRB1_TAIL 0x02040 /* 915+ only */ 468 #define PRB1_HEAD 0x02044 /* 915+ only */ 469 #define PRB1_START 0x02048 /* 915+ only */ 470 #define PRB1_CTL 0x0204c /* 915+ only */ 471 #endif 472 #define IPEIR_I965 0x02064 473 #define IPEHR_I965 0x02068 474 #define INSTDONE_I965 0x0206c 475 #define RING_IPEIR(base) ((base)+0x64) 476 #define RING_IPEHR(base) ((base)+0x68) 477 #define RING_INSTDONE(base) ((base)+0x6c) 478 #define RING_INSTPS(base) ((base)+0x70) 479 #define RING_DMA_FADD(base) ((base)+0x78) 480 #define RING_INSTPM(base) ((base)+0xc0) 481 #define INSTPS 0x02070 /* 965+ only */ 482 #define INSTDONE1 0x0207c /* 965+ only */ 483 #define ACTHD_I965 0x02074 484 #define HWS_PGA 0x02080 485 #define HWS_ADDRESS_MASK 0xfffff000 486 #define HWS_START_ADDRESS_SHIFT 4 487 #define PWRCTXA 0x2088 /* 965GM+ only */ 488 #define PWRCTX_EN (1<<0) 489 #define IPEIR 0x02088 490 #define IPEHR 0x0208c 491 #define INSTDONE 0x02090 492 #define NOPID 0x02094 493 #define HWSTAM 0x02098 494 #define DMA_FADD_I8XX 0x020d0 495 496 #define ERROR_GEN6 0x040a0 497 498 /* GM45+ chicken bits -- debug workaround bits that may be required 499 * for various sorts of correct behavior. The top 16 bits of each are 500 * the enables for writing to the corresponding low bit. 501 */ 502 #define _3D_CHICKEN 0x02084 503 #define _3D_CHICKEN2 0x0208c 504 /* Disables pipelining of read flushes past the SF-WIZ interface. 505 * Required on all Ironlake steppings according to the B-Spec, but the 506 * particular danger of not doing so is not specified. 507 */ 508 # define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14) 509 #define _3D_CHICKEN3 0x02090 510 #define _3D_CHICKEN_SF_DISABLE_FASTCLIP_CULL (1 << 5) 511 512 #define MI_MODE 0x0209c 513 # define VS_TIMER_DISPATCH (1 << 6) 514 # define MI_FLUSH_ENABLE (1 << 12) 515 516 #define GFX_MODE 0x02520 517 #define GFX_MODE_GEN7 0x0229c 518 #define RING_MODE_GEN7(ring) ((ring)->mmio_base+0x29c) 519 #define GFX_RUN_LIST_ENABLE (1<<15) 520 #define GFX_TLB_INVALIDATE_ALWAYS (1<<13) 521 #define GFX_SURFACE_FAULT_ENABLE (1<<12) 522 #define GFX_REPLAY_MODE (1<<11) 523 #define GFX_PSMI_GRANULARITY (1<<10) 524 #define GFX_PPGTT_ENABLE (1<<9) 525 526 #define SCPD0 0x0209c /* 915+ only */ 527 #define IER 0x020a0 528 #define IIR 0x020a4 529 #define IMR 0x020a8 530 #define ISR 0x020ac 531 #define VLV_IIR_RW 0x182084 532 #define VLV_IER 0x1820a0 533 #define VLV_IIR 0x1820a4 534 #define VLV_IMR 0x1820a8 535 #define VLV_ISR 0x1820ac 536 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18) 537 #define I915_DISPLAY_PORT_INTERRUPT (1<<17) 538 #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15) 539 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */ 540 #define I915_HWB_OOM_INTERRUPT (1<<13) 541 #define I915_SYNC_STATUS_INTERRUPT (1<<12) 542 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11) 543 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10) 544 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9) 545 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8) 546 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7) 547 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6) 548 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5) 549 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4) 550 #define I915_DEBUG_INTERRUPT (1<<2) 551 #define I915_USER_INTERRUPT (1<<1) 552 #define I915_ASLE_INTERRUPT (1<<0) 553 #define I915_BSD_USER_INTERRUPT (1<<25) 554 #define EIR 0x020b0 555 #define EMR 0x020b4 556 #define ESR 0x020b8 557 #define GM45_ERROR_PAGE_TABLE (1<<5) 558 #define GM45_ERROR_MEM_PRIV (1<<4) 559 #define I915_ERROR_PAGE_TABLE (1<<4) 560 #define GM45_ERROR_CP_PRIV (1<<3) 561 #define I915_ERROR_MEMORY_REFRESH (1<<1) 562 #define I915_ERROR_INSTRUCTION (1<<0) 563 #define INSTPM 0x020c0 564 #define INSTPM_SELF_EN (1<<12) /* 915GM only */ 565 #define INSTPM_AGPBUSY_DIS (1<<11) /* gen3: when disabled, pending interrupts 566 will not assert AGPBUSY# and will only 567 be delivered when out of C3. */ 568 #define INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */ 569 #define ACTHD 0x020c8 570 #define FW_BLC 0x020d8 571 #define FW_BLC2 0x020dc 572 #define FW_BLC_SELF 0x020e0 /* 915+ only */ 573 #define FW_BLC_SELF_EN_MASK (1<<31) 574 #define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */ 575 #define FW_BLC_SELF_EN (1<<15) /* 945 only */ 576 #define MM_BURST_LENGTH 0x00700000 577 #define MM_FIFO_WATERMARK 0x0001F000 578 #define LM_BURST_LENGTH 0x00000700 579 #define LM_FIFO_WATERMARK 0x0000001F 580 #define MI_ARB_STATE 0x020e4 /* 915+ only */ 581 582 /* Make render/texture TLB fetches lower priorty than associated data 583 * fetches. This is not turned on by default 584 */ 585 #define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15) 586 587 /* Isoch request wait on GTT enable (Display A/B/C streams). 588 * Make isoch requests stall on the TLB update. May cause 589 * display underruns (test mode only) 590 */ 591 #define MI_ARB_ISOCH_WAIT_GTT (1 << 14) 592 593 /* Block grant count for isoch requests when block count is 594 * set to a finite value. 595 */ 596 #define MI_ARB_BLOCK_GRANT_MASK (3 << 12) 597 #define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */ 598 #define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */ 599 #define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */ 600 #define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */ 601 602 /* Enable render writes to complete in C2/C3/C4 power states. 603 * If this isn't enabled, render writes are prevented in low 604 * power states. That seems bad to me. 605 */ 606 #define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11) 607 608 /* This acknowledges an async flip immediately instead 609 * of waiting for 2TLB fetches. 610 */ 611 #define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10) 612 613 /* Enables non-sequential data reads through arbiter 614 */ 615 #define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9) 616 617 /* Disable FSB snooping of cacheable write cycles from binner/render 618 * command stream 619 */ 620 #define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8) 621 622 /* Arbiter time slice for non-isoch streams */ 623 #define MI_ARB_TIME_SLICE_MASK (7 << 5) 624 #define MI_ARB_TIME_SLICE_1 (0 << 5) 625 #define MI_ARB_TIME_SLICE_2 (1 << 5) 626 #define MI_ARB_TIME_SLICE_4 (2 << 5) 627 #define MI_ARB_TIME_SLICE_6 (3 << 5) 628 #define MI_ARB_TIME_SLICE_8 (4 << 5) 629 #define MI_ARB_TIME_SLICE_10 (5 << 5) 630 #define MI_ARB_TIME_SLICE_14 (6 << 5) 631 #define MI_ARB_TIME_SLICE_16 (7 << 5) 632 633 /* Low priority grace period page size */ 634 #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */ 635 #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4) 636 637 /* Disable display A/B trickle feed */ 638 #define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) 639 640 /* Set display plane priority */ 641 #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */ 642 #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */ 643 644 #define CACHE_MODE_0 0x02120 /* 915+ only */ 645 #define CM0_IZ_OPT_DISABLE (1<<6) 646 #define CM0_ZR_OPT_DISABLE (1<<5) 647 #define CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5) 648 #define CM0_DEPTH_EVICT_DISABLE (1<<4) 649 #define CM0_COLOR_EVICT_DISABLE (1<<3) 650 #define CM0_DEPTH_WRITE_DISABLE (1<<1) 651 #define CM0_RC_OP_FLUSH_DISABLE (1<<0) 652 #define BB_ADDR 0x02140 /* 8 bytes */ 653 #define GFX_FLSH_CNTL 0x02170 /* 915+ only */ 654 #define ECOSKPD 0x021d0 655 #define ECO_GATING_CX_ONLY (1<<3) 656 #define ECO_FLIP_DONE (1<<0) 657 658 #define CACHE_MODE_1 0x7004 /* IVB+ */ 659 #define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6) 660 661 /* GEN6 interrupt control 662 * Note that the per-ring interrupt bits do alias with the global interrupt bits 663 * in GTIMR. */ 664 #define GEN6_RENDER_HWSTAM 0x2098 665 #define GEN6_RENDER_IMR 0x20a8 666 #define GEN6_RENDER_CONTEXT_SWITCH_INTERRUPT (1 << 8) 667 #define GEN6_RENDER_PPGTT_PAGE_FAULT (1 << 7) 668 #define GEN6_RENDER_TIMEOUT_COUNTER_EXPIRED (1 << 6) 669 #define GEN6_RENDER_L3_PARITY_ERROR (1 << 5) 670 #define GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 4) 671 #define GEN6_RENDER_COMMAND_PARSER_MASTER_ERROR (1 << 3) 672 #define GEN6_RENDER_SYNC_STATUS (1 << 2) 673 #define GEN6_RENDER_DEBUG_INTERRUPT (1 << 1) 674 #define GEN6_RENDER_USER_INTERRUPT (1 << 0) 675 676 #define GEN6_BLITTER_HWSTAM 0x22098 677 #define GEN6_BLITTER_IMR 0x220a8 678 #define GEN6_BLITTER_MI_FLUSH_DW_NOTIFY_INTERRUPT (1 << 26) 679 #define GEN6_BLITTER_COMMAND_PARSER_MASTER_ERROR (1 << 25) 680 #define GEN6_BLITTER_SYNC_STATUS (1 << 24) 681 #define GEN6_BLITTER_USER_INTERRUPT (1 << 22) 682 683 #define GEN6_BLITTER_ECOSKPD 0x221d0 684 #define GEN6_BLITTER_LOCK_SHIFT 16 685 #define GEN6_BLITTER_FBC_NOTIFY (1<<3) 686 687 #define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050 688 #define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK (1 << 16) 689 #define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE (1 << 0) 690 #define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE 0 691 #define GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR (1 << 3) 692 693 #define GEN6_BSD_HWSTAM 0x12098 694 #define GEN6_BSD_IMR 0x120a8 695 #define GEN6_BSD_USER_INTERRUPT (1 << 12) 696 697 #define GEN6_BSD_RNCID 0x12198 698 699 #define GEN7_FF_THREAD_MODE 0x20a0 700 #define GEN7_FF_SCHED_MASK 0x0077070 701 #define GEN7_FF_TS_SCHED_HS1 (0x5<<16) 702 #define GEN7_FF_TS_SCHED_HS0 (0x3<<16) 703 #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1<<16) 704 #define GEN7_FF_TS_SCHED_HW (0x0<<16) /* Default */ 705 #define GEN7_FF_VS_SCHED_HS1 (0x5<<12) 706 #define GEN7_FF_VS_SCHED_HS0 (0x3<<12) 707 #define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1<<12) /* Default */ 708 #define GEN7_FF_VS_SCHED_HW (0x0<<12) 709 #define GEN7_FF_DS_SCHED_HS1 (0x5<<4) 710 #define GEN7_FF_DS_SCHED_HS0 (0x3<<4) 711 #define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1<<4) /* Default */ 712 #define GEN7_FF_DS_SCHED_HW (0x0<<4) 713 714 /* 715 * Framebuffer compression (915+ only) 716 */ 717 718 #define FBC_CFB_BASE 0x03200 /* 4k page aligned */ 719 #define FBC_LL_BASE 0x03204 /* 4k page aligned */ 720 #define FBC_CONTROL 0x03208 721 #define FBC_CTL_EN (1<<31) 722 #define FBC_CTL_PERIODIC (1<<30) 723 #define FBC_CTL_INTERVAL_SHIFT (16) 724 #define FBC_CTL_UNCOMPRESSIBLE (1<<14) 725 #define FBC_CTL_C3_IDLE (1<<13) 726 #define FBC_CTL_STRIDE_SHIFT (5) 727 #define FBC_CTL_FENCENO (1<<0) 728 #define FBC_COMMAND 0x0320c 729 #define FBC_CMD_COMPRESS (1<<0) 730 #define FBC_STATUS 0x03210 731 #define FBC_STAT_COMPRESSING (1<<31) 732 #define FBC_STAT_COMPRESSED (1<<30) 733 #define FBC_STAT_MODIFIED (1<<29) 734 #define FBC_STAT_CURRENT_LINE (1<<0) 735 #define FBC_CONTROL2 0x03214 736 #define FBC_CTL_FENCE_DBL (0<<4) 737 #define FBC_CTL_IDLE_IMM (0<<2) 738 #define FBC_CTL_IDLE_FULL (1<<2) 739 #define FBC_CTL_IDLE_LINE (2<<2) 740 #define FBC_CTL_IDLE_DEBUG (3<<2) 741 #define FBC_CTL_CPU_FENCE (1<<1) 742 #define FBC_CTL_PLANEA (0<<0) 743 #define FBC_CTL_PLANEB (1<<0) 744 #define FBC_FENCE_OFF 0x0321b 745 #define FBC_TAG 0x03300 746 747 #define FBC_LL_SIZE (1536) 748 749 /* Framebuffer compression for GM45+ */ 750 #define DPFC_CB_BASE 0x3200 751 #define DPFC_CONTROL 0x3208 752 #define DPFC_CTL_EN (1<<31) 753 #define DPFC_CTL_PLANEA (0<<30) 754 #define DPFC_CTL_PLANEB (1<<30) 755 #define DPFC_CTL_FENCE_EN (1<<29) 756 #define DPFC_CTL_PERSISTENT_MODE (1<<25) 757 #define DPFC_SR_EN (1<<10) 758 #define DPFC_CTL_LIMIT_1X (0<<6) 759 #define DPFC_CTL_LIMIT_2X (1<<6) 760 #define DPFC_CTL_LIMIT_4X (2<<6) 761 #define DPFC_RECOMP_CTL 0x320c 762 #define DPFC_RECOMP_STALL_EN (1<<27) 763 #define DPFC_RECOMP_STALL_WM_SHIFT (16) 764 #define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000) 765 #define DPFC_RECOMP_TIMER_COUNT_SHIFT (0) 766 #define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f) 767 #define DPFC_STATUS 0x3210 768 #define DPFC_INVAL_SEG_SHIFT (16) 769 #define DPFC_INVAL_SEG_MASK (0x07ff0000) 770 #define DPFC_COMP_SEG_SHIFT (0) 771 #define DPFC_COMP_SEG_MASK (0x000003ff) 772 #define DPFC_STATUS2 0x3214 773 #define DPFC_FENCE_YOFF 0x3218 774 #define DPFC_CHICKEN 0x3224 775 #define DPFC_HT_MODIFY (1<<31) 776 777 /* Framebuffer compression for Ironlake */ 778 #define ILK_DPFC_CB_BASE 0x43200 779 #define ILK_DPFC_CONTROL 0x43208 780 /* The bit 28-8 is reserved */ 781 #define DPFC_RESERVED (0x1FFFFF00) 782 #define ILK_DPFC_RECOMP_CTL 0x4320c 783 #define ILK_DPFC_STATUS 0x43210 784 #define ILK_DPFC_FENCE_YOFF 0x43218 785 #define ILK_DPFC_CHICKEN 0x43224 786 #define ILK_FBC_RT_BASE 0x2128 787 #define ILK_FBC_RT_VALID (1<<0) 788 789 #define ILK_DISPLAY_CHICKEN1 0x42000 790 #define ILK_FBCQ_DIS (1<<22) 791 #define ILK_PABSTRETCH_DIS (1<<21) 792 793 794 /* 795 * Framebuffer compression for Sandybridge 796 * 797 * The following two registers are of type GTTMMADR 798 */ 799 #define SNB_DPFC_CTL_SA 0x100100 800 #define SNB_CPU_FENCE_ENABLE (1<<29) 801 #define DPFC_CPU_FENCE_OFFSET 0x100104 802 803 804 /* 805 * GPIO regs 806 */ 807 #define GPIOA 0x5010 808 #define GPIOB 0x5014 809 #define GPIOC 0x5018 810 #define GPIOD 0x501c 811 #define GPIOE 0x5020 812 #define GPIOF 0x5024 813 #define GPIOG 0x5028 814 #define GPIOH 0x502c 815 # define GPIO_CLOCK_DIR_MASK (1 << 0) 816 # define GPIO_CLOCK_DIR_IN (0 << 1) 817 # define GPIO_CLOCK_DIR_OUT (1 << 1) 818 # define GPIO_CLOCK_VAL_MASK (1 << 2) 819 # define GPIO_CLOCK_VAL_OUT (1 << 3) 820 # define GPIO_CLOCK_VAL_IN (1 << 4) 821 # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5) 822 # define GPIO_DATA_DIR_MASK (1 << 8) 823 # define GPIO_DATA_DIR_IN (0 << 9) 824 # define GPIO_DATA_DIR_OUT (1 << 9) 825 # define GPIO_DATA_VAL_MASK (1 << 10) 826 # define GPIO_DATA_VAL_OUT (1 << 11) 827 # define GPIO_DATA_VAL_IN (1 << 12) 828 # define GPIO_DATA_PULLUP_DISABLE (1 << 13) 829 830 #define GMBUS0 0x5100 /* clock/port select */ 831 #define GMBUS_RATE_100KHZ (0<<8) 832 #define GMBUS_RATE_50KHZ (1<<8) 833 #define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */ 834 #define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */ 835 #define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */ 836 #define GMBUS_PORT_DISABLED 0 837 #define GMBUS_PORT_SSC 1 838 #define GMBUS_PORT_VGADDC 2 839 #define GMBUS_PORT_PANEL 3 840 #define GMBUS_PORT_DPC 4 /* HDMIC */ 841 #define GMBUS_PORT_DPB 5 /* SDVO, HDMIB */ 842 #define GMBUS_PORT_DPD 6 /* HDMID */ 843 #define GMBUS_PORT_RESERVED 7 /* 7 reserved */ 844 #define GMBUS_NUM_PORTS (GMBUS_PORT_DPD - GMBUS_PORT_SSC + 1) 845 #define GMBUS1 0x5104 /* command/status */ 846 #define GMBUS_SW_CLR_INT (1<<31) 847 #define GMBUS_SW_RDY (1<<30) 848 #define GMBUS_ENT (1<<29) /* enable timeout */ 849 #define GMBUS_CYCLE_NONE (0<<25) 850 #define GMBUS_CYCLE_WAIT (1<<25) 851 #define GMBUS_CYCLE_INDEX (2<<25) 852 #define GMBUS_CYCLE_STOP (4<<25) 853 #define GMBUS_BYTE_COUNT_SHIFT 16 854 #define GMBUS_SLAVE_INDEX_SHIFT 8 855 #define GMBUS_SLAVE_ADDR_SHIFT 1 856 #define GMBUS_SLAVE_READ (1<<0) 857 #define GMBUS_SLAVE_WRITE (0<<0) 858 #define GMBUS2 0x5108 /* status */ 859 #define GMBUS_INUSE (1<<15) 860 #define GMBUS_HW_WAIT_PHASE (1<<14) 861 #define GMBUS_STALL_TIMEOUT (1<<13) 862 #define GMBUS_INT (1<<12) 863 #define GMBUS_HW_RDY (1<<11) 864 #define GMBUS_SATOER (1<<10) 865 #define GMBUS_ACTIVE (1<<9) 866 #define GMBUS3 0x510c /* data buffer bytes 3-0 */ 867 #define GMBUS4 0x5110 /* interrupt mask (Pineview+) */ 868 #define GMBUS_SLAVE_TIMEOUT_EN (1<<4) 869 #define GMBUS_NAK_EN (1<<3) 870 #define GMBUS_IDLE_EN (1<<2) 871 #define GMBUS_HW_WAIT_EN (1<<1) 872 #define GMBUS_HW_RDY_EN (1<<0) 873 #define GMBUS5 0x5120 /* byte index */ 874 #define GMBUS_2BYTE_INDEX_EN (1<<31) 875 876 /* 877 * Clock control & power management 878 */ 879 880 #define VGA0 0x6000 881 #define VGA1 0x6004 882 #define VGA_PD 0x6010 883 #define VGA0_PD_P2_DIV_4 (1 << 7) 884 #define VGA0_PD_P1_DIV_2 (1 << 5) 885 #define VGA0_PD_P1_SHIFT 0 886 #define VGA0_PD_P1_MASK (0x1f << 0) 887 #define VGA1_PD_P2_DIV_4 (1 << 15) 888 #define VGA1_PD_P1_DIV_2 (1 << 13) 889 #define VGA1_PD_P1_SHIFT 8 890 #define VGA1_PD_P1_MASK (0x1f << 8) 891 #define _DPLL_A 0x06014 892 #define _DPLL_B 0x06018 893 #define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B) 894 #define DPLL_VCO_ENABLE (1U << 31) 895 #define DPLL_DVO_HIGH_SPEED (1 << 30) 896 #define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30) 897 #define DPLL_SYNCLOCK_ENABLE (1 << 29) 898 #define DPLL_REFA_CLK_ENABLE_VLV (1 << 29) 899 #define DPLL_VGA_MODE_DIS (1 << 28) 900 #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ 901 #define DPLLB_MODE_LVDS (2 << 26) /* i915 */ 902 #define DPLL_MODE_MASK (3 << 26) 903 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ 904 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ 905 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ 906 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ 907 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ 908 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ 909 #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */ 910 #define DPLL_INTEGRATED_CLOCK_VLV (1<<13) 911 912 #define SRX_INDEX 0x3c4 913 #define SRX_DATA 0x3c5 914 #define SR01 1 915 #define SR01_SCREEN_OFF (1<<5) 916 917 #define PPCR 0x61204 918 #define PPCR_ON (1<<0) 919 920 #define DVOB 0x61140 921 #define DVOB_ON (1<<31) 922 #define DVOC 0x61160 923 #define DVOC_ON (1<<31) 924 #define LVDS 0x61180 925 #define LVDS_ON (1<<31) 926 927 /* Scratch pad debug 0 reg: 928 */ 929 #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 930 /* 931 * The i830 generation, in LVDS mode, defines P1 as the bit number set within 932 * this field (only one bit may be set). 933 */ 934 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 935 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16 936 #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15 937 /* i830, required in DVO non-gang */ 938 #define PLL_P2_DIVIDE_BY_4 (1 << 23) 939 #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ 940 #define PLL_REF_INPUT_DREFCLK (0 << 13) 941 #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ 942 #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ 943 #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) 944 #define PLL_REF_INPUT_MASK (3 << 13) 945 #define PLL_LOAD_PULSE_PHASE_SHIFT 9 946 /* Ironlake */ 947 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9 948 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9) 949 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9) 950 # define DPLL_FPA1_P1_POST_DIV_SHIFT 0 951 # define DPLL_FPA1_P1_POST_DIV_MASK 0xff 952 953 /* 954 * Parallel to Serial Load Pulse phase selection. 955 * Selects the phase for the 10X DPLL clock for the PCIe 956 * digital display port. The range is 4 to 13; 10 or more 957 * is just a flip delay. The default is 6 958 */ 959 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) 960 #define DISPLAY_RATE_SELECT_FPA1 (1 << 8) 961 /* 962 * SDVO multiplier for 945G/GM. Not used on 965. 963 */ 964 #define SDVO_MULTIPLIER_MASK 0x000000ff 965 #define SDVO_MULTIPLIER_SHIFT_HIRES 4 966 #define SDVO_MULTIPLIER_SHIFT_VGA 0 967 #define _DPLL_A_MD 0x0601c /* 965+ only */ 968 /* 969 * UDI pixel divider, controlling how many pixels are stuffed into a packet. 970 * 971 * Value is pixels minus 1. Must be set to 1 pixel for SDVO. 972 */ 973 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 974 #define DPLL_MD_UDI_DIVIDER_SHIFT 24 975 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ 976 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 977 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 978 /* 979 * SDVO/UDI pixel multiplier. 980 * 981 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus 982 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate 983 * modes, the bus rate would be below the limits, so SDVO allows for stuffing 984 * dummy bytes in the datastream at an increased clock rate, with both sides of 985 * the link knowing how many bytes are fill. 986 * 987 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock 988 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be 989 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and 990 * through an SDVO command. 991 * 992 * This register field has values of multiplication factor minus 1, with 993 * a maximum multiplier of 5 for SDVO. 994 */ 995 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 996 #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 997 /* 998 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. 999 * This best be set to the default value (3) or the CRT won't work. No, 1000 * I don't entirely understand what this does... 1001 */ 1002 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f 1003 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 1004 #define _DPLL_B_MD 0x06020 /* 965+ only */ 1005 #define DPLL_MD(pipe) _PIPE(pipe, _DPLL_A_MD, _DPLL_B_MD) 1006 1007 #define _FPA0 0x06040 1008 #define _FPA1 0x06044 1009 #define _FPB0 0x06048 1010 #define _FPB1 0x0604c 1011 #define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0) 1012 #define FP1(pipe) _PIPE(pipe, _FPA1, _FPB1) 1013 #define FP_N_DIV_MASK 0x003f0000 1014 #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000 1015 #define FP_N_DIV_SHIFT 16 1016 #define FP_M1_DIV_MASK 0x00003f00 1017 #define FP_M1_DIV_SHIFT 8 1018 #define FP_M2_DIV_MASK 0x0000003f 1019 #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff 1020 #define FP_M2_DIV_SHIFT 0 1021 #define DPLL_TEST 0x606c 1022 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22) 1023 #define DPLLB_TEST_SDVO_DIV_2 (1 << 22) 1024 #define DPLLB_TEST_SDVO_DIV_4 (2 << 22) 1025 #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) 1026 #define DPLLB_TEST_N_BYPASS (1 << 19) 1027 #define DPLLB_TEST_M_BYPASS (1 << 18) 1028 #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) 1029 #define DPLLA_TEST_N_BYPASS (1 << 3) 1030 #define DPLLA_TEST_M_BYPASS (1 << 2) 1031 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) 1032 #define D_STATE 0x6104 1033 #define DSTATE_GFX_RESET_I830 (1<<6) 1034 #define DSTATE_PLL_D3_OFF (1<<3) 1035 #define DSTATE_GFX_CLOCK_GATING (1<<1) 1036 #define DSTATE_DOT_CLOCK_GATING (1<<0) 1037 #define DSPCLK_GATE_D 0x6200 1038 # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */ 1039 # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */ 1040 # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */ 1041 # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */ 1042 # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */ 1043 # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */ 1044 # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */ 1045 # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */ 1046 # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */ 1047 # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */ 1048 # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */ 1049 # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */ 1050 # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */ 1051 # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */ 1052 # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */ 1053 # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */ 1054 # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */ 1055 # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */ 1056 # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */ 1057 # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11) 1058 # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10) 1059 # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9) 1060 # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8) 1061 # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */ 1062 # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */ 1063 # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */ 1064 # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5) 1065 # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4) 1066 /** 1067 * This bit must be set on the 830 to prevent hangs when turning off the 1068 * overlay scaler. 1069 */ 1070 # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3) 1071 # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2) 1072 # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1) 1073 # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */ 1074 # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */ 1075 1076 #define RENCLK_GATE_D1 0x6204 1077 # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */ 1078 # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */ 1079 # define PC_FE_CLOCK_GATE_DISABLE (1 << 11) 1080 # define PC_BE_CLOCK_GATE_DISABLE (1 << 10) 1081 # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9) 1082 # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8) 1083 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7) 1084 # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6) 1085 # define MAG_CLOCK_GATE_DISABLE (1 << 5) 1086 /** This bit must be unset on 855,865 */ 1087 # define MECI_CLOCK_GATE_DISABLE (1 << 4) 1088 # define DCMP_CLOCK_GATE_DISABLE (1 << 3) 1089 # define MEC_CLOCK_GATE_DISABLE (1 << 2) 1090 # define MECO_CLOCK_GATE_DISABLE (1 << 1) 1091 /** This bit must be set on 855,865. */ 1092 # define SV_CLOCK_GATE_DISABLE (1 << 0) 1093 # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16) 1094 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15) 1095 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14) 1096 # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13) 1097 # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12) 1098 # define I915_WM_CLOCK_GATE_DISABLE (1 << 11) 1099 # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10) 1100 # define I915_PI_CLOCK_GATE_DISABLE (1 << 9) 1101 # define I915_DI_CLOCK_GATE_DISABLE (1 << 8) 1102 # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7) 1103 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6) 1104 # define I915_SC_CLOCK_GATE_DISABLE (1 << 5) 1105 # define I915_FL_CLOCK_GATE_DISABLE (1 << 4) 1106 # define I915_DM_CLOCK_GATE_DISABLE (1 << 3) 1107 # define I915_PS_CLOCK_GATE_DISABLE (1 << 2) 1108 # define I915_CC_CLOCK_GATE_DISABLE (1 << 1) 1109 # define I915_BY_CLOCK_GATE_DISABLE (1 << 0) 1110 1111 # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30) 1112 /** This bit must always be set on 965G/965GM */ 1113 # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29) 1114 # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28) 1115 # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27) 1116 # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26) 1117 # define I965_GW_CLOCK_GATE_DISABLE (1 << 25) 1118 # define I965_TD_CLOCK_GATE_DISABLE (1 << 24) 1119 /** This bit must always be set on 965G */ 1120 # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23) 1121 # define I965_IC_CLOCK_GATE_DISABLE (1 << 22) 1122 # define I965_EU_CLOCK_GATE_DISABLE (1 << 21) 1123 # define I965_IF_CLOCK_GATE_DISABLE (1 << 20) 1124 # define I965_TC_CLOCK_GATE_DISABLE (1 << 19) 1125 # define I965_SO_CLOCK_GATE_DISABLE (1 << 17) 1126 # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16) 1127 # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15) 1128 # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14) 1129 # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13) 1130 # define I965_EM_CLOCK_GATE_DISABLE (1 << 12) 1131 # define I965_UC_CLOCK_GATE_DISABLE (1 << 11) 1132 # define I965_SI_CLOCK_GATE_DISABLE (1 << 6) 1133 # define I965_MT_CLOCK_GATE_DISABLE (1 << 5) 1134 # define I965_PL_CLOCK_GATE_DISABLE (1 << 4) 1135 # define I965_DG_CLOCK_GATE_DISABLE (1 << 3) 1136 # define I965_QC_CLOCK_GATE_DISABLE (1 << 2) 1137 # define I965_FT_CLOCK_GATE_DISABLE (1 << 1) 1138 # define I965_DM_CLOCK_GATE_DISABLE (1 << 0) 1139 1140 #define RENCLK_GATE_D2 0x6208 1141 #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9) 1142 #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7) 1143 #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6) 1144 #define RAMCLK_GATE_D 0x6210 /* CRL only */ 1145 #define DEUC 0x6214 /* CRL only */ 1146 1147 #define FW_BLC_SELF_VLV 0x6500 1148 #define FW_CSPWRDWNEN (1<<15) 1149 1150 /* 1151 * Palette regs 1152 */ 1153 1154 #define _PALETTE_A 0x0a000 1155 #define _PALETTE_B 0x0a800 1156 #define PALETTE(pipe) _PIPE(pipe, _PALETTE_A, _PALETTE_B) 1157 1158 /* MCH MMIO space */ 1159 1160 /* 1161 * MCHBAR mirror. 1162 * 1163 * This mirrors the MCHBAR MMIO space whose location is determined by 1164 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in 1165 * every way. It is not accessible from the CP register read instructions. 1166 * 1167 */ 1168 #define MCHBAR_MIRROR_BASE 0x10000 1169 1170 #define MCHBAR_MIRROR_BASE_SNB 0x140000 1171 1172 /** 915-945 and GM965 MCH register controlling DRAM channel access */ 1173 #define DCC 0x10200 1174 #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0) 1175 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0) 1176 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0) 1177 #define DCC_ADDRESSING_MODE_MASK (3 << 0) 1178 #define DCC_CHANNEL_XOR_DISABLE (1 << 10) 1179 #define DCC_CHANNEL_XOR_BIT_17 (1 << 9) 1180 1181 /** Pineview MCH register contains DDR3 setting */ 1182 #define CSHRDDR3CTL 0x101a8 1183 #define CSHRDDR3CTL_DDR3 (1 << 2) 1184 1185 /** 965 MCH register controlling DRAM channel configuration */ 1186 #define C0DRB3 0x10206 1187 #define C1DRB3 0x10606 1188 1189 /** snb MCH registers for reading the DRAM channel configuration */ 1190 #define MAD_DIMM_C0 (MCHBAR_MIRROR_BASE_SNB + 0x5004) 1191 #define MAD_DIMM_C1 (MCHBAR_MIRROR_BASE_SNB + 0x5008) 1192 #define MAD_DIMM_C2 (MCHBAR_MIRROR_BASE_SNB + 0x500C) 1193 #define MAD_DIMM_ECC_MASK (0x3 << 24) 1194 #define MAD_DIMM_ECC_OFF (0x0 << 24) 1195 #define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24) 1196 #define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24) 1197 #define MAD_DIMM_ECC_ON (0x3 << 24) 1198 #define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22) 1199 #define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21) 1200 #define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */ 1201 #define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */ 1202 #define MAD_DIMM_B_DUAL_RANK (0x1 << 18) 1203 #define MAD_DIMM_A_DUAL_RANK (0x1 << 17) 1204 #define MAD_DIMM_A_SELECT (0x1 << 16) 1205 /* DIMM sizes are in multiples of 256mb. */ 1206 #define MAD_DIMM_B_SIZE_SHIFT 8 1207 #define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT) 1208 #define MAD_DIMM_A_SIZE_SHIFT 0 1209 #define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT) 1210 1211 1212 /* Clocking configuration register */ 1213 #define CLKCFG 0x10c00 1214 #define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */ 1215 #define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */ 1216 #define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */ 1217 #define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */ 1218 #define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */ 1219 #define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */ 1220 /* Note, below two are guess */ 1221 #define CLKCFG_FSB_1600 (4 << 0) /* hrawclk 400 */ 1222 #define CLKCFG_FSB_1600_ALT (0 << 0) /* hrawclk 400 */ 1223 #define CLKCFG_FSB_MASK (7 << 0) 1224 #define CLKCFG_MEM_533 (1 << 4) 1225 #define CLKCFG_MEM_667 (2 << 4) 1226 #define CLKCFG_MEM_800 (3 << 4) 1227 #define CLKCFG_MEM_MASK (7 << 4) 1228 1229 #define TSC1 0x11001 1230 #define TSE (1<<0) 1231 #define I915_TR1 0x11006 1232 #define TSFS 0x11020 1233 #define TSFS_SLOPE_MASK 0x0000ff00 1234 #define TSFS_SLOPE_SHIFT 8 1235 #define TSFS_INTR_MASK 0x000000ff 1236 1237 #define CRSTANDVID 0x11100 1238 #define PXVFREQ_BASE 0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */ 1239 #define PXVFREQ_PX_MASK 0x7f000000 1240 #define PXVFREQ_PX_SHIFT 24 1241 #define VIDFREQ_BASE 0x11110 1242 #define VIDFREQ1 0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */ 1243 #define VIDFREQ2 0x11114 1244 #define VIDFREQ3 0x11118 1245 #define VIDFREQ4 0x1111c 1246 #define VIDFREQ_P0_MASK 0x1f000000 1247 #define VIDFREQ_P0_SHIFT 24 1248 #define VIDFREQ_P0_CSCLK_MASK 0x00f00000 1249 #define VIDFREQ_P0_CSCLK_SHIFT 20 1250 #define VIDFREQ_P0_CRCLK_MASK 0x000f0000 1251 #define VIDFREQ_P0_CRCLK_SHIFT 16 1252 #define VIDFREQ_P1_MASK 0x00001f00 1253 #define VIDFREQ_P1_SHIFT 8 1254 #define VIDFREQ_P1_CSCLK_MASK 0x000000f0 1255 #define VIDFREQ_P1_CSCLK_SHIFT 4 1256 #define VIDFREQ_P1_CRCLK_MASK 0x0000000f 1257 #define INTTOEXT_BASE_ILK 0x11300 1258 #define INTTOEXT_BASE 0x11120 /* INTTOEXT1-8 (0x1113c) */ 1259 #define INTTOEXT_MAP3_SHIFT 24 1260 #define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT) 1261 #define INTTOEXT_MAP2_SHIFT 16 1262 #define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT) 1263 #define INTTOEXT_MAP1_SHIFT 8 1264 #define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT) 1265 #define INTTOEXT_MAP0_SHIFT 0 1266 #define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT) 1267 #define MEMSWCTL 0x11170 /* Ironlake only */ 1268 #define MEMCTL_CMD_MASK 0xe000 1269 #define MEMCTL_CMD_SHIFT 13 1270 #define MEMCTL_CMD_RCLK_OFF 0 1271 #define MEMCTL_CMD_RCLK_ON 1 1272 #define MEMCTL_CMD_CHFREQ 2 1273 #define MEMCTL_CMD_CHVID 3 1274 #define MEMCTL_CMD_VMMOFF 4 1275 #define MEMCTL_CMD_VMMON 5 1276 #define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears 1277 when command complete */ 1278 #define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */ 1279 #define MEMCTL_FREQ_SHIFT 8 1280 #define MEMCTL_SFCAVM (1<<7) 1281 #define MEMCTL_TGT_VID_MASK 0x007f 1282 #define MEMIHYST 0x1117c 1283 #define MEMINTREN 0x11180 /* 16 bits */ 1284 #define MEMINT_RSEXIT_EN (1<<8) 1285 #define MEMINT_CX_SUPR_EN (1<<7) 1286 #define MEMINT_CONT_BUSY_EN (1<<6) 1287 #define MEMINT_AVG_BUSY_EN (1<<5) 1288 #define MEMINT_EVAL_CHG_EN (1<<4) 1289 #define MEMINT_MON_IDLE_EN (1<<3) 1290 #define MEMINT_UP_EVAL_EN (1<<2) 1291 #define MEMINT_DOWN_EVAL_EN (1<<1) 1292 #define MEMINT_SW_CMD_EN (1<<0) 1293 #define MEMINTRSTR 0x11182 /* 16 bits */ 1294 #define MEM_RSEXIT_MASK 0xc000 1295 #define MEM_RSEXIT_SHIFT 14 1296 #define MEM_CONT_BUSY_MASK 0x3000 1297 #define MEM_CONT_BUSY_SHIFT 12 1298 #define MEM_AVG_BUSY_MASK 0x0c00 1299 #define MEM_AVG_BUSY_SHIFT 10 1300 #define MEM_EVAL_CHG_MASK 0x0300 1301 #define MEM_EVAL_BUSY_SHIFT 8 1302 #define MEM_MON_IDLE_MASK 0x00c0 1303 #define MEM_MON_IDLE_SHIFT 6 1304 #define MEM_UP_EVAL_MASK 0x0030 1305 #define MEM_UP_EVAL_SHIFT 4 1306 #define MEM_DOWN_EVAL_MASK 0x000c 1307 #define MEM_DOWN_EVAL_SHIFT 2 1308 #define MEM_SW_CMD_MASK 0x0003 1309 #define MEM_INT_STEER_GFX 0 1310 #define MEM_INT_STEER_CMR 1 1311 #define MEM_INT_STEER_SMI 2 1312 #define MEM_INT_STEER_SCI 3 1313 #define MEMINTRSTS 0x11184 1314 #define MEMINT_RSEXIT (1<<7) 1315 #define MEMINT_CONT_BUSY (1<<6) 1316 #define MEMINT_AVG_BUSY (1<<5) 1317 #define MEMINT_EVAL_CHG (1<<4) 1318 #define MEMINT_MON_IDLE (1<<3) 1319 #define MEMINT_UP_EVAL (1<<2) 1320 #define MEMINT_DOWN_EVAL (1<<1) 1321 #define MEMINT_SW_CMD (1<<0) 1322 #define MEMMODECTL 0x11190 1323 #define MEMMODE_BOOST_EN (1<<31) 1324 #define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */ 1325 #define MEMMODE_BOOST_FREQ_SHIFT 24 1326 #define MEMMODE_IDLE_MODE_MASK 0x00030000 1327 #define MEMMODE_IDLE_MODE_SHIFT 16 1328 #define MEMMODE_IDLE_MODE_EVAL 0 1329 #define MEMMODE_IDLE_MODE_CONT 1 1330 #define MEMMODE_HWIDLE_EN (1<<15) 1331 #define MEMMODE_SWMODE_EN (1<<14) 1332 #define MEMMODE_RCLK_GATE (1<<13) 1333 #define MEMMODE_HW_UPDATE (1<<12) 1334 #define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */ 1335 #define MEMMODE_FSTART_SHIFT 8 1336 #define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */ 1337 #define MEMMODE_FMAX_SHIFT 4 1338 #define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */ 1339 #define RCBMAXAVG 0x1119c 1340 #define MEMSWCTL2 0x1119e /* Cantiga only */ 1341 #define SWMEMCMD_RENDER_OFF (0 << 13) 1342 #define SWMEMCMD_RENDER_ON (1 << 13) 1343 #define SWMEMCMD_SWFREQ (2 << 13) 1344 #define SWMEMCMD_TARVID (3 << 13) 1345 #define SWMEMCMD_VRM_OFF (4 << 13) 1346 #define SWMEMCMD_VRM_ON (5 << 13) 1347 #define CMDSTS (1<<12) 1348 #define SFCAVM (1<<11) 1349 #define SWFREQ_MASK 0x0380 /* P0-7 */ 1350 #define SWFREQ_SHIFT 7 1351 #define TARVID_MASK 0x001f 1352 #define MEMSTAT_CTG 0x111a0 1353 #define RCBMINAVG 0x111a0 1354 #define RCUPEI 0x111b0 1355 #define RCDNEI 0x111b4 1356 #define RSTDBYCTL 0x111b8 1357 #define RS1EN (1<<31) 1358 #define RS2EN (1<<30) 1359 #define RS3EN (1<<29) 1360 #define D3RS3EN (1<<28) /* Display D3 imlies RS3 */ 1361 #define SWPROMORSX (1<<27) /* RSx promotion timers ignored */ 1362 #define RCWAKERW (1<<26) /* Resetwarn from PCH causes wakeup */ 1363 #define DPRSLPVREN (1<<25) /* Fast voltage ramp enable */ 1364 #define GFXTGHYST (1<<24) /* Hysteresis to allow trunk gating */ 1365 #define RCX_SW_EXIT (1<<23) /* Leave RSx and prevent re-entry */ 1366 #define RSX_STATUS_MASK (7<<20) 1367 #define RSX_STATUS_ON (0<<20) 1368 #define RSX_STATUS_RC1 (1<<20) 1369 #define RSX_STATUS_RC1E (2<<20) 1370 #define RSX_STATUS_RS1 (3<<20) 1371 #define RSX_STATUS_RS2 (4<<20) /* aka rc6 */ 1372 #define RSX_STATUS_RSVD (5<<20) /* deep rc6 unsupported on ilk */ 1373 #define RSX_STATUS_RS3 (6<<20) /* rs3 unsupported on ilk */ 1374 #define RSX_STATUS_RSVD2 (7<<20) 1375 #define UWRCRSXE (1<<19) /* wake counter limit prevents rsx */ 1376 #define RSCRP (1<<18) /* rs requests control on rs1/2 reqs */ 1377 #define JRSC (1<<17) /* rsx coupled to cpu c-state */ 1378 #define RS2INC0 (1<<16) /* allow rs2 in cpu c0 */ 1379 #define RS1CONTSAV_MASK (3<<14) 1380 #define RS1CONTSAV_NO_RS1 (0<<14) /* rs1 doesn't save/restore context */ 1381 #define RS1CONTSAV_RSVD (1<<14) 1382 #define RS1CONTSAV_SAVE_RS1 (2<<14) /* rs1 saves context */ 1383 #define RS1CONTSAV_FULL_RS1 (3<<14) /* rs1 saves and restores context */ 1384 #define NORMSLEXLAT_MASK (3<<12) 1385 #define SLOW_RS123 (0<<12) 1386 #define SLOW_RS23 (1<<12) 1387 #define SLOW_RS3 (2<<12) 1388 #define NORMAL_RS123 (3<<12) 1389 #define RCMODE_TIMEOUT (1<<11) /* 0 is eval interval method */ 1390 #define IMPROMOEN (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */ 1391 #define RCENTSYNC (1<<9) /* rs coupled to cpu c-state (3/6/7) */ 1392 #define STATELOCK (1<<7) /* locked to rs_cstate if 0 */ 1393 #define RS_CSTATE_MASK (3<<4) 1394 #define RS_CSTATE_C367_RS1 (0<<4) 1395 #define RS_CSTATE_C36_RS1_C7_RS2 (1<<4) 1396 #define RS_CSTATE_RSVD (2<<4) 1397 #define RS_CSTATE_C367_RS2 (3<<4) 1398 #define REDSAVES (1<<3) /* no context save if was idle during rs0 */ 1399 #define REDRESTORES (1<<2) /* no restore if was idle during rs0 */ 1400 #define VIDCTL 0x111c0 1401 #define VIDSTS 0x111c8 1402 #define VIDSTART 0x111cc /* 8 bits */ 1403 #define MEMSTAT_ILK 0x111f8 1404 #define MEMSTAT_VID_MASK 0x7f00 1405 #define MEMSTAT_VID_SHIFT 8 1406 #define MEMSTAT_PSTATE_MASK 0x00f8 1407 #define MEMSTAT_PSTATE_SHIFT 3 1408 #define MEMSTAT_MON_ACTV (1<<2) 1409 #define MEMSTAT_SRC_CTL_MASK 0x0003 1410 #define MEMSTAT_SRC_CTL_CORE 0 1411 #define MEMSTAT_SRC_CTL_TRB 1 1412 #define MEMSTAT_SRC_CTL_THM 2 1413 #define MEMSTAT_SRC_CTL_STDBY 3 1414 #define RCPREVBSYTUPAVG 0x113b8 1415 #define RCPREVBSYTDNAVG 0x113bc 1416 #define PMMISC 0x11214 1417 #define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */ 1418 #define SDEW 0x1124c 1419 #define CSIEW0 0x11250 1420 #define CSIEW1 0x11254 1421 #define CSIEW2 0x11258 1422 #define PEW 0x1125c 1423 #define DEW 0x11270 1424 #define MCHAFE 0x112c0 1425 #define CSIEC 0x112e0 1426 #define DMIEC 0x112e4 1427 #define DDREC 0x112e8 1428 #define PEG0EC 0x112ec 1429 #define PEG1EC 0x112f0 1430 #define GFXEC 0x112f4 1431 #define RPPREVBSYTUPAVG 0x113b8 1432 #define RPPREVBSYTDNAVG 0x113bc 1433 #define ECR 0x11600 1434 #define ECR_GPFE (1<<31) 1435 #define ECR_IMONE (1<<30) 1436 #define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */ 1437 #define OGW0 0x11608 1438 #define OGW1 0x1160c 1439 #define EG0 0x11610 1440 #define EG1 0x11614 1441 #define EG2 0x11618 1442 #define EG3 0x1161c 1443 #define EG4 0x11620 1444 #define EG5 0x11624 1445 #define EG6 0x11628 1446 #define EG7 0x1162c 1447 #define PXW 0x11664 1448 #define PXWL 0x11680 1449 #define LCFUSE02 0x116c0 1450 #define LCFUSE_HIV_MASK 0x000000ff 1451 #define CSIPLL0 0x12c10 1452 #define DDRMPLL1 0X12c20 1453 #define PEG_BAND_GAP_DATA 0x14d68 1454 1455 #define GEN6_GT_PERF_STATUS 0x145948 1456 #define GEN6_RP_STATE_LIMITS 0x145994 1457 #define GEN6_RP_STATE_CAP 0x145998 1458 1459 /* 1460 * Logical Context regs 1461 */ 1462 #define CCID 0x2180 1463 #define CCID_EN (1<<0) 1464 #define CXT_SIZE 0x21a0 1465 #define GEN6_CXT_POWER_SIZE(cxt_reg) ((cxt_reg >> 24) & 0x3f) 1466 #define GEN6_CXT_RING_SIZE(cxt_reg) ((cxt_reg >> 18) & 0x3f) 1467 #define GEN6_CXT_RENDER_SIZE(cxt_reg) ((cxt_reg >> 12) & 0x3f) 1468 #define GEN6_CXT_EXTENDED_SIZE(cxt_reg) ((cxt_reg >> 6) & 0x3f) 1469 #define GEN6_CXT_PIPELINE_SIZE(cxt_reg) ((cxt_reg >> 0) & 0x3f) 1470 #define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_POWER_SIZE(cxt_reg) + \ 1471 GEN6_CXT_RING_SIZE(cxt_reg) + \ 1472 GEN6_CXT_RENDER_SIZE(cxt_reg) + \ 1473 GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \ 1474 GEN6_CXT_PIPELINE_SIZE(cxt_reg)) 1475 #define GEN7_CXT_SIZE 0x21a8 1476 #define GEN7_CXT_POWER_SIZE(ctx_reg) ((ctx_reg >> 25) & 0x7f) 1477 #define GEN7_CXT_RING_SIZE(ctx_reg) ((ctx_reg >> 22) & 0x7) 1478 #define GEN7_CXT_RENDER_SIZE(ctx_reg) ((ctx_reg >> 16) & 0x3f) 1479 #define GEN7_CXT_EXTENDED_SIZE(ctx_reg) ((ctx_reg >> 9) & 0x7f) 1480 #define GEN7_CXT_GT1_SIZE(ctx_reg) ((ctx_reg >> 6) & 0x7) 1481 #define GEN7_CXT_VFSTATE_SIZE(ctx_reg) ((ctx_reg >> 0) & 0x3f) 1482 #define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_POWER_SIZE(ctx_reg) + \ 1483 GEN7_CXT_RING_SIZE(ctx_reg) + \ 1484 GEN7_CXT_RENDER_SIZE(ctx_reg) + \ 1485 GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \ 1486 GEN7_CXT_GT1_SIZE(ctx_reg) + \ 1487 GEN7_CXT_VFSTATE_SIZE(ctx_reg)) 1488 1489 /* 1490 * Overlay regs 1491 */ 1492 1493 #define OVADD 0x30000 1494 #define DOVSTA 0x30008 1495 #define OC_BUF (0x3<<20) 1496 #define OGAMC5 0x30010 1497 #define OGAMC4 0x30014 1498 #define OGAMC3 0x30018 1499 #define OGAMC2 0x3001c 1500 #define OGAMC1 0x30020 1501 #define OGAMC0 0x30024 1502 1503 /* 1504 * Display engine regs 1505 */ 1506 1507 /* Pipe A timing regs */ 1508 #define _HTOTAL_A 0x60000 1509 #define _HBLANK_A 0x60004 1510 #define _HSYNC_A 0x60008 1511 #define _VTOTAL_A 0x6000c 1512 #define _VBLANK_A 0x60010 1513 #define _VSYNC_A 0x60014 1514 #define _PIPEASRC 0x6001c 1515 #define _BCLRPAT_A 0x60020 1516 #define _VSYNCSHIFT_A 0x60028 1517 1518 /* Pipe B timing regs */ 1519 #define _HTOTAL_B 0x61000 1520 #define _HBLANK_B 0x61004 1521 #define _HSYNC_B 0x61008 1522 #define _VTOTAL_B 0x6100c 1523 #define _VBLANK_B 0x61010 1524 #define _VSYNC_B 0x61014 1525 #define _PIPEBSRC 0x6101c 1526 #define _BCLRPAT_B 0x61020 1527 #define _VSYNCSHIFT_B 0x61028 1528 1529 1530 #define HTOTAL(pipe) _PIPE(pipe, _HTOTAL_A, _HTOTAL_B) 1531 #define HBLANK(pipe) _PIPE(pipe, _HBLANK_A, _HBLANK_B) 1532 #define HSYNC(pipe) _PIPE(pipe, _HSYNC_A, _HSYNC_B) 1533 #define VTOTAL(pipe) _PIPE(pipe, _VTOTAL_A, _VTOTAL_B) 1534 #define VBLANK(pipe) _PIPE(pipe, _VBLANK_A, _VBLANK_B) 1535 #define VSYNC(pipe) _PIPE(pipe, _VSYNC_A, _VSYNC_B) 1536 #define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B) 1537 #define VSYNCSHIFT(pipe) _PIPE(pipe, _VSYNCSHIFT_A, _VSYNCSHIFT_B) 1538 1539 /* VGA port control */ 1540 #define ADPA 0x61100 1541 #define ADPA_DAC_ENABLE (1<<31) 1542 #define ADPA_DAC_DISABLE 0 1543 #define ADPA_PIPE_SELECT_MASK (1<<30) 1544 #define ADPA_PIPE_A_SELECT 0 1545 #define ADPA_PIPE_B_SELECT (1<<30) 1546 #define ADPA_PIPE_SELECT(pipe) ((pipe) << 30) 1547 #define ADPA_USE_VGA_HVPOLARITY (1<<15) 1548 #define ADPA_SETS_HVPOLARITY 0 1549 #define ADPA_VSYNC_CNTL_DISABLE (1<<11) 1550 #define ADPA_VSYNC_CNTL_ENABLE 0 1551 #define ADPA_HSYNC_CNTL_DISABLE (1<<10) 1552 #define ADPA_HSYNC_CNTL_ENABLE 0 1553 #define ADPA_VSYNC_ACTIVE_HIGH (1<<4) 1554 #define ADPA_VSYNC_ACTIVE_LOW 0 1555 #define ADPA_HSYNC_ACTIVE_HIGH (1<<3) 1556 #define ADPA_HSYNC_ACTIVE_LOW 0 1557 #define ADPA_DPMS_MASK (~(3<<10)) 1558 #define ADPA_DPMS_ON (0<<10) 1559 #define ADPA_DPMS_SUSPEND (1<<10) 1560 #define ADPA_DPMS_STANDBY (2<<10) 1561 #define ADPA_DPMS_OFF (3<<10) 1562 1563 1564 /* Hotplug control (945+ only) */ 1565 #define PORT_HOTPLUG_EN 0x61110 1566 #define HDMIB_HOTPLUG_INT_EN (1 << 29) 1567 #define DPB_HOTPLUG_INT_EN (1 << 29) 1568 #define HDMIC_HOTPLUG_INT_EN (1 << 28) 1569 #define DPC_HOTPLUG_INT_EN (1 << 28) 1570 #define HDMID_HOTPLUG_INT_EN (1 << 27) 1571 #define DPD_HOTPLUG_INT_EN (1 << 27) 1572 #define SDVOB_HOTPLUG_INT_EN (1 << 26) 1573 #define SDVOC_HOTPLUG_INT_EN (1 << 25) 1574 #define TV_HOTPLUG_INT_EN (1 << 18) 1575 #define CRT_HOTPLUG_INT_EN (1 << 9) 1576 #define CRT_HOTPLUG_FORCE_DETECT (1 << 3) 1577 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8) 1578 /* must use period 64 on GM45 according to docs */ 1579 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8) 1580 #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7) 1581 #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7) 1582 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5) 1583 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5) 1584 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5) 1585 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5) 1586 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5) 1587 #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4) 1588 #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4) 1589 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2) 1590 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) 1591 1592 #define PORT_HOTPLUG_STAT 0x61114 1593 #define HDMIB_HOTPLUG_INT_STATUS (1 << 29) 1594 #define DPB_HOTPLUG_INT_STATUS (1 << 29) 1595 #define HDMIC_HOTPLUG_INT_STATUS (1 << 28) 1596 #define DPC_HOTPLUG_INT_STATUS (1 << 28) 1597 #define HDMID_HOTPLUG_INT_STATUS (1 << 27) 1598 #define DPD_HOTPLUG_INT_STATUS (1 << 27) 1599 #define CRT_HOTPLUG_INT_STATUS (1 << 11) 1600 #define TV_HOTPLUG_INT_STATUS (1 << 10) 1601 #define CRT_HOTPLUG_MONITOR_MASK (3 << 8) 1602 #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) 1603 #define CRT_HOTPLUG_MONITOR_MONO (2 << 8) 1604 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8) 1605 #define SDVOC_HOTPLUG_INT_STATUS (1 << 7) 1606 #define SDVOB_HOTPLUG_INT_STATUS (1 << 6) 1607 1608 /* SDVO port control */ 1609 #define SDVOB 0x61140 1610 #define SDVOC 0x61160 1611 #define SDVO_ENABLE (1U << 31) 1612 #define SDVO_PIPE_B_SELECT (1 << 30) 1613 #define SDVO_STALL_SELECT (1 << 29) 1614 #define SDVO_INTERRUPT_ENABLE (1 << 26) 1615 /** 1616 * 915G/GM SDVO pixel multiplier. 1617 * 1618 * Programmed value is multiplier - 1, up to 5x. 1619 * 1620 * \sa DPLL_MD_UDI_MULTIPLIER_MASK 1621 */ 1622 #define SDVO_PORT_MULTIPLY_MASK (7 << 23) 1623 #define SDVO_PORT_MULTIPLY_SHIFT 23 1624 #define SDVO_PHASE_SELECT_MASK (15 << 19) 1625 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19) 1626 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) 1627 #define SDVOC_GANG_MODE (1 << 16) 1628 #define SDVO_ENCODING_SDVO (0x0 << 10) 1629 #define SDVO_ENCODING_HDMI (0x2 << 10) 1630 /** Requird for HDMI operation */ 1631 #define SDVO_NULL_PACKETS_DURING_VSYNC (1 << 9) 1632 #define SDVO_COLOR_RANGE_16_235 (1 << 8) 1633 #define SDVO_BORDER_ENABLE (1 << 7) 1634 #define SDVO_AUDIO_ENABLE (1 << 6) 1635 /** New with 965, default is to be set */ 1636 #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4) 1637 /** New with 965, default is to be set */ 1638 #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3) 1639 #define SDVOB_PCIE_CONCURRENCY (1 << 3) 1640 #define SDVO_DETECTED (1 << 2) 1641 /* Bits to be preserved when writing */ 1642 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26)) 1643 #define SDVOC_PRESERVE_MASK ((1 << 17) | (1 << 26)) 1644 1645 /* DVO port control */ 1646 #define DVOA 0x61120 1647 #define DVOB 0x61140 1648 #define DVOC 0x61160 1649 #define DVO_ENABLE (1U << 31) 1650 #define DVO_PIPE_B_SELECT (1 << 30) 1651 #define DVO_PIPE_STALL_UNUSED (0 << 28) 1652 #define DVO_PIPE_STALL (1 << 28) 1653 #define DVO_PIPE_STALL_TV (2 << 28) 1654 #define DVO_PIPE_STALL_MASK (3 << 28) 1655 #define DVO_USE_VGA_SYNC (1 << 15) 1656 #define DVO_DATA_ORDER_I740 (0 << 14) 1657 #define DVO_DATA_ORDER_FP (1 << 14) 1658 #define DVO_VSYNC_DISABLE (1 << 11) 1659 #define DVO_HSYNC_DISABLE (1 << 10) 1660 #define DVO_VSYNC_TRISTATE (1 << 9) 1661 #define DVO_HSYNC_TRISTATE (1 << 8) 1662 #define DVO_BORDER_ENABLE (1 << 7) 1663 #define DVO_DATA_ORDER_GBRG (1 << 6) 1664 #define DVO_DATA_ORDER_RGGB (0 << 6) 1665 #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6) 1666 #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6) 1667 #define DVO_VSYNC_ACTIVE_HIGH (1 << 4) 1668 #define DVO_HSYNC_ACTIVE_HIGH (1 << 3) 1669 #define DVO_BLANK_ACTIVE_HIGH (1 << 2) 1670 #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */ 1671 #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */ 1672 #define DVO_PRESERVE_MASK (0x7<<24) 1673 #define DVOA_SRCDIM 0x61124 1674 #define DVOB_SRCDIM 0x61144 1675 #define DVOC_SRCDIM 0x61164 1676 #define DVO_SRCDIM_HORIZONTAL_SHIFT 12 1677 #define DVO_SRCDIM_VERTICAL_SHIFT 0 1678 1679 /* LVDS port control */ 1680 #define LVDS 0x61180 1681 /* 1682 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as 1683 * the DPLL semantics change when the LVDS is assigned to that pipe. 1684 */ 1685 #define LVDS_PORT_EN (1U << 31) 1686 /* Selects pipe B for LVDS data. Must be set on pre-965. */ 1687 #define LVDS_PIPEB_SELECT (1 << 30) 1688 #define LVDS_PIPE_MASK (1 << 30) 1689 #define LVDS_PIPE(pipe) ((pipe) << 30) 1690 /* LVDS dithering flag on 965/g4x platform */ 1691 #define LVDS_ENABLE_DITHER (1 << 25) 1692 /* LVDS sync polarity flags. Set to invert (i.e. negative) */ 1693 #define LVDS_VSYNC_POLARITY (1 << 21) 1694 #define LVDS_HSYNC_POLARITY (1 << 20) 1695 1696 /* Enable border for unscaled (or aspect-scaled) display */ 1697 #define LVDS_BORDER_ENABLE (1 << 15) 1698 /* 1699 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per 1700 * pixel. 1701 */ 1702 #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) 1703 #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) 1704 #define LVDS_A0A2_CLKA_POWER_UP (3 << 8) 1705 /* 1706 * Controls the A3 data pair, which contains the additional LSBs for 24 bit 1707 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be 1708 * on. 1709 */ 1710 #define LVDS_A3_POWER_MASK (3 << 6) 1711 #define LVDS_A3_POWER_DOWN (0 << 6) 1712 #define LVDS_A3_POWER_UP (3 << 6) 1713 /* 1714 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP 1715 * is set. 1716 */ 1717 #define LVDS_CLKB_POWER_MASK (3 << 4) 1718 #define LVDS_CLKB_POWER_DOWN (0 << 4) 1719 #define LVDS_CLKB_POWER_UP (3 << 4) 1720 /* 1721 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 1722 * setting for whether we are in dual-channel mode. The B3 pair will 1723 * additionally only be powered up when LVDS_A3_POWER_UP is set. 1724 */ 1725 #define LVDS_B0B3_POWER_MASK (3 << 2) 1726 #define LVDS_B0B3_POWER_DOWN (0 << 2) 1727 #define LVDS_B0B3_POWER_UP (3 << 2) 1728 1729 /* Video Data Island Packet control */ 1730 #define VIDEO_DIP_DATA 0x61178 1731 #define VIDEO_DIP_CTL 0x61170 1732 /* Pre HSW: */ 1733 #define VIDEO_DIP_ENABLE (1U << 31) 1734 #define VIDEO_DIP_PORT_B (1 << 29) 1735 #define VIDEO_DIP_PORT_C (2 << 29) 1736 #define VIDEO_DIP_PORT_D (3 << 29) 1737 #define VIDEO_DIP_PORT_MASK (3 << 29) 1738 #define VIDEO_DIP_ENABLE_AVI (1 << 21) 1739 #define VIDEO_DIP_ENABLE_VENDOR (2 << 21) 1740 #define VIDEO_DIP_ENABLE_SPD (8 << 21) 1741 #define VIDEO_DIP_SELECT_MASK (3 << 19) 1742 #define VIDEO_DIP_SELECT_AVI (0 << 19) 1743 #define VIDEO_DIP_SELECT_VENDOR (1 << 19) 1744 #define VIDEO_DIP_SELECT_SPD (3 << 19) 1745 #define VIDEO_DIP_FREQ_ONCE (0 << 16) 1746 #define VIDEO_DIP_FREQ_VSYNC (1 << 16) 1747 #define VIDEO_DIP_FREQ_2VSYNC (2 << 16) 1748 #define VIDEO_DIP_FREQ_MASK (3 << 16) 1749 /* HSW and later: */ 1750 #define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12) 1751 #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0) 1752 1753 /* Panel power sequencing */ 1754 #define PP_STATUS 0x61200 1755 #define PP_ON (1U << 31) 1756 /* 1757 * Indicates that all dependencies of the panel are on: 1758 * 1759 * - PLL enabled 1760 * - pipe enabled 1761 * - LVDS/DVOB/DVOC on 1762 */ 1763 #define PP_READY (1 << 30) 1764 #define PP_SEQUENCE_NONE (0 << 28) 1765 #define PP_SEQUENCE_POWER_UP (1 << 28) 1766 #define PP_SEQUENCE_POWER_DOWN (2 << 28) 1767 #define PP_SEQUENCE_MASK (3 << 28) 1768 #define PP_SEQUENCE_SHIFT 28 1769 #define PP_CYCLE_DELAY_ACTIVE (1 << 27) 1770 #define PP_SEQUENCE_STATE_MASK 0x0000000f 1771 #define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0) 1772 #define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0) 1773 #define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0) 1774 #define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0) 1775 #define PP_SEQUENCE_STATE_ON_IDLE (0x8 << 0) 1776 #define PP_SEQUENCE_STATE_ON_S1_0 (0x9 << 0) 1777 #define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0) 1778 #define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0) 1779 #define PP_SEQUENCE_STATE_RESET (0xf << 0) 1780 #define PP_CONTROL 0x61204 1781 #define POWER_TARGET_ON (1 << 0) 1782 #define PP_ON_DELAYS 0x61208 1783 #define PP_OFF_DELAYS 0x6120c 1784 #define PP_DIVISOR 0x61210 1785 1786 /* Panel fitting */ 1787 #define PFIT_CONTROL 0x61230 1788 #define PFIT_ENABLE (1U << 31) 1789 #define PFIT_PIPE_MASK (3 << 29) 1790 #define PFIT_PIPE_SHIFT 29 1791 #define VERT_INTERP_DISABLE (0 << 10) 1792 #define VERT_INTERP_BILINEAR (1 << 10) 1793 #define VERT_INTERP_MASK (3 << 10) 1794 #define VERT_AUTO_SCALE (1 << 9) 1795 #define HORIZ_INTERP_DISABLE (0 << 6) 1796 #define HORIZ_INTERP_BILINEAR (1 << 6) 1797 #define HORIZ_INTERP_MASK (3 << 6) 1798 #define HORIZ_AUTO_SCALE (1 << 5) 1799 #define PANEL_8TO6_DITHER_ENABLE (1 << 3) 1800 #define PFIT_FILTER_FUZZY (0 << 24) 1801 #define PFIT_SCALING_AUTO (0 << 26) 1802 #define PFIT_SCALING_PROGRAMMED (1 << 26) 1803 #define PFIT_SCALING_PILLAR (2 << 26) 1804 #define PFIT_SCALING_LETTER (3 << 26) 1805 #define PFIT_PGM_RATIOS 0x61234 1806 #define PFIT_VERT_SCALE_MASK 0xfff00000 1807 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0 1808 /* Pre-965 */ 1809 #define PFIT_VERT_SCALE_SHIFT 20 1810 #define PFIT_VERT_SCALE_MASK 0xfff00000 1811 #define PFIT_HORIZ_SCALE_SHIFT 4 1812 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0 1813 /* 965+ */ 1814 #define PFIT_VERT_SCALE_SHIFT_965 16 1815 #define PFIT_VERT_SCALE_MASK_965 0x1fff0000 1816 #define PFIT_HORIZ_SCALE_SHIFT_965 0 1817 #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff 1818 1819 #define PFIT_AUTO_RATIOS 0x61238 1820 1821 /* Backlight control */ 1822 #define BLC_PWM_CTL 0x61254 1823 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17) 1824 #define BLC_PWM_CTL2 0x61250 /* 965+ only */ 1825 #define BLM_COMBINATION_MODE (1 << 30) 1826 /* 1827 * This is the most significant 15 bits of the number of backlight cycles in a 1828 * complete cycle of the modulated backlight control. 1829 * 1830 * The actual value is this field multiplied by two. 1831 */ 1832 #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17) 1833 #define BLM_LEGACY_MODE (1 << 16) 1834 /* 1835 * This is the number of cycles out of the backlight modulation cycle for which 1836 * the backlight is on. 1837 * 1838 * This field must be no greater than the number of cycles in the complete 1839 * backlight modulation cycle. 1840 */ 1841 #define BACKLIGHT_DUTY_CYCLE_SHIFT (0) 1842 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) 1843 1844 #define BLC_HIST_CTL 0x61260 1845 1846 /* TV port control */ 1847 #define TV_CTL 0x68000 1848 /** Enables the TV encoder */ 1849 # define TV_ENC_ENABLE (1U << 31) 1850 /** Sources the TV encoder input from pipe B instead of A. */ 1851 # define TV_ENC_PIPEB_SELECT (1 << 30) 1852 /** Outputs composite video (DAC A only) */ 1853 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28) 1854 /** Outputs SVideo video (DAC B/C) */ 1855 # define TV_ENC_OUTPUT_SVIDEO (1 << 28) 1856 /** Outputs Component video (DAC A/B/C) */ 1857 # define TV_ENC_OUTPUT_COMPONENT (2 << 28) 1858 /** Outputs Composite and SVideo (DAC A/B/C) */ 1859 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28) 1860 # define TV_TRILEVEL_SYNC (1 << 21) 1861 /** Enables slow sync generation (945GM only) */ 1862 # define TV_SLOW_SYNC (1 << 20) 1863 /** Selects 4x oversampling for 480i and 576p */ 1864 # define TV_OVERSAMPLE_4X (0 << 18) 1865 /** Selects 2x oversampling for 720p and 1080i */ 1866 # define TV_OVERSAMPLE_2X (1 << 18) 1867 /** Selects no oversampling for 1080p */ 1868 # define TV_OVERSAMPLE_NONE (2 << 18) 1869 /** Selects 8x oversampling */ 1870 # define TV_OVERSAMPLE_8X (3 << 18) 1871 /** Selects progressive mode rather than interlaced */ 1872 # define TV_PROGRESSIVE (1 << 17) 1873 /** Sets the colorburst to PAL mode. Required for non-M PAL modes. */ 1874 # define TV_PAL_BURST (1 << 16) 1875 /** Field for setting delay of Y compared to C */ 1876 # define TV_YC_SKEW_MASK (7 << 12) 1877 /** Enables a fix for 480p/576p standard definition modes on the 915GM only */ 1878 # define TV_ENC_SDP_FIX (1 << 11) 1879 /** 1880 * Enables a fix for the 915GM only. 1881 * 1882 * Not sure what it does. 1883 */ 1884 # define TV_ENC_C0_FIX (1 << 10) 1885 /** Bits that must be preserved by software */ 1886 # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf) 1887 # define TV_FUSE_STATE_MASK (3 << 4) 1888 /** Read-only state that reports all features enabled */ 1889 # define TV_FUSE_STATE_ENABLED (0 << 4) 1890 /** Read-only state that reports that Macrovision is disabled in hardware*/ 1891 # define TV_FUSE_STATE_NO_MACROVISION (1 << 4) 1892 /** Read-only state that reports that TV-out is disabled in hardware. */ 1893 # define TV_FUSE_STATE_DISABLED (2 << 4) 1894 /** Normal operation */ 1895 # define TV_TEST_MODE_NORMAL (0 << 0) 1896 /** Encoder test pattern 1 - combo pattern */ 1897 # define TV_TEST_MODE_PATTERN_1 (1 << 0) 1898 /** Encoder test pattern 2 - full screen vertical 75% color bars */ 1899 # define TV_TEST_MODE_PATTERN_2 (2 << 0) 1900 /** Encoder test pattern 3 - full screen horizontal 75% color bars */ 1901 # define TV_TEST_MODE_PATTERN_3 (3 << 0) 1902 /** Encoder test pattern 4 - random noise */ 1903 # define TV_TEST_MODE_PATTERN_4 (4 << 0) 1904 /** Encoder test pattern 5 - linear color ramps */ 1905 # define TV_TEST_MODE_PATTERN_5 (5 << 0) 1906 /** 1907 * This test mode forces the DACs to 50% of full output. 1908 * 1909 * This is used for load detection in combination with TVDAC_SENSE_MASK 1910 */ 1911 # define TV_TEST_MODE_MONITOR_DETECT (7 << 0) 1912 # define TV_TEST_MODE_MASK (7 << 0) 1913 1914 #define TV_DAC 0x68004 1915 # define TV_DAC_SAVE 0x00ffff00 1916 /** 1917 * Reports that DAC state change logic has reported change (RO). 1918 * 1919 * This gets cleared when TV_DAC_STATE_EN is cleared 1920 */ 1921 # define TVDAC_STATE_CHG (1U << 31) 1922 # define TVDAC_SENSE_MASK (7 << 28) 1923 /** Reports that DAC A voltage is above the detect threshold */ 1924 # define TVDAC_A_SENSE (1 << 30) 1925 /** Reports that DAC B voltage is above the detect threshold */ 1926 # define TVDAC_B_SENSE (1 << 29) 1927 /** Reports that DAC C voltage is above the detect threshold */ 1928 # define TVDAC_C_SENSE (1 << 28) 1929 /** 1930 * Enables DAC state detection logic, for load-based TV detection. 1931 * 1932 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set 1933 * to off, for load detection to work. 1934 */ 1935 # define TVDAC_STATE_CHG_EN (1 << 27) 1936 /** Sets the DAC A sense value to high */ 1937 # define TVDAC_A_SENSE_CTL (1 << 26) 1938 /** Sets the DAC B sense value to high */ 1939 # define TVDAC_B_SENSE_CTL (1 << 25) 1940 /** Sets the DAC C sense value to high */ 1941 # define TVDAC_C_SENSE_CTL (1 << 24) 1942 /** Overrides the ENC_ENABLE and DAC voltage levels */ 1943 # define DAC_CTL_OVERRIDE (1 << 7) 1944 /** Sets the slew rate. Must be preserved in software */ 1945 # define ENC_TVDAC_SLEW_FAST (1 << 6) 1946 # define DAC_A_1_3_V (0 << 4) 1947 # define DAC_A_1_1_V (1 << 4) 1948 # define DAC_A_0_7_V (2 << 4) 1949 # define DAC_A_MASK (3 << 4) 1950 # define DAC_B_1_3_V (0 << 2) 1951 # define DAC_B_1_1_V (1 << 2) 1952 # define DAC_B_0_7_V (2 << 2) 1953 # define DAC_B_MASK (3 << 2) 1954 # define DAC_C_1_3_V (0 << 0) 1955 # define DAC_C_1_1_V (1 << 0) 1956 # define DAC_C_0_7_V (2 << 0) 1957 # define DAC_C_MASK (3 << 0) 1958 1959 /** 1960 * CSC coefficients are stored in a floating point format with 9 bits of 1961 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n, 1962 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with 1963 * -1 (0x3) being the only legal negative value. 1964 */ 1965 #define TV_CSC_Y 0x68010 1966 # define TV_RY_MASK 0x07ff0000 1967 # define TV_RY_SHIFT 16 1968 # define TV_GY_MASK 0x00000fff 1969 # define TV_GY_SHIFT 0 1970 1971 #define TV_CSC_Y2 0x68014 1972 # define TV_BY_MASK 0x07ff0000 1973 # define TV_BY_SHIFT 16 1974 /** 1975 * Y attenuation for component video. 1976 * 1977 * Stored in 1.9 fixed point. 1978 */ 1979 # define TV_AY_MASK 0x000003ff 1980 # define TV_AY_SHIFT 0 1981 1982 #define TV_CSC_U 0x68018 1983 # define TV_RU_MASK 0x07ff0000 1984 # define TV_RU_SHIFT 16 1985 # define TV_GU_MASK 0x000007ff 1986 # define TV_GU_SHIFT 0 1987 1988 #define TV_CSC_U2 0x6801c 1989 # define TV_BU_MASK 0x07ff0000 1990 # define TV_BU_SHIFT 16 1991 /** 1992 * U attenuation for component video. 1993 * 1994 * Stored in 1.9 fixed point. 1995 */ 1996 # define TV_AU_MASK 0x000003ff 1997 # define TV_AU_SHIFT 0 1998 1999 #define TV_CSC_V 0x68020 2000 # define TV_RV_MASK 0x0fff0000 2001 # define TV_RV_SHIFT 16 2002 # define TV_GV_MASK 0x000007ff 2003 # define TV_GV_SHIFT 0 2004 2005 #define TV_CSC_V2 0x68024 2006 # define TV_BV_MASK 0x07ff0000 2007 # define TV_BV_SHIFT 16 2008 /** 2009 * V attenuation for component video. 2010 * 2011 * Stored in 1.9 fixed point. 2012 */ 2013 # define TV_AV_MASK 0x000007ff 2014 # define TV_AV_SHIFT 0 2015 2016 #define TV_CLR_KNOBS 0x68028 2017 /** 2s-complement brightness adjustment */ 2018 # define TV_BRIGHTNESS_MASK 0xff000000 2019 # define TV_BRIGHTNESS_SHIFT 24 2020 /** Contrast adjustment, as a 2.6 unsigned floating point number */ 2021 # define TV_CONTRAST_MASK 0x00ff0000 2022 # define TV_CONTRAST_SHIFT 16 2023 /** Saturation adjustment, as a 2.6 unsigned floating point number */ 2024 # define TV_SATURATION_MASK 0x0000ff00 2025 # define TV_SATURATION_SHIFT 8 2026 /** Hue adjustment, as an integer phase angle in degrees */ 2027 # define TV_HUE_MASK 0x000000ff 2028 # define TV_HUE_SHIFT 0 2029 2030 #define TV_CLR_LEVEL 0x6802c 2031 /** Controls the DAC level for black */ 2032 # define TV_BLACK_LEVEL_MASK 0x01ff0000 2033 # define TV_BLACK_LEVEL_SHIFT 16 2034 /** Controls the DAC level for blanking */ 2035 # define TV_BLANK_LEVEL_MASK 0x000001ff 2036 # define TV_BLANK_LEVEL_SHIFT 0 2037 2038 #define TV_H_CTL_1 0x68030 2039 /** Number of pixels in the hsync. */ 2040 # define TV_HSYNC_END_MASK 0x1fff0000 2041 # define TV_HSYNC_END_SHIFT 16 2042 /** Total number of pixels minus one in the line (display and blanking). */ 2043 # define TV_HTOTAL_MASK 0x00001fff 2044 # define TV_HTOTAL_SHIFT 0 2045 2046 #define TV_H_CTL_2 0x68034 2047 /** Enables the colorburst (needed for non-component color) */ 2048 # define TV_BURST_ENA (1U << 31) 2049 /** Offset of the colorburst from the start of hsync, in pixels minus one. */ 2050 # define TV_HBURST_START_SHIFT 16 2051 # define TV_HBURST_START_MASK 0x1fff0000 2052 /** Length of the colorburst */ 2053 # define TV_HBURST_LEN_SHIFT 0 2054 # define TV_HBURST_LEN_MASK 0x0001fff 2055 2056 #define TV_H_CTL_3 0x68038 2057 /** End of hblank, measured in pixels minus one from start of hsync */ 2058 # define TV_HBLANK_END_SHIFT 16 2059 # define TV_HBLANK_END_MASK 0x1fff0000 2060 /** Start of hblank, measured in pixels minus one from start of hsync */ 2061 # define TV_HBLANK_START_SHIFT 0 2062 # define TV_HBLANK_START_MASK 0x0001fff 2063 2064 #define TV_V_CTL_1 0x6803c 2065 /** XXX */ 2066 # define TV_NBR_END_SHIFT 16 2067 # define TV_NBR_END_MASK 0x07ff0000 2068 /** XXX */ 2069 # define TV_VI_END_F1_SHIFT 8 2070 # define TV_VI_END_F1_MASK 0x00003f00 2071 /** XXX */ 2072 # define TV_VI_END_F2_SHIFT 0 2073 # define TV_VI_END_F2_MASK 0x0000003f 2074 2075 #define TV_V_CTL_2 0x68040 2076 /** Length of vsync, in half lines */ 2077 # define TV_VSYNC_LEN_MASK 0x07ff0000 2078 # define TV_VSYNC_LEN_SHIFT 16 2079 /** Offset of the start of vsync in field 1, measured in one less than the 2080 * number of half lines. 2081 */ 2082 # define TV_VSYNC_START_F1_MASK 0x00007f00 2083 # define TV_VSYNC_START_F1_SHIFT 8 2084 /** 2085 * Offset of the start of vsync in field 2, measured in one less than the 2086 * number of half lines. 2087 */ 2088 # define TV_VSYNC_START_F2_MASK 0x0000007f 2089 # define TV_VSYNC_START_F2_SHIFT 0 2090 2091 #define TV_V_CTL_3 0x68044 2092 /** Enables generation of the equalization signal */ 2093 # define TV_EQUAL_ENA (1U << 31) 2094 /** Length of vsync, in half lines */ 2095 # define TV_VEQ_LEN_MASK 0x007f0000 2096 # define TV_VEQ_LEN_SHIFT 16 2097 /** Offset of the start of equalization in field 1, measured in one less than 2098 * the number of half lines. 2099 */ 2100 # define TV_VEQ_START_F1_MASK 0x0007f00 2101 # define TV_VEQ_START_F1_SHIFT 8 2102 /** 2103 * Offset of the start of equalization in field 2, measured in one less than 2104 * the number of half lines. 2105 */ 2106 # define TV_VEQ_START_F2_MASK 0x000007f 2107 # define TV_VEQ_START_F2_SHIFT 0 2108 2109 #define TV_V_CTL_4 0x68048 2110 /** 2111 * Offset to start of vertical colorburst, measured in one less than the 2112 * number of lines from vertical start. 2113 */ 2114 # define TV_VBURST_START_F1_MASK 0x003f0000 2115 # define TV_VBURST_START_F1_SHIFT 16 2116 /** 2117 * Offset to the end of vertical colorburst, measured in one less than the 2118 * number of lines from the start of NBR. 2119 */ 2120 # define TV_VBURST_END_F1_MASK 0x000000ff 2121 # define TV_VBURST_END_F1_SHIFT 0 2122 2123 #define TV_V_CTL_5 0x6804c 2124 /** 2125 * Offset to start of vertical colorburst, measured in one less than the 2126 * number of lines from vertical start. 2127 */ 2128 # define TV_VBURST_START_F2_MASK 0x003f0000 2129 # define TV_VBURST_START_F2_SHIFT 16 2130 /** 2131 * Offset to the end of vertical colorburst, measured in one less than the 2132 * number of lines from the start of NBR. 2133 */ 2134 # define TV_VBURST_END_F2_MASK 0x000000ff 2135 # define TV_VBURST_END_F2_SHIFT 0 2136 2137 #define TV_V_CTL_6 0x68050 2138 /** 2139 * Offset to start of vertical colorburst, measured in one less than the 2140 * number of lines from vertical start. 2141 */ 2142 # define TV_VBURST_START_F3_MASK 0x003f0000 2143 # define TV_VBURST_START_F3_SHIFT 16 2144 /** 2145 * Offset to the end of vertical colorburst, measured in one less than the 2146 * number of lines from the start of NBR. 2147 */ 2148 # define TV_VBURST_END_F3_MASK 0x000000ff 2149 # define TV_VBURST_END_F3_SHIFT 0 2150 2151 #define TV_V_CTL_7 0x68054 2152 /** 2153 * Offset to start of vertical colorburst, measured in one less than the 2154 * number of lines from vertical start. 2155 */ 2156 # define TV_VBURST_START_F4_MASK 0x003f0000 2157 # define TV_VBURST_START_F4_SHIFT 16 2158 /** 2159 * Offset to the end of vertical colorburst, measured in one less than the 2160 * number of lines from the start of NBR. 2161 */ 2162 # define TV_VBURST_END_F4_MASK 0x000000ff 2163 # define TV_VBURST_END_F4_SHIFT 0 2164 2165 #define TV_SC_CTL_1 0x68060 2166 /** Turns on the first subcarrier phase generation DDA */ 2167 # define TV_SC_DDA1_EN (1U << 31) 2168 /** Turns on the first subcarrier phase generation DDA */ 2169 # define TV_SC_DDA2_EN (1 << 30) 2170 /** Turns on the first subcarrier phase generation DDA */ 2171 # define TV_SC_DDA3_EN (1 << 29) 2172 /** Sets the subcarrier DDA to reset frequency every other field */ 2173 # define TV_SC_RESET_EVERY_2 (0 << 24) 2174 /** Sets the subcarrier DDA to reset frequency every fourth field */ 2175 # define TV_SC_RESET_EVERY_4 (1 << 24) 2176 /** Sets the subcarrier DDA to reset frequency every eighth field */ 2177 # define TV_SC_RESET_EVERY_8 (2 << 24) 2178 /** Sets the subcarrier DDA to never reset the frequency */ 2179 # define TV_SC_RESET_NEVER (3 << 24) 2180 /** Sets the peak amplitude of the colorburst.*/ 2181 # define TV_BURST_LEVEL_MASK 0x00ff0000 2182 # define TV_BURST_LEVEL_SHIFT 16 2183 /** Sets the increment of the first subcarrier phase generation DDA */ 2184 # define TV_SCDDA1_INC_MASK 0x00000fff 2185 # define TV_SCDDA1_INC_SHIFT 0 2186 2187 #define TV_SC_CTL_2 0x68064 2188 /** Sets the rollover for the second subcarrier phase generation DDA */ 2189 # define TV_SCDDA2_SIZE_MASK 0x7fff0000 2190 # define TV_SCDDA2_SIZE_SHIFT 16 2191 /** Sets the increent of the second subcarrier phase generation DDA */ 2192 # define TV_SCDDA2_INC_MASK 0x00007fff 2193 # define TV_SCDDA2_INC_SHIFT 0 2194 2195 #define TV_SC_CTL_3 0x68068 2196 /** Sets the rollover for the third subcarrier phase generation DDA */ 2197 # define TV_SCDDA3_SIZE_MASK 0x7fff0000 2198 # define TV_SCDDA3_SIZE_SHIFT 16 2199 /** Sets the increent of the third subcarrier phase generation DDA */ 2200 # define TV_SCDDA3_INC_MASK 0x00007fff 2201 # define TV_SCDDA3_INC_SHIFT 0 2202 2203 #define TV_WIN_POS 0x68070 2204 /** X coordinate of the display from the start of horizontal active */ 2205 # define TV_XPOS_MASK 0x1fff0000 2206 # define TV_XPOS_SHIFT 16 2207 /** Y coordinate of the display from the start of vertical active (NBR) */ 2208 # define TV_YPOS_MASK 0x00000fff 2209 # define TV_YPOS_SHIFT 0 2210 2211 #define TV_WIN_SIZE 0x68074 2212 /** Horizontal size of the display window, measured in pixels*/ 2213 # define TV_XSIZE_MASK 0x1fff0000 2214 # define TV_XSIZE_SHIFT 16 2215 /** 2216 * Vertical size of the display window, measured in pixels. 2217 * 2218 * Must be even for interlaced modes. 2219 */ 2220 # define TV_YSIZE_MASK 0x00000fff 2221 # define TV_YSIZE_SHIFT 0 2222 2223 #define TV_FILTER_CTL_1 0x68080 2224 /** 2225 * Enables automatic scaling calculation. 2226 * 2227 * If set, the rest of the registers are ignored, and the calculated values can 2228 * be read back from the register. 2229 */ 2230 # define TV_AUTO_SCALE (1U << 31) 2231 /** 2232 * Disables the vertical filter. 2233 * 2234 * This is required on modes more than 1024 pixels wide */ 2235 # define TV_V_FILTER_BYPASS (1 << 29) 2236 /** Enables adaptive vertical filtering */ 2237 # define TV_VADAPT (1 << 28) 2238 # define TV_VADAPT_MODE_MASK (3 << 26) 2239 /** Selects the least adaptive vertical filtering mode */ 2240 # define TV_VADAPT_MODE_LEAST (0 << 26) 2241 /** Selects the moderately adaptive vertical filtering mode */ 2242 # define TV_VADAPT_MODE_MODERATE (1 << 26) 2243 /** Selects the most adaptive vertical filtering mode */ 2244 # define TV_VADAPT_MODE_MOST (3 << 26) 2245 /** 2246 * Sets the horizontal scaling factor. 2247 * 2248 * This should be the fractional part of the horizontal scaling factor divided 2249 * by the oversampling rate. TV_HSCALE should be less than 1, and set to: 2250 * 2251 * (src width - 1) / ((oversample * dest width) - 1) 2252 */ 2253 # define TV_HSCALE_FRAC_MASK 0x00003fff 2254 # define TV_HSCALE_FRAC_SHIFT 0 2255 2256 #define TV_FILTER_CTL_2 0x68084 2257 /** 2258 * Sets the integer part of the 3.15 fixed-point vertical scaling factor. 2259 * 2260 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1) 2261 */ 2262 # define TV_VSCALE_INT_MASK 0x00038000 2263 # define TV_VSCALE_INT_SHIFT 15 2264 /** 2265 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. 2266 * 2267 * \sa TV_VSCALE_INT_MASK 2268 */ 2269 # define TV_VSCALE_FRAC_MASK 0x00007fff 2270 # define TV_VSCALE_FRAC_SHIFT 0 2271 2272 #define TV_FILTER_CTL_3 0x68088 2273 /** 2274 * Sets the integer part of the 3.15 fixed-point vertical scaling factor. 2275 * 2276 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1)) 2277 * 2278 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. 2279 */ 2280 # define TV_VSCALE_IP_INT_MASK 0x00038000 2281 # define TV_VSCALE_IP_INT_SHIFT 15 2282 /** 2283 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. 2284 * 2285 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. 2286 * 2287 * \sa TV_VSCALE_IP_INT_MASK 2288 */ 2289 # define TV_VSCALE_IP_FRAC_MASK 0x00007fff 2290 # define TV_VSCALE_IP_FRAC_SHIFT 0 2291 2292 #define TV_CC_CONTROL 0x68090 2293 # define TV_CC_ENABLE (1U << 31) 2294 /** 2295 * Specifies which field to send the CC data in. 2296 * 2297 * CC data is usually sent in field 0. 2298 */ 2299 # define TV_CC_FID_MASK (1 << 27) 2300 # define TV_CC_FID_SHIFT 27 2301 /** Sets the horizontal position of the CC data. Usually 135. */ 2302 # define TV_CC_HOFF_MASK 0x03ff0000 2303 # define TV_CC_HOFF_SHIFT 16 2304 /** Sets the vertical position of the CC data. Usually 21 */ 2305 # define TV_CC_LINE_MASK 0x0000003f 2306 # define TV_CC_LINE_SHIFT 0 2307 2308 #define TV_CC_DATA 0x68094 2309 # define TV_CC_RDY (1U << 31) 2310 /** Second word of CC data to be transmitted. */ 2311 # define TV_CC_DATA_2_MASK 0x007f0000 2312 # define TV_CC_DATA_2_SHIFT 16 2313 /** First word of CC data to be transmitted. */ 2314 # define TV_CC_DATA_1_MASK 0x0000007f 2315 # define TV_CC_DATA_1_SHIFT 0 2316 2317 #define TV_H_LUMA_0 0x68100 2318 #define TV_H_LUMA_59 0x681ec 2319 #define TV_H_CHROMA_0 0x68200 2320 #define TV_H_CHROMA_59 0x682ec 2321 #define TV_V_LUMA_0 0x68300 2322 #define TV_V_LUMA_42 0x683a8 2323 #define TV_V_CHROMA_0 0x68400 2324 #define TV_V_CHROMA_42 0x684a8 2325 2326 /* Display Port */ 2327 #define DP_A 0x64000 /* eDP */ 2328 #define DP_B 0x64100 2329 #define DP_C 0x64200 2330 #define DP_D 0x64300 2331 2332 #define DP_PORT_EN (1U << 31) 2333 #define DP_PIPEB_SELECT (1 << 30) 2334 #define DP_PIPE_MASK (1 << 30) 2335 2336 /* Link training mode - select a suitable mode for each stage */ 2337 #define DP_LINK_TRAIN_PAT_1 (0 << 28) 2338 #define DP_LINK_TRAIN_PAT_2 (1 << 28) 2339 #define DP_LINK_TRAIN_PAT_IDLE (2 << 28) 2340 #define DP_LINK_TRAIN_OFF (3 << 28) 2341 #define DP_LINK_TRAIN_MASK (3 << 28) 2342 #define DP_LINK_TRAIN_SHIFT 28 2343 2344 /* CPT Link training mode */ 2345 #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8) 2346 #define DP_LINK_TRAIN_PAT_2_CPT (1 << 8) 2347 #define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8) 2348 #define DP_LINK_TRAIN_OFF_CPT (3 << 8) 2349 #define DP_LINK_TRAIN_MASK_CPT (7 << 8) 2350 #define DP_LINK_TRAIN_SHIFT_CPT 8 2351 2352 /* Signal voltages. These are mostly controlled by the other end */ 2353 #define DP_VOLTAGE_0_4 (0 << 25) 2354 #define DP_VOLTAGE_0_6 (1 << 25) 2355 #define DP_VOLTAGE_0_8 (2 << 25) 2356 #define DP_VOLTAGE_1_2 (3 << 25) 2357 #define DP_VOLTAGE_MASK (7 << 25) 2358 #define DP_VOLTAGE_SHIFT 25 2359 2360 /* Signal pre-emphasis levels, like voltages, the other end tells us what 2361 * they want 2362 */ 2363 #define DP_PRE_EMPHASIS_0 (0 << 22) 2364 #define DP_PRE_EMPHASIS_3_5 (1 << 22) 2365 #define DP_PRE_EMPHASIS_6 (2 << 22) 2366 #define DP_PRE_EMPHASIS_9_5 (3 << 22) 2367 #define DP_PRE_EMPHASIS_MASK (7 << 22) 2368 #define DP_PRE_EMPHASIS_SHIFT 22 2369 2370 /* How many wires to use. I guess 3 was too hard */ 2371 #define DP_PORT_WIDTH_1 (0 << 19) 2372 #define DP_PORT_WIDTH_2 (1 << 19) 2373 #define DP_PORT_WIDTH_4 (3 << 19) 2374 #define DP_PORT_WIDTH_MASK (7 << 19) 2375 2376 /* Mystic DPCD version 1.1 special mode */ 2377 #define DP_ENHANCED_FRAMING (1 << 18) 2378 2379 /* eDP */ 2380 #define DP_PLL_FREQ_270MHZ (0 << 16) 2381 #define DP_PLL_FREQ_160MHZ (1 << 16) 2382 #define DP_PLL_FREQ_MASK (3 << 16) 2383 2384 /** locked once port is enabled */ 2385 #define DP_PORT_REVERSAL (1 << 15) 2386 2387 /* eDP */ 2388 #define DP_PLL_ENABLE (1 << 14) 2389 2390 /** sends the clock on lane 15 of the PEG for debug */ 2391 #define DP_CLOCK_OUTPUT_ENABLE (1 << 13) 2392 2393 #define DP_SCRAMBLING_DISABLE (1 << 12) 2394 #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7) 2395 2396 /** limit RGB values to avoid confusing TVs */ 2397 #define DP_COLOR_RANGE_16_235 (1 << 8) 2398 2399 /** Turn on the audio link */ 2400 #define DP_AUDIO_OUTPUT_ENABLE (1 << 6) 2401 2402 /** vs and hs sync polarity */ 2403 #define DP_SYNC_VS_HIGH (1 << 4) 2404 #define DP_SYNC_HS_HIGH (1 << 3) 2405 2406 /** A fantasy */ 2407 #define DP_DETECTED (1 << 2) 2408 2409 /** The aux channel provides a way to talk to the 2410 * signal sink for DDC etc. Max packet size supported 2411 * is 20 bytes in each direction, hence the 5 fixed 2412 * data registers 2413 */ 2414 #define DPA_AUX_CH_CTL 0x64010 2415 #define DPA_AUX_CH_DATA1 0x64014 2416 #define DPA_AUX_CH_DATA2 0x64018 2417 #define DPA_AUX_CH_DATA3 0x6401c 2418 #define DPA_AUX_CH_DATA4 0x64020 2419 #define DPA_AUX_CH_DATA5 0x64024 2420 2421 #define DPB_AUX_CH_CTL 0x64110 2422 #define DPB_AUX_CH_DATA1 0x64114 2423 #define DPB_AUX_CH_DATA2 0x64118 2424 #define DPB_AUX_CH_DATA3 0x6411c 2425 #define DPB_AUX_CH_DATA4 0x64120 2426 #define DPB_AUX_CH_DATA5 0x64124 2427 2428 #define DPC_AUX_CH_CTL 0x64210 2429 #define DPC_AUX_CH_DATA1 0x64214 2430 #define DPC_AUX_CH_DATA2 0x64218 2431 #define DPC_AUX_CH_DATA3 0x6421c 2432 #define DPC_AUX_CH_DATA4 0x64220 2433 #define DPC_AUX_CH_DATA5 0x64224 2434 2435 #define DPD_AUX_CH_CTL 0x64310 2436 #define DPD_AUX_CH_DATA1 0x64314 2437 #define DPD_AUX_CH_DATA2 0x64318 2438 #define DPD_AUX_CH_DATA3 0x6431c 2439 #define DPD_AUX_CH_DATA4 0x64320 2440 #define DPD_AUX_CH_DATA5 0x64324 2441 2442 #define DP_AUX_CH_CTL_SEND_BUSY (1U << 31) 2443 #define DP_AUX_CH_CTL_DONE (1 << 30) 2444 #define DP_AUX_CH_CTL_INTERRUPT (1 << 29) 2445 #define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28) 2446 #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26) 2447 #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26) 2448 #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26) 2449 #define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26) 2450 #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26) 2451 #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25) 2452 #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20) 2453 #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20 2454 #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16) 2455 #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16 2456 #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15) 2457 #define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14) 2458 #define DP_AUX_CH_CTL_SYNC_TEST (1 << 13) 2459 #define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12) 2460 #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11) 2461 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff) 2462 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0 2463 2464 /* 2465 * Computing GMCH M and N values for the Display Port link 2466 * 2467 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes 2468 * 2469 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz) 2470 * 2471 * The GMCH value is used internally 2472 * 2473 * bytes_per_pixel is the number of bytes coming out of the plane, 2474 * which is after the LUTs, so we want the bytes for our color format. 2475 * For our current usage, this is always 3, one byte for R, G and B. 2476 */ 2477 #define _PIPEA_GMCH_DATA_M 0x70050 2478 #define _PIPEB_GMCH_DATA_M 0x71050 2479 2480 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */ 2481 #define PIPE_GMCH_DATA_M_TU_SIZE_MASK (0x3f << 25) 2482 #define PIPE_GMCH_DATA_M_TU_SIZE_SHIFT 25 2483 2484 #define PIPE_GMCH_DATA_M_MASK (0xffffff) 2485 2486 #define _PIPEA_GMCH_DATA_N 0x70054 2487 #define _PIPEB_GMCH_DATA_N 0x71054 2488 #define PIPE_GMCH_DATA_N_MASK (0xffffff) 2489 2490 /* 2491 * Computing Link M and N values for the Display Port link 2492 * 2493 * Link M / N = pixel_clock / ls_clk 2494 * 2495 * (the DP spec calls pixel_clock the 'strm_clk') 2496 * 2497 * The Link value is transmitted in the Main Stream 2498 * Attributes and VB-ID. 2499 */ 2500 2501 #define _PIPEA_DP_LINK_M 0x70060 2502 #define _PIPEB_DP_LINK_M 0x71060 2503 #define PIPEA_DP_LINK_M_MASK (0xffffff) 2504 2505 #define _PIPEA_DP_LINK_N 0x70064 2506 #define _PIPEB_DP_LINK_N 0x71064 2507 #define PIPEA_DP_LINK_N_MASK (0xffffff) 2508 2509 #define PIPE_GMCH_DATA_M(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_M, _PIPEB_GMCH_DATA_M) 2510 #define PIPE_GMCH_DATA_N(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_N, _PIPEB_GMCH_DATA_N) 2511 #define PIPE_DP_LINK_M(pipe) _PIPE(pipe, _PIPEA_DP_LINK_M, _PIPEB_DP_LINK_M) 2512 #define PIPE_DP_LINK_N(pipe) _PIPE(pipe, _PIPEA_DP_LINK_N, _PIPEB_DP_LINK_N) 2513 2514 /* Display & cursor control */ 2515 2516 /* Pipe A */ 2517 #define _PIPEADSL 0x70000 2518 #define DSL_LINEMASK_GEN2 0x00000fff 2519 #define DSL_LINEMASK_GEN3 0x00001fff 2520 #define _PIPEACONF 0x70008 2521 #define PIPECONF_ENABLE (1<<31) 2522 #define PIPECONF_DISABLE 0 2523 #define PIPECONF_DOUBLE_WIDE (1<<30) 2524 #define I965_PIPECONF_ACTIVE (1<<30) 2525 #define PIPECONF_FRAME_START_DELAY_MASK (3<<27) 2526 #define PIPECONF_SINGLE_WIDE 0 2527 #define PIPECONF_PIPE_UNLOCKED 0 2528 #define PIPECONF_PIPE_LOCKED (1<<25) 2529 #define PIPECONF_PALETTE 0 2530 #define PIPECONF_GAMMA (1<<24) 2531 #define PIPECONF_FORCE_BORDER (1<<25) 2532 #define PIPECONF_INTERLACE_MASK (7 << 21) 2533 /* Note that pre-gen3 does not support interlaced display directly. Panel 2534 * fitting must be disabled on pre-ilk for interlaced. */ 2535 #define PIPECONF_PROGRESSIVE (0 << 21) 2536 #define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */ 2537 #define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */ 2538 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) 2539 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */ 2540 /* Ironlake and later have a complete new set of values for interlaced. PFIT 2541 * means panel fitter required, PF means progressive fetch, DBL means power 2542 * saving pixel doubling. */ 2543 #define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21) 2544 #define PIPECONF_INTERLACED_ILK (3 << 21) 2545 #define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */ 2546 #define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */ 2547 #define PIPECONF_CXSR_DOWNCLOCK (1<<16) 2548 #define PIPECONF_BPP_MASK (0x000000e0) 2549 #define PIPECONF_BPP_8 (0<<5) 2550 #define PIPECONF_BPP_10 (1<<5) 2551 #define PIPECONF_BPP_6 (2<<5) 2552 #define PIPECONF_BPP_12 (3<<5) 2553 #define PIPECONF_DITHER_EN (1<<4) 2554 #define PIPECONF_DITHER_TYPE_MASK (0x0000000c) 2555 #define PIPECONF_DITHER_TYPE_SP (0<<2) 2556 #define PIPECONF_DITHER_TYPE_ST1 (1<<2) 2557 #define PIPECONF_DITHER_TYPE_ST2 (2<<2) 2558 #define PIPECONF_DITHER_TYPE_TEMP (3<<2) 2559 #define _PIPEASTAT 0x70024 2560 #define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31) 2561 #define SPRITE1_FLIPDONE_INT_EN_VLV (1UL<<30) 2562 #define PIPE_CRC_ERROR_ENABLE (1UL<<29) 2563 #define PIPE_CRC_DONE_ENABLE (1UL<<28) 2564 #define PIPE_GMBUS_EVENT_ENABLE (1UL<<27) 2565 #define PLANE_FLIP_DONE_INT_EN_VLV (1UL<<26) 2566 #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26) 2567 #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25) 2568 #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24) 2569 #define PIPE_DPST_EVENT_ENABLE (1UL<<23) 2570 #define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL<<26) 2571 #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22) 2572 #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) 2573 #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) 2574 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */ 2575 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */ 2576 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17) 2577 #define PIPEA_HBLANK_INT_EN_VLV (1UL<<16) 2578 #define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16) 2579 #define SPRITE1_FLIPDONE_INT_STATUS_VLV (1UL<<15) 2580 #define SPRITE0_FLIPDONE_INT_STATUS_VLV (1UL<<15) 2581 #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) 2582 #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12) 2583 #define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11) 2584 #define PLANE_FLIPDONE_INT_STATUS_VLV (1UL<<10) 2585 #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10) 2586 #define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9) 2587 #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) 2588 #define PIPE_DPST_EVENT_STATUS (1UL<<7) 2589 #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6) 2590 #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5) 2591 #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4) 2592 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */ 2593 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */ 2594 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1) 2595 #define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0) 2596 #define PIPE_BPC_MASK (7 << 5) /* Ironlake */ 2597 #define PIPE_8BPC (0 << 5) 2598 #define PIPE_10BPC (1 << 5) 2599 #define PIPE_6BPC (2 << 5) 2600 #define PIPE_12BPC (3 << 5) 2601 2602 #define PIPESRC(pipe) _PIPE(pipe, _PIPEASRC, _PIPEBSRC) 2603 #define PIPECONF(pipe) _PIPE(pipe, _PIPEACONF, _PIPEBCONF) 2604 #define PIPEDSL(pipe) _PIPE(pipe, _PIPEADSL, _PIPEBDSL) 2605 #define PIPEFRAME(pipe) _PIPE(pipe, _PIPEAFRAMEHIGH, _PIPEBFRAMEHIGH) 2606 #define PIPEFRAMEPIXEL(pipe) _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL) 2607 #define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT) 2608 2609 #define VLV_DPFLIPSTAT 0x70028 2610 #define PIPEB_LINE_COMPARE_STATUS (1<<29) 2611 #define PIPEB_HLINE_INT_EN (1<<28) 2612 #define PIPEB_VBLANK_INT_EN (1<<27) 2613 #define SPRITED_FLIPDONE_INT_EN (1<<26) 2614 #define SPRITEC_FLIPDONE_INT_EN (1<<25) 2615 #define PLANEB_FLIPDONE_INT_EN (1<<24) 2616 #define PIPEA_LINE_COMPARE_STATUS (1<<21) 2617 #define PIPEA_HLINE_INT_EN (1<<20) 2618 #define PIPEA_VBLANK_INT_EN (1<<19) 2619 #define SPRITEB_FLIPDONE_INT_EN (1<<18) 2620 #define SPRITEA_FLIPDONE_INT_EN (1<<17) 2621 #define PLANEA_FLIPDONE_INT_EN (1<<16) 2622 2623 #define DPINVGTT 0x7002c /* VLV only */ 2624 #define CURSORB_INVALID_GTT_INT_EN (1<<23) 2625 #define CURSORA_INVALID_GTT_INT_EN (1<<22) 2626 #define SPRITED_INVALID_GTT_INT_EN (1<<21) 2627 #define SPRITEC_INVALID_GTT_INT_EN (1<<20) 2628 #define PLANEB_INVALID_GTT_INT_EN (1<<19) 2629 #define SPRITEB_INVALID_GTT_INT_EN (1<<18) 2630 #define SPRITEA_INVALID_GTT_INT_EN (1<<17) 2631 #define PLANEA_INVALID_GTT_INT_EN (1<<16) 2632 #define DPINVGTT_EN_MASK 0xff0000 2633 #define CURSORB_INVALID_GTT_STATUS (1<<7) 2634 #define CURSORA_INVALID_GTT_STATUS (1<<6) 2635 #define SPRITED_INVALID_GTT_STATUS (1<<5) 2636 #define SPRITEC_INVALID_GTT_STATUS (1<<4) 2637 #define PLANEB_INVALID_GTT_STATUS (1<<3) 2638 #define SPRITEB_INVALID_GTT_STATUS (1<<2) 2639 #define SPRITEA_INVALID_GTT_STATUS (1<<1) 2640 #define PLANEA_INVALID_GTT_STATUS (1<<0) 2641 #define DPINVGTT_STATUS_MASK 0xff 2642 2643 #define DSPARB 0x70030 2644 #define DSPARB_CSTART_MASK (0x7f << 7) 2645 #define DSPARB_CSTART_SHIFT 7 2646 #define DSPARB_BSTART_MASK (0x7f) 2647 #define DSPARB_BSTART_SHIFT 0 2648 #define DSPARB_BEND_SHIFT 9 /* on 855 */ 2649 #define DSPARB_AEND_SHIFT 0 2650 2651 #define DSPFW1 0x70034 2652 #define DSPFW_SR_SHIFT 23 2653 #define DSPFW_SR_MASK (0x1ff<<23) 2654 #define DSPFW_CURSORB_SHIFT 16 2655 #define DSPFW_CURSORB_MASK (0x3f<<16) 2656 #define DSPFW_PLANEB_SHIFT 8 2657 #define DSPFW_PLANEB_MASK (0x7f<<8) 2658 #define DSPFW_PLANEA_MASK (0x7f) 2659 #define DSPFW2 0x70038 2660 #define DSPFW_CURSORA_MASK 0x00003f00 2661 #define DSPFW_CURSORA_SHIFT 8 2662 #define DSPFW_PLANEC_MASK (0x7f) 2663 #define DSPFW3 0x7003c 2664 #define DSPFW_HPLL_SR_EN (1<<31) 2665 #define DSPFW_CURSOR_SR_SHIFT 24 2666 #define PINEVIEW_SELF_REFRESH_EN (1<<30) 2667 #define DSPFW_CURSOR_SR_MASK (0x3f<<24) 2668 #define DSPFW_HPLL_CURSOR_SHIFT 16 2669 #define DSPFW_HPLL_CURSOR_MASK (0x3f<<16) 2670 #define DSPFW_HPLL_SR_MASK (0x1ff) 2671 2672 /* drain latency register values*/ 2673 #define DRAIN_LATENCY_PRECISION_32 32 2674 #define DRAIN_LATENCY_PRECISION_16 16 2675 #define VLV_DDL1 0x70050 2676 #define DDL_CURSORA_PRECISION_32 (1<<31) 2677 #define DDL_CURSORA_PRECISION_16 (0<<31) 2678 #define DDL_CURSORA_SHIFT 24 2679 #define DDL_PLANEA_PRECISION_32 (1<<7) 2680 #define DDL_PLANEA_PRECISION_16 (0<<7) 2681 #define VLV_DDL2 0x70054 2682 #define DDL_CURSORB_PRECISION_32 (1<<31) 2683 #define DDL_CURSORB_PRECISION_16 (0<<31) 2684 #define DDL_CURSORB_SHIFT 24 2685 #define DDL_PLANEB_PRECISION_32 (1<<7) 2686 #define DDL_PLANEB_PRECISION_16 (0<<7) 2687 2688 /* FIFO watermark sizes etc */ 2689 #define G4X_FIFO_LINE_SIZE 64 2690 #define I915_FIFO_LINE_SIZE 64 2691 #define I830_FIFO_LINE_SIZE 32 2692 2693 #define VALLEYVIEW_FIFO_SIZE 255 2694 #define G4X_FIFO_SIZE 127 2695 #define I965_FIFO_SIZE 512 2696 #define I945_FIFO_SIZE 127 2697 #define I915_FIFO_SIZE 95 2698 #define I855GM_FIFO_SIZE 127 /* In cachelines */ 2699 #define I830_FIFO_SIZE 95 2700 2701 #define VALLEYVIEW_MAX_WM 0xff 2702 #define G4X_MAX_WM 0x3f 2703 #define I915_MAX_WM 0x3f 2704 2705 #define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */ 2706 #define PINEVIEW_FIFO_LINE_SIZE 64 2707 #define PINEVIEW_MAX_WM 0x1ff 2708 #define PINEVIEW_DFT_WM 0x3f 2709 #define PINEVIEW_DFT_HPLLOFF_WM 0 2710 #define PINEVIEW_GUARD_WM 10 2711 #define PINEVIEW_CURSOR_FIFO 64 2712 #define PINEVIEW_CURSOR_MAX_WM 0x3f 2713 #define PINEVIEW_CURSOR_DFT_WM 0 2714 #define PINEVIEW_CURSOR_GUARD_WM 5 2715 2716 #define VALLEYVIEW_CURSOR_MAX_WM 64 2717 #define I965_CURSOR_FIFO 64 2718 #define I965_CURSOR_MAX_WM 32 2719 #define I965_CURSOR_DFT_WM 8 2720 2721 /* define the Watermark register on Ironlake */ 2722 #define WM0_PIPEA_ILK 0x45100 2723 #define WM0_PIPE_PLANE_MASK (0x7f<<16) 2724 #define WM0_PIPE_PLANE_SHIFT 16 2725 #define WM0_PIPE_SPRITE_MASK (0x3f<<8) 2726 #define WM0_PIPE_SPRITE_SHIFT 8 2727 #define WM0_PIPE_CURSOR_MASK (0x1f) 2728 2729 #define WM0_PIPEB_ILK 0x45104 2730 #define WM0_PIPEC_IVB 0x45200 2731 #define WM1_LP_ILK 0x45108 2732 #define WM1_LP_SR_EN (1<<31) 2733 #define WM1_LP_LATENCY_SHIFT 24 2734 #define WM1_LP_LATENCY_MASK (0x7f<<24) 2735 #define WM1_LP_FBC_MASK (0xf<<20) 2736 #define WM1_LP_FBC_SHIFT 20 2737 #define WM1_LP_SR_MASK (0x1ff<<8) 2738 #define WM1_LP_SR_SHIFT 8 2739 #define WM1_LP_CURSOR_MASK (0x3f) 2740 #define WM2_LP_ILK 0x4510c 2741 #define WM2_LP_EN (1<<31) 2742 #define WM3_LP_ILK 0x45110 2743 #define WM3_LP_EN (1<<31) 2744 #define WM1S_LP_ILK 0x45120 2745 #define WM2S_LP_IVB 0x45124 2746 #define WM3S_LP_IVB 0x45128 2747 #define WM1S_LP_EN (1<<31) 2748 2749 /* Memory latency timer register */ 2750 #define MLTR_ILK 0x11222 2751 #define MLTR_WM1_SHIFT 0 2752 #define MLTR_WM2_SHIFT 8 2753 /* the unit of memory self-refresh latency time is 0.5us */ 2754 #define ILK_SRLT_MASK 0x3f 2755 #define ILK_LATENCY(shift) (I915_READ(MLTR_ILK) >> (shift) & ILK_SRLT_MASK) 2756 #define ILK_READ_WM1_LATENCY() ILK_LATENCY(MLTR_WM1_SHIFT) 2757 #define ILK_READ_WM2_LATENCY() ILK_LATENCY(MLTR_WM2_SHIFT) 2758 2759 /* define the fifo size on Ironlake */ 2760 #define ILK_DISPLAY_FIFO 128 2761 #define ILK_DISPLAY_MAXWM 64 2762 #define ILK_DISPLAY_DFTWM 8 2763 #define ILK_CURSOR_FIFO 32 2764 #define ILK_CURSOR_MAXWM 16 2765 #define ILK_CURSOR_DFTWM 8 2766 2767 #define ILK_DISPLAY_SR_FIFO 512 2768 #define ILK_DISPLAY_MAX_SRWM 0x1ff 2769 #define ILK_DISPLAY_DFT_SRWM 0x3f 2770 #define ILK_CURSOR_SR_FIFO 64 2771 #define ILK_CURSOR_MAX_SRWM 0x3f 2772 #define ILK_CURSOR_DFT_SRWM 8 2773 2774 #define ILK_FIFO_LINE_SIZE 64 2775 2776 /* define the WM info on Sandybridge */ 2777 #define SNB_DISPLAY_FIFO 128 2778 #define SNB_DISPLAY_MAXWM 0x7f /* bit 16:22 */ 2779 #define SNB_DISPLAY_DFTWM 8 2780 #define SNB_CURSOR_FIFO 32 2781 #define SNB_CURSOR_MAXWM 0x1f /* bit 4:0 */ 2782 #define SNB_CURSOR_DFTWM 8 2783 2784 #define SNB_DISPLAY_SR_FIFO 512 2785 #define SNB_DISPLAY_MAX_SRWM 0x1ff /* bit 16:8 */ 2786 #define SNB_DISPLAY_DFT_SRWM 0x3f 2787 #define SNB_CURSOR_SR_FIFO 64 2788 #define SNB_CURSOR_MAX_SRWM 0x3f /* bit 5:0 */ 2789 #define SNB_CURSOR_DFT_SRWM 8 2790 2791 #define SNB_FBC_MAX_SRWM 0xf /* bit 23:20 */ 2792 2793 #define SNB_FIFO_LINE_SIZE 64 2794 2795 2796 /* the address where we get all kinds of latency value */ 2797 #define SSKPD 0x5d10 2798 #define SSKPD_WM_MASK 0x3f 2799 #define SSKPD_WM0_SHIFT 0 2800 #define SSKPD_WM1_SHIFT 8 2801 #define SSKPD_WM2_SHIFT 16 2802 #define SSKPD_WM3_SHIFT 24 2803 2804 #define SNB_LATENCY(shift) (I915_READ(MCHBAR_MIRROR_BASE_SNB + SSKPD) >> (shift) & SSKPD_WM_MASK) 2805 #define SNB_READ_WM0_LATENCY() SNB_LATENCY(SSKPD_WM0_SHIFT) 2806 #define SNB_READ_WM1_LATENCY() SNB_LATENCY(SSKPD_WM1_SHIFT) 2807 #define SNB_READ_WM2_LATENCY() SNB_LATENCY(SSKPD_WM2_SHIFT) 2808 #define SNB_READ_WM3_LATENCY() SNB_LATENCY(SSKPD_WM3_SHIFT) 2809 2810 /* 2811 * The two pipe frame counter registers are not synchronized, so 2812 * reading a stable value is somewhat tricky. The following code 2813 * should work: 2814 * 2815 * do { 2816 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 2817 * PIPE_FRAME_HIGH_SHIFT; 2818 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >> 2819 * PIPE_FRAME_LOW_SHIFT); 2820 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 2821 * PIPE_FRAME_HIGH_SHIFT); 2822 * } while (high1 != high2); 2823 * frame = (high1 << 8) | low1; 2824 */ 2825 #define _PIPEAFRAMEHIGH 0x70040 2826 #define PIPE_FRAME_HIGH_MASK 0x0000ffff 2827 #define PIPE_FRAME_HIGH_SHIFT 0 2828 #define _PIPEAFRAMEPIXEL 0x70044 2829 #define PIPE_FRAME_LOW_MASK 0xff000000 2830 #define PIPE_FRAME_LOW_SHIFT 24 2831 #define PIPE_PIXEL_MASK 0x00ffffff 2832 #define PIPE_PIXEL_SHIFT 0 2833 /* GM45+ just has to be different */ 2834 #define _PIPEA_FRMCOUNT_GM45 0x70040 2835 #define _PIPEA_FLIPCOUNT_GM45 0x70044 2836 #define PIPE_FRMCOUNT_GM45(pipe) _PIPE(pipe, _PIPEA_FRMCOUNT_GM45, _PIPEB_FRMCOUNT_GM45) 2837 2838 /* Cursor A & B regs */ 2839 #define _CURACNTR 0x70080 2840 /* Old style CUR*CNTR flags (desktop 8xx) */ 2841 #define CURSOR_ENABLE 0x80000000 2842 #define CURSOR_GAMMA_ENABLE 0x40000000 2843 #define CURSOR_STRIDE_MASK 0x30000000 2844 #define CURSOR_FORMAT_SHIFT 24 2845 #define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT) 2846 #define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT) 2847 #define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT) 2848 #define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT) 2849 #define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT) 2850 #define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT) 2851 /* New style CUR*CNTR flags */ 2852 #define CURSOR_MODE 0x27 2853 #define CURSOR_MODE_DISABLE 0x00 2854 #define CURSOR_MODE_64_32B_AX 0x07 2855 #define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX) 2856 #define MCURSOR_PIPE_SELECT (1 << 28) 2857 #define MCURSOR_PIPE_A 0x00 2858 #define MCURSOR_PIPE_B (1 << 28) 2859 #define MCURSOR_GAMMA_ENABLE (1 << 26) 2860 #define _CURABASE 0x70084 2861 #define _CURAPOS 0x70088 2862 #define CURSOR_POS_MASK 0x007FF 2863 #define CURSOR_POS_SIGN 0x8000 2864 #define CURSOR_X_SHIFT 0 2865 #define CURSOR_Y_SHIFT 16 2866 #define CURSIZE 0x700a0 2867 #define _CURBCNTR 0x700c0 2868 #define _CURBBASE 0x700c4 2869 #define _CURBPOS 0x700c8 2870 2871 #define _CURBCNTR_IVB 0x71080 2872 #define _CURBBASE_IVB 0x71084 2873 #define _CURBPOS_IVB 0x71088 2874 2875 #define CURCNTR(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR) 2876 #define CURBASE(pipe) _PIPE(pipe, _CURABASE, _CURBBASE) 2877 #define CURPOS(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS) 2878 2879 #define CURCNTR_IVB(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR_IVB) 2880 #define CURBASE_IVB(pipe) _PIPE(pipe, _CURABASE, _CURBBASE_IVB) 2881 #define CURPOS_IVB(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS_IVB) 2882 2883 /* Display A control */ 2884 #define _DSPACNTR 0x70180 2885 #define DISPLAY_PLANE_ENABLE (1<<31) 2886 #define DISPLAY_PLANE_DISABLE 0 2887 #define DISPPLANE_GAMMA_ENABLE (1<<30) 2888 #define DISPPLANE_GAMMA_DISABLE 0 2889 #define DISPPLANE_PIXFORMAT_MASK (0xf<<26) 2890 #define DISPPLANE_8BPP (0x2<<26) 2891 #define DISPPLANE_15_16BPP (0x4<<26) 2892 #define DISPPLANE_16BPP (0x5<<26) 2893 #define DISPPLANE_32BPP_NO_ALPHA (0x6<<26) 2894 #define DISPPLANE_32BPP (0x7<<26) 2895 #define DISPPLANE_32BPP_30BIT_NO_ALPHA (0xa<<26) 2896 #define DISPPLANE_STEREO_ENABLE (1<<25) 2897 #define DISPPLANE_STEREO_DISABLE 0 2898 #define DISPPLANE_SEL_PIPE_SHIFT 24 2899 #define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT) 2900 #define DISPPLANE_SEL_PIPE_A 0 2901 #define DISPPLANE_SEL_PIPE_B (1<<DISPPLANE_SEL_PIPE_SHIFT) 2902 #define DISPPLANE_SRC_KEY_ENABLE (1<<22) 2903 #define DISPPLANE_SRC_KEY_DISABLE 0 2904 #define DISPPLANE_LINE_DOUBLE (1<<20) 2905 #define DISPPLANE_NO_LINE_DOUBLE 0 2906 #define DISPPLANE_STEREO_POLARITY_FIRST 0 2907 #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) 2908 #define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */ 2909 #define DISPPLANE_TILED (1<<10) 2910 #define _DSPAADDR 0x70184 2911 #define _DSPASTRIDE 0x70188 2912 #define _DSPAPOS 0x7018C /* reserved */ 2913 #define _DSPASIZE 0x70190 2914 #define _DSPASURF 0x7019C /* 965+ only */ 2915 #define _DSPATILEOFF 0x701A4 /* 965+ only */ 2916 2917 #define DSPCNTR(plane) _PIPE(plane, _DSPACNTR, _DSPBCNTR) 2918 #define DSPADDR(plane) _PIPE(plane, _DSPAADDR, _DSPBADDR) 2919 #define DSPSTRIDE(plane) _PIPE(plane, _DSPASTRIDE, _DSPBSTRIDE) 2920 #define DSPPOS(plane) _PIPE(plane, _DSPAPOS, _DSPBPOS) 2921 #define DSPSIZE(plane) _PIPE(plane, _DSPASIZE, _DSPBSIZE) 2922 #define DSPSURF(plane) _PIPE(plane, _DSPASURF, _DSPBSURF) 2923 #define DSPTILEOFF(plane) _PIPE(plane, _DSPATILEOFF, _DSPBTILEOFF) 2924 2925 /* Display/Sprite base address macros */ 2926 #define DISP_BASEADDR_MASK (0xfffff000) 2927 #define I915_LO_DISPBASE(val) (val & ~DISP_BASEADDR_MASK) 2928 #define I915_HI_DISPBASE(val) (val & DISP_BASEADDR_MASK) 2929 #define I915_MODIFY_DISPBASE(reg, gfx_addr) \ 2930 (I915_WRITE(reg, gfx_addr | I915_LO_DISPBASE(I915_READ(reg)))) 2931 2932 /* VBIOS flags */ 2933 #define SWF00 0x71410 2934 #define SWF01 0x71414 2935 #define SWF02 0x71418 2936 #define SWF03 0x7141c 2937 #define SWF04 0x71420 2938 #define SWF05 0x71424 2939 #define SWF06 0x71428 2940 #define SWF10 0x70410 2941 #define SWF11 0x70414 2942 #define SWF14 0x71420 2943 #define SWF30 0x72414 2944 #define SWF31 0x72418 2945 #define SWF32 0x7241c 2946 2947 /* Pipe B */ 2948 #define _PIPEBDSL 0x71000 2949 #define _PIPEBCONF 0x71008 2950 #define _PIPEBSTAT 0x71024 2951 #define _PIPEBFRAMEHIGH 0x71040 2952 #define _PIPEBFRAMEPIXEL 0x71044 2953 #define _PIPEB_FRMCOUNT_GM45 0x71040 2954 #define _PIPEB_FLIPCOUNT_GM45 0x71044 2955 2956 2957 /* Display B control */ 2958 #define _DSPBCNTR 0x71180 2959 #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) 2960 #define DISPPLANE_ALPHA_TRANS_DISABLE 0 2961 #define DISPPLANE_SPRITE_ABOVE_DISPLAY 0 2962 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) 2963 #define _DSPBADDR 0x71184 2964 #define _DSPBSTRIDE 0x71188 2965 #define _DSPBPOS 0x7118C 2966 #define _DSPBSIZE 0x71190 2967 #define _DSPBSURF 0x7119C 2968 #define _DSPBTILEOFF 0x711A4 2969 2970 /* Sprite A control */ 2971 #define _DVSACNTR 0x72180 2972 #define DVS_ENABLE (1<<31) 2973 #define DVS_GAMMA_ENABLE (1<<30) 2974 #define DVS_PIXFORMAT_MASK (3<<25) 2975 #define DVS_FORMAT_YUV422 (0<<25) 2976 #define DVS_FORMAT_RGBX101010 (1<<25) 2977 #define DVS_FORMAT_RGBX888 (2<<25) 2978 #define DVS_FORMAT_RGBX161616 (3<<25) 2979 #define DVS_SOURCE_KEY (1<<22) 2980 #define DVS_RGB_ORDER_XBGR (1<<20) 2981 #define DVS_YUV_BYTE_ORDER_MASK (3<<16) 2982 #define DVS_YUV_ORDER_YUYV (0<<16) 2983 #define DVS_YUV_ORDER_UYVY (1<<16) 2984 #define DVS_YUV_ORDER_YVYU (2<<16) 2985 #define DVS_YUV_ORDER_VYUY (3<<16) 2986 #define DVS_DEST_KEY (1<<2) 2987 #define DVS_TRICKLE_FEED_DISABLE (1<<14) 2988 #define DVS_TILED (1<<10) 2989 #define _DVSALINOFF 0x72184 2990 #define _DVSASTRIDE 0x72188 2991 #define _DVSAPOS 0x7218c 2992 #define _DVSASIZE 0x72190 2993 #define _DVSAKEYVAL 0x72194 2994 #define _DVSAKEYMSK 0x72198 2995 #define _DVSASURF 0x7219c 2996 #define _DVSAKEYMAXVAL 0x721a0 2997 #define _DVSATILEOFF 0x721a4 2998 #define _DVSASURFLIVE 0x721ac 2999 #define _DVSASCALE 0x72204 3000 #define DVS_SCALE_ENABLE (1<<31) 3001 #define DVS_FILTER_MASK (3<<29) 3002 #define DVS_FILTER_MEDIUM (0<<29) 3003 #define DVS_FILTER_ENHANCING (1<<29) 3004 #define DVS_FILTER_SOFTENING (2<<29) 3005 #define DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */ 3006 #define DVS_VERTICAL_OFFSET_ENABLE (1<<27) 3007 #define _DVSAGAMC 0x72300 3008 3009 #define _DVSBCNTR 0x73180 3010 #define _DVSBLINOFF 0x73184 3011 #define _DVSBSTRIDE 0x73188 3012 #define _DVSBPOS 0x7318c 3013 #define _DVSBSIZE 0x73190 3014 #define _DVSBKEYVAL 0x73194 3015 #define _DVSBKEYMSK 0x73198 3016 #define _DVSBSURF 0x7319c 3017 #define _DVSBKEYMAXVAL 0x731a0 3018 #define _DVSBTILEOFF 0x731a4 3019 #define _DVSBSURFLIVE 0x731ac 3020 #define _DVSBSCALE 0x73204 3021 #define _DVSBGAMC 0x73300 3022 3023 #define DVSCNTR(pipe) _PIPE(pipe, _DVSACNTR, _DVSBCNTR) 3024 #define DVSLINOFF(pipe) _PIPE(pipe, _DVSALINOFF, _DVSBLINOFF) 3025 #define DVSSTRIDE(pipe) _PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE) 3026 #define DVSPOS(pipe) _PIPE(pipe, _DVSAPOS, _DVSBPOS) 3027 #define DVSSURF(pipe) _PIPE(pipe, _DVSASURF, _DVSBSURF) 3028 #define DVSKEYMAX(pipe) _PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL) 3029 #define DVSSIZE(pipe) _PIPE(pipe, _DVSASIZE, _DVSBSIZE) 3030 #define DVSSCALE(pipe) _PIPE(pipe, _DVSASCALE, _DVSBSCALE) 3031 #define DVSTILEOFF(pipe) _PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF) 3032 #define DVSKEYVAL(pipe) _PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL) 3033 #define DVSKEYMSK(pipe) _PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK) 3034 3035 #define _SPRA_CTL 0x70280 3036 #define SPRITE_ENABLE (1<<31) 3037 #define SPRITE_GAMMA_ENABLE (1<<30) 3038 #define SPRITE_PIXFORMAT_MASK (7<<25) 3039 #define SPRITE_FORMAT_YUV422 (0<<25) 3040 #define SPRITE_FORMAT_RGBX101010 (1<<25) 3041 #define SPRITE_FORMAT_RGBX888 (2<<25) 3042 #define SPRITE_FORMAT_RGBX161616 (3<<25) 3043 #define SPRITE_FORMAT_YUV444 (4<<25) 3044 #define SPRITE_FORMAT_XR_BGR101010 (5<<25) /* Extended range */ 3045 #define SPRITE_CSC_ENABLE (1<<24) 3046 #define SPRITE_SOURCE_KEY (1<<22) 3047 #define SPRITE_RGB_ORDER_RGBX (1<<20) /* only for 888 and 161616 */ 3048 #define SPRITE_YUV_TO_RGB_CSC_DISABLE (1<<19) 3049 #define SPRITE_YUV_CSC_FORMAT_BT709 (1<<18) /* 0 is BT601 */ 3050 #define SPRITE_YUV_BYTE_ORDER_MASK (3<<16) 3051 #define SPRITE_YUV_ORDER_YUYV (0<<16) 3052 #define SPRITE_YUV_ORDER_UYVY (1<<16) 3053 #define SPRITE_YUV_ORDER_YVYU (2<<16) 3054 #define SPRITE_YUV_ORDER_VYUY (3<<16) 3055 #define SPRITE_TRICKLE_FEED_DISABLE (1<<14) 3056 #define SPRITE_INT_GAMMA_ENABLE (1<<13) 3057 #define SPRITE_TILED (1<<10) 3058 #define SPRITE_DEST_KEY (1<<2) 3059 #define _SPRA_LINOFF 0x70284 3060 #define _SPRA_STRIDE 0x70288 3061 #define _SPRA_POS 0x7028c 3062 #define _SPRA_SIZE 0x70290 3063 #define _SPRA_KEYVAL 0x70294 3064 #define _SPRA_KEYMSK 0x70298 3065 #define _SPRA_SURF 0x7029c 3066 #define _SPRA_KEYMAX 0x702a0 3067 #define _SPRA_TILEOFF 0x702a4 3068 #define _SPRA_SCALE 0x70304 3069 #define SPRITE_SCALE_ENABLE (1<<31) 3070 #define SPRITE_FILTER_MASK (3<<29) 3071 #define SPRITE_FILTER_MEDIUM (0<<29) 3072 #define SPRITE_FILTER_ENHANCING (1<<29) 3073 #define SPRITE_FILTER_SOFTENING (2<<29) 3074 #define SPRITE_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */ 3075 #define SPRITE_VERTICAL_OFFSET_ENABLE (1<<27) 3076 #define _SPRA_GAMC 0x70400 3077 3078 #define _SPRB_CTL 0x71280 3079 #define _SPRB_LINOFF 0x71284 3080 #define _SPRB_STRIDE 0x71288 3081 #define _SPRB_POS 0x7128c 3082 #define _SPRB_SIZE 0x71290 3083 #define _SPRB_KEYVAL 0x71294 3084 #define _SPRB_KEYMSK 0x71298 3085 #define _SPRB_SURF 0x7129c 3086 #define _SPRB_KEYMAX 0x712a0 3087 #define _SPRB_TILEOFF 0x712a4 3088 #define _SPRB_SCALE 0x71304 3089 #define _SPRB_GAMC 0x71400 3090 3091 #define SPRCTL(pipe) _PIPE(pipe, _SPRA_CTL, _SPRB_CTL) 3092 #define SPRLINOFF(pipe) _PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF) 3093 #define SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE) 3094 #define SPRPOS(pipe) _PIPE(pipe, _SPRA_POS, _SPRB_POS) 3095 #define SPRSIZE(pipe) _PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE) 3096 #define SPRKEYVAL(pipe) _PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL) 3097 #define SPRKEYMSK(pipe) _PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK) 3098 #define SPRSURF(pipe) _PIPE(pipe, _SPRA_SURF, _SPRB_SURF) 3099 #define SPRKEYMAX(pipe) _PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX) 3100 #define SPRTILEOFF(pipe) _PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF) 3101 #define SPRSCALE(pipe) _PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE) 3102 #define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) 3103 3104 /* VBIOS regs */ 3105 #define VGACNTRL 0x71400 3106 # define VGA_DISP_DISABLE (1U << 31) 3107 # define VGA_2X_MODE (1 << 30) 3108 # define VGA_PIPE_B_SELECT (1 << 29) 3109 3110 /* Ironlake */ 3111 3112 #define CPU_VGACNTRL 0x41000 3113 3114 #define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030 3115 #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) 3116 #define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2) 3117 #define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2) 3118 #define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2) 3119 #define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2) 3120 #define DIGITAL_PORTA_NO_DETECT (0 << 0) 3121 #define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1) 3122 #define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0) 3123 3124 /* refresh rate hardware control */ 3125 #define RR_HW_CTL 0x45300 3126 #define RR_HW_LOW_POWER_FRAMES_MASK 0xff 3127 #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00 3128 3129 #define FDI_PLL_BIOS_0 0x46000 3130 #define FDI_PLL_FB_CLOCK_MASK 0xff 3131 #define FDI_PLL_BIOS_1 0x46004 3132 #define FDI_PLL_BIOS_2 0x46008 3133 #define DISPLAY_PORT_PLL_BIOS_0 0x4600c 3134 #define DISPLAY_PORT_PLL_BIOS_1 0x46010 3135 #define DISPLAY_PORT_PLL_BIOS_2 0x46014 3136 3137 #define PCH_DSPCLK_GATE_D 0x42020 3138 # define DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9) 3139 # define DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8) 3140 # define DPFDUNIT_CLOCK_GATE_DISABLE (1 << 7) 3141 # define DPARBUNIT_CLOCK_GATE_DISABLE (1 << 5) 3142 3143 #define PCH_3DCGDIS0 0x46020 3144 # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18) 3145 # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1) 3146 3147 #define PCH_3DCGDIS1 0x46024 3148 # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11) 3149 3150 #define FDI_PLL_FREQ_CTL 0x46030 3151 #define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24) 3152 #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00 3153 #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff 3154 3155 3156 #define _PIPEA_DATA_M1 0x60030 3157 #define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */ 3158 #define TU_SIZE_MASK 0x7e000000 3159 #define PIPE_DATA_M1_OFFSET 0 3160 #define _PIPEA_DATA_N1 0x60034 3161 #define PIPE_DATA_N1_OFFSET 0 3162 3163 #define _PIPEA_DATA_M2 0x60038 3164 #define PIPE_DATA_M2_OFFSET 0 3165 #define _PIPEA_DATA_N2 0x6003c 3166 #define PIPE_DATA_N2_OFFSET 0 3167 3168 #define _PIPEA_LINK_M1 0x60040 3169 #define PIPE_LINK_M1_OFFSET 0 3170 #define _PIPEA_LINK_N1 0x60044 3171 #define PIPE_LINK_N1_OFFSET 0 3172 3173 #define _PIPEA_LINK_M2 0x60048 3174 #define PIPE_LINK_M2_OFFSET 0 3175 #define _PIPEA_LINK_N2 0x6004c 3176 #define PIPE_LINK_N2_OFFSET 0 3177 3178 /* PIPEB timing regs are same start from 0x61000 */ 3179 3180 #define _PIPEB_DATA_M1 0x61030 3181 #define _PIPEB_DATA_N1 0x61034 3182 3183 #define _PIPEB_DATA_M2 0x61038 3184 #define _PIPEB_DATA_N2 0x6103c 3185 3186 #define _PIPEB_LINK_M1 0x61040 3187 #define _PIPEB_LINK_N1 0x61044 3188 3189 #define _PIPEB_LINK_M2 0x61048 3190 #define _PIPEB_LINK_N2 0x6104c 3191 3192 #define PIPE_DATA_M1(pipe) _PIPE(pipe, _PIPEA_DATA_M1, _PIPEB_DATA_M1) 3193 #define PIPE_DATA_N1(pipe) _PIPE(pipe, _PIPEA_DATA_N1, _PIPEB_DATA_N1) 3194 #define PIPE_DATA_M2(pipe) _PIPE(pipe, _PIPEA_DATA_M2, _PIPEB_DATA_M2) 3195 #define PIPE_DATA_N2(pipe) _PIPE(pipe, _PIPEA_DATA_N2, _PIPEB_DATA_N2) 3196 #define PIPE_LINK_M1(pipe) _PIPE(pipe, _PIPEA_LINK_M1, _PIPEB_LINK_M1) 3197 #define PIPE_LINK_N1(pipe) _PIPE(pipe, _PIPEA_LINK_N1, _PIPEB_LINK_N1) 3198 #define PIPE_LINK_M2(pipe) _PIPE(pipe, _PIPEA_LINK_M2, _PIPEB_LINK_M2) 3199 #define PIPE_LINK_N2(pipe) _PIPE(pipe, _PIPEA_LINK_N2, _PIPEB_LINK_N2) 3200 3201 /* CPU panel fitter */ 3202 /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */ 3203 #define _PFA_CTL_1 0x68080 3204 #define _PFB_CTL_1 0x68880 3205 #define PF_ENABLE (1<<31) 3206 #define PF_FILTER_MASK (3<<23) 3207 #define PF_FILTER_PROGRAMMED (0<<23) 3208 #define PF_FILTER_MED_3x3 (1<<23) 3209 #define PF_FILTER_EDGE_ENHANCE (2<<23) 3210 #define PF_FILTER_EDGE_SOFTEN (3<<23) 3211 #define _PFA_WIN_SZ 0x68074 3212 #define _PFB_WIN_SZ 0x68874 3213 #define _PFA_WIN_POS 0x68070 3214 #define _PFB_WIN_POS 0x68870 3215 #define _PFA_VSCALE 0x68084 3216 #define _PFB_VSCALE 0x68884 3217 #define _PFA_HSCALE 0x68090 3218 #define _PFB_HSCALE 0x68890 3219 3220 #define PF_CTL(pipe) _PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1) 3221 #define PF_WIN_SZ(pipe) _PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ) 3222 #define PF_WIN_POS(pipe) _PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS) 3223 #define PF_VSCALE(pipe) _PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE) 3224 #define PF_HSCALE(pipe) _PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE) 3225 3226 /* legacy palette */ 3227 #define _LGC_PALETTE_A 0x4a000 3228 #define _LGC_PALETTE_B 0x4a800 3229 #define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) 3230 3231 /* interrupts */ 3232 #define DE_MASTER_IRQ_CONTROL (1U << 31) 3233 #define DE_SPRITEB_FLIP_DONE (1 << 29) 3234 #define DE_SPRITEA_FLIP_DONE (1 << 28) 3235 #define DE_PLANEB_FLIP_DONE (1 << 27) 3236 #define DE_PLANEA_FLIP_DONE (1 << 26) 3237 #define DE_PCU_EVENT (1 << 25) 3238 #define DE_GTT_FAULT (1 << 24) 3239 #define DE_POISON (1 << 23) 3240 #define DE_PERFORM_COUNTER (1 << 22) 3241 #define DE_PCH_EVENT (1 << 21) 3242 #define DE_AUX_CHANNEL_A (1 << 20) 3243 #define DE_DP_A_HOTPLUG (1 << 19) 3244 #define DE_GSE (1 << 18) 3245 #define DE_PIPEB_VBLANK (1 << 15) 3246 #define DE_PIPEB_EVEN_FIELD (1 << 14) 3247 #define DE_PIPEB_ODD_FIELD (1 << 13) 3248 #define DE_PIPEB_LINE_COMPARE (1 << 12) 3249 #define DE_PIPEB_VSYNC (1 << 11) 3250 #define DE_PIPEB_FIFO_UNDERRUN (1 << 8) 3251 #define DE_PIPEA_VBLANK (1 << 7) 3252 #define DE_PIPEA_EVEN_FIELD (1 << 6) 3253 #define DE_PIPEA_ODD_FIELD (1 << 5) 3254 #define DE_PIPEA_LINE_COMPARE (1 << 4) 3255 #define DE_PIPEA_VSYNC (1 << 3) 3256 #define DE_PIPEA_FIFO_UNDERRUN (1 << 0) 3257 3258 /* More Ivybridge lolz */ 3259 #define DE_ERR_DEBUG_IVB (1<<30) 3260 #define DE_GSE_IVB (1<<29) 3261 #define DE_PCH_EVENT_IVB (1<<28) 3262 #define DE_DP_A_HOTPLUG_IVB (1<<27) 3263 #define DE_AUX_CHANNEL_A_IVB (1<<26) 3264 #define DE_SPRITEC_FLIP_DONE_IVB (1<<14) 3265 #define DE_PLANEC_FLIP_DONE_IVB (1<<13) 3266 #define DE_PIPEC_VBLANK_IVB (1<<10) 3267 #define DE_SPRITEB_FLIP_DONE_IVB (1<<9) 3268 #define DE_PLANEB_FLIP_DONE_IVB (1<<8) 3269 #define DE_PIPEB_VBLANK_IVB (1<<5) 3270 #define DE_SPRITEA_FLIP_DONE_IVB (1<<4) 3271 #define DE_PLANEA_FLIP_DONE_IVB (1<<3) 3272 #define DE_PIPEA_VBLANK_IVB (1<<0) 3273 3274 #define VLV_MASTER_IER 0x4400c /* Gunit master IER */ 3275 #define MASTER_INTERRUPT_ENABLE (1<<31) 3276 3277 #define DEISR 0x44000 3278 #define DEIMR 0x44004 3279 #define DEIIR 0x44008 3280 #define DEIER 0x4400c 3281 3282 /* GT interrupt. 3283 * Note that for gen6+ the ring-specific interrupt bits do alias with the 3284 * corresponding bits in the per-ring interrupt control registers. */ 3285 #define GT_GEN6_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26) 3286 #define GT_GEN6_BLT_CS_ERROR_INTERRUPT (1 << 25) 3287 #define GT_GEN6_BLT_USER_INTERRUPT (1 << 22) 3288 #define GT_GEN6_BSD_CS_ERROR_INTERRUPT (1 << 15) 3289 #define GT_GEN6_BSD_USER_INTERRUPT (1 << 12) 3290 #define GT_BSD_USER_INTERRUPT (1 << 5) /* ilk only */ 3291 #define GT_GEN7_L3_PARITY_ERROR_INTERRUPT (1 << 5) 3292 #define GT_PIPE_NOTIFY (1 << 4) 3293 #define GT_RENDER_CS_ERROR_INTERRUPT (1 << 3) 3294 #define GT_SYNC_STATUS (1 << 2) 3295 #define GT_USER_INTERRUPT (1 << 0) 3296 3297 #define GTISR 0x44010 3298 #define GTIMR 0x44014 3299 #define GTIIR 0x44018 3300 #define GTIER 0x4401c 3301 3302 #define ILK_DISPLAY_CHICKEN2 0x42004 3303 /* Required on all Ironlake and Sandybridge according to the B-Spec. */ 3304 #define ILK_ELPIN_409_SELECT (1 << 25) 3305 #define ILK_DPARB_GATE (1<<22) 3306 #define ILK_VSDPFD_FULL (1<<21) 3307 #define ILK_DISPLAY_CHICKEN_FUSES 0x42014 3308 #define ILK_INTERNAL_GRAPHICS_DISABLE (1<<31) 3309 #define ILK_INTERNAL_DISPLAY_DISABLE (1<<30) 3310 #define ILK_DISPLAY_DEBUG_DISABLE (1<<29) 3311 #define ILK_HDCP_DISABLE (1<<25) 3312 #define ILK_eDP_A_DISABLE (1<<24) 3313 #define ILK_DESKTOP (1<<23) 3314 #define ILK_DSPCLK_GATE 0x42020 3315 #define IVB_VRHUNIT_CLK_GATE (1<<28) 3316 #define ILK_DPARB_CLK_GATE (1<<5) 3317 #define ILK_DPFD_CLK_GATE (1<<7) 3318 3319 /* According to spec this bit 7/8/9 of 0x42020 should be set to enable FBC */ 3320 #define ILK_CLK_FBC (1<<7) 3321 #define ILK_DPFC_DIS1 (1<<8) 3322 #define ILK_DPFC_DIS2 (1<<9) 3323 3324 #define IVB_CHICKEN3 0x4200c 3325 # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5) 3326 # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2) 3327 3328 #define DISP_ARB_CTL 0x45000 3329 #define DISP_TILE_SURFACE_SWIZZLING (1<<13) 3330 #define DISP_FBC_WM_DIS (1<<15) 3331 3332 /* GEN7 chicken */ 3333 #define GEN7_COMMON_SLICE_CHICKEN1 0x7010 3334 # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26)) 3335 3336 #define GEN7_L3CNTLREG1 0xB01C 3337 #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C4FFF8C 3338 3339 #define GEN7_L3_CHICKEN_MODE_REGISTER 0xB030 3340 #define GEN7_WA_L3_CHICKEN_MODE 0x20000000 3341 3342 /* WaCatErrorRejectionIssue */ 3343 #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030 3344 #define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11) 3345 3346 /* PCH */ 3347 3348 /* south display engine interrupt */ 3349 #define SDE_AUDIO_POWER_D (1 << 27) 3350 #define SDE_AUDIO_POWER_C (1 << 26) 3351 #define SDE_AUDIO_POWER_B (1 << 25) 3352 #define SDE_AUDIO_POWER_SHIFT (25) 3353 #define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT) 3354 #define SDE_GMBUS (1 << 24) 3355 #define SDE_AUDIO_HDCP_TRANSB (1 << 23) 3356 #define SDE_AUDIO_HDCP_TRANSA (1 << 22) 3357 #define SDE_AUDIO_HDCP_MASK (3 << 22) 3358 #define SDE_AUDIO_TRANSB (1 << 21) 3359 #define SDE_AUDIO_TRANSA (1 << 20) 3360 #define SDE_AUDIO_TRANS_MASK (3 << 20) 3361 #define SDE_POISON (1 << 19) 3362 /* 18 reserved */ 3363 #define SDE_FDI_RXB (1 << 17) 3364 #define SDE_FDI_RXA (1 << 16) 3365 #define SDE_FDI_MASK (3 << 16) 3366 #define SDE_AUXD (1 << 15) 3367 #define SDE_AUXC (1 << 14) 3368 #define SDE_AUXB (1 << 13) 3369 #define SDE_AUX_MASK (7 << 13) 3370 /* 12 reserved */ 3371 #define SDE_CRT_HOTPLUG (1 << 11) 3372 #define SDE_PORTD_HOTPLUG (1 << 10) 3373 #define SDE_PORTC_HOTPLUG (1 << 9) 3374 #define SDE_PORTB_HOTPLUG (1 << 8) 3375 #define SDE_SDVOB_HOTPLUG (1 << 6) 3376 #define SDE_HOTPLUG_MASK (0xf << 8) 3377 #define SDE_TRANSB_CRC_DONE (1 << 5) 3378 #define SDE_TRANSB_CRC_ERR (1 << 4) 3379 #define SDE_TRANSB_FIFO_UNDER (1 << 3) 3380 #define SDE_TRANSA_CRC_DONE (1 << 2) 3381 #define SDE_TRANSA_CRC_ERR (1 << 1) 3382 #define SDE_TRANSA_FIFO_UNDER (1 << 0) 3383 #define SDE_TRANS_MASK (0x3f) 3384 /* CPT */ 3385 #define SDE_CRT_HOTPLUG_CPT (1 << 19) 3386 #define SDE_PORTD_HOTPLUG_CPT (1 << 23) 3387 #define SDE_PORTC_HOTPLUG_CPT (1 << 22) 3388 #define SDE_PORTB_HOTPLUG_CPT (1 << 21) 3389 #define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \ 3390 SDE_PORTD_HOTPLUG_CPT | \ 3391 SDE_PORTC_HOTPLUG_CPT | \ 3392 SDE_PORTB_HOTPLUG_CPT) 3393 3394 #define SDEISR 0xc4000 3395 #define SDEIMR 0xc4004 3396 #define SDEIIR 0xc4008 3397 #define SDEIER 0xc400c 3398 3399 /* digital port hotplug */ 3400 #define PCH_PORT_HOTPLUG 0xc4030 /* SHOTPLUG_CTL */ 3401 #define PORTD_HOTPLUG_ENABLE (1 << 20) 3402 #define PORTD_PULSE_DURATION_2ms (0) 3403 #define PORTD_PULSE_DURATION_4_5ms (1 << 18) 3404 #define PORTD_PULSE_DURATION_6ms (2 << 18) 3405 #define PORTD_PULSE_DURATION_100ms (3 << 18) 3406 #define PORTD_PULSE_DURATION_MASK (3 << 18) 3407 #define PORTD_HOTPLUG_NO_DETECT (0) 3408 #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16) 3409 #define PORTD_HOTPLUG_LONG_DETECT (1 << 17) 3410 #define PORTC_HOTPLUG_ENABLE (1 << 12) 3411 #define PORTC_PULSE_DURATION_2ms (0) 3412 #define PORTC_PULSE_DURATION_4_5ms (1 << 10) 3413 #define PORTC_PULSE_DURATION_6ms (2 << 10) 3414 #define PORTC_PULSE_DURATION_100ms (3 << 10) 3415 #define PORTC_PULSE_DURATION_MASK (3 << 10) 3416 #define PORTC_HOTPLUG_NO_DETECT (0) 3417 #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8) 3418 #define PORTC_HOTPLUG_LONG_DETECT (1 << 9) 3419 #define PORTB_HOTPLUG_ENABLE (1 << 4) 3420 #define PORTB_PULSE_DURATION_2ms (0) 3421 #define PORTB_PULSE_DURATION_4_5ms (1 << 2) 3422 #define PORTB_PULSE_DURATION_6ms (2 << 2) 3423 #define PORTB_PULSE_DURATION_100ms (3 << 2) 3424 #define PORTB_PULSE_DURATION_MASK (3 << 2) 3425 #define PORTB_HOTPLUG_NO_DETECT (0) 3426 #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0) 3427 #define PORTB_HOTPLUG_LONG_DETECT (1 << 1) 3428 3429 #define PCH_GPIOA 0xc5010 3430 #define PCH_GPIOB 0xc5014 3431 #define PCH_GPIOC 0xc5018 3432 #define PCH_GPIOD 0xc501c 3433 #define PCH_GPIOE 0xc5020 3434 #define PCH_GPIOF 0xc5024 3435 3436 #define PCH_GMBUS0 0xc5100 3437 #define PCH_GMBUS1 0xc5104 3438 #define PCH_GMBUS2 0xc5108 3439 #define PCH_GMBUS3 0xc510c 3440 #define PCH_GMBUS4 0xc5110 3441 #define PCH_GMBUS5 0xc5120 3442 3443 #define _PCH_DPLL_A 0xc6014 3444 #define _PCH_DPLL_B 0xc6018 3445 #define _PCH_DPLL(pll) (pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B) 3446 3447 #define _PCH_FPA0 0xc6040 3448 #define FP_CB_TUNE (0x3<<22) 3449 #define _PCH_FPA1 0xc6044 3450 #define _PCH_FPB0 0xc6048 3451 #define _PCH_FPB1 0xc604c 3452 #define _PCH_FP0(pll) (pll == 0 ? _PCH_FPA0 : _PCH_FPB0) 3453 #define _PCH_FP1(pll) (pll == 0 ? _PCH_FPA1 : _PCH_FPB1) 3454 3455 #define PCH_DPLL_TEST 0xc606c 3456 3457 #define PCH_DREF_CONTROL 0xC6200 3458 #define DREF_CONTROL_MASK 0x7fc3 3459 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13) 3460 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13) 3461 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13) 3462 #define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13) 3463 #define DREF_SSC_SOURCE_DISABLE (0<<11) 3464 #define DREF_SSC_SOURCE_ENABLE (2<<11) 3465 #define DREF_SSC_SOURCE_MASK (3<<11) 3466 #define DREF_NONSPREAD_SOURCE_DISABLE (0<<9) 3467 #define DREF_NONSPREAD_CK505_ENABLE (1<<9) 3468 #define DREF_NONSPREAD_SOURCE_ENABLE (2<<9) 3469 #define DREF_NONSPREAD_SOURCE_MASK (3<<9) 3470 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7) 3471 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7) 3472 #define DREF_SUPERSPREAD_SOURCE_MASK (3<<7) 3473 #define DREF_SSC4_DOWNSPREAD (0<<6) 3474 #define DREF_SSC4_CENTERSPREAD (1<<6) 3475 #define DREF_SSC1_DISABLE (0<<1) 3476 #define DREF_SSC1_ENABLE (1<<1) 3477 #define DREF_SSC4_DISABLE (0) 3478 #define DREF_SSC4_ENABLE (1) 3479 3480 #define PCH_RAWCLK_FREQ 0xc6204 3481 #define FDL_TP1_TIMER_SHIFT 12 3482 #define FDL_TP1_TIMER_MASK (3<<12) 3483 #define FDL_TP2_TIMER_SHIFT 10 3484 #define FDL_TP2_TIMER_MASK (3<<10) 3485 #define RAWCLK_FREQ_MASK 0x3ff 3486 3487 #define PCH_DPLL_TMR_CFG 0xc6208 3488 3489 #define PCH_SSC4_PARMS 0xc6210 3490 #define PCH_SSC4_AUX_PARMS 0xc6214 3491 3492 #define PCH_DPLL_SEL 0xc7000 3493 #define TRANSA_DPLL_ENABLE (1<<3) 3494 #define TRANSA_DPLLB_SEL (1<<0) 3495 #define TRANSA_DPLLA_SEL 0 3496 #define TRANSB_DPLL_ENABLE (1<<7) 3497 #define TRANSB_DPLLB_SEL (1<<4) 3498 #define TRANSB_DPLLA_SEL (0) 3499 #define TRANSC_DPLL_ENABLE (1<<11) 3500 #define TRANSC_DPLLB_SEL (1<<8) 3501 #define TRANSC_DPLLA_SEL (0) 3502 3503 /* transcoder */ 3504 3505 #define _TRANS_HTOTAL_A 0xe0000 3506 #define TRANS_HTOTAL_SHIFT 16 3507 #define TRANS_HACTIVE_SHIFT 0 3508 #define _TRANS_HBLANK_A 0xe0004 3509 #define TRANS_HBLANK_END_SHIFT 16 3510 #define TRANS_HBLANK_START_SHIFT 0 3511 #define _TRANS_HSYNC_A 0xe0008 3512 #define TRANS_HSYNC_END_SHIFT 16 3513 #define TRANS_HSYNC_START_SHIFT 0 3514 #define _TRANS_VTOTAL_A 0xe000c 3515 #define TRANS_VTOTAL_SHIFT 16 3516 #define TRANS_VACTIVE_SHIFT 0 3517 #define _TRANS_VBLANK_A 0xe0010 3518 #define TRANS_VBLANK_END_SHIFT 16 3519 #define TRANS_VBLANK_START_SHIFT 0 3520 #define _TRANS_VSYNC_A 0xe0014 3521 #define TRANS_VSYNC_END_SHIFT 16 3522 #define TRANS_VSYNC_START_SHIFT 0 3523 #define _TRANS_VSYNCSHIFT_A 0xe0028 3524 3525 #define _TRANSA_DATA_M1 0xe0030 3526 #define _TRANSA_DATA_N1 0xe0034 3527 #define _TRANSA_DATA_M2 0xe0038 3528 #define _TRANSA_DATA_N2 0xe003c 3529 #define _TRANSA_DP_LINK_M1 0xe0040 3530 #define _TRANSA_DP_LINK_N1 0xe0044 3531 #define _TRANSA_DP_LINK_M2 0xe0048 3532 #define _TRANSA_DP_LINK_N2 0xe004c 3533 3534 /* Per-transcoder DIP controls */ 3535 3536 #define _VIDEO_DIP_CTL_A 0xe0200 3537 #define _VIDEO_DIP_DATA_A 0xe0208 3538 #define _VIDEO_DIP_GCP_A 0xe0210 3539 3540 #define _VIDEO_DIP_CTL_B 0xe1200 3541 #define _VIDEO_DIP_DATA_B 0xe1208 3542 #define _VIDEO_DIP_GCP_B 0xe1210 3543 3544 #define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B) 3545 #define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B) 3546 #define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B) 3547 3548 #define VLV_VIDEO_DIP_CTL_A 0x60220 3549 #define VLV_VIDEO_DIP_DATA_A 0x60208 3550 #define VLV_VIDEO_DIP_GDCP_PAYLOAD_A 0x60210 3551 3552 #define VLV_VIDEO_DIP_CTL_B 0x61170 3553 #define VLV_VIDEO_DIP_DATA_B 0x61174 3554 #define VLV_VIDEO_DIP_GDCP_PAYLOAD_B 0x61178 3555 3556 #define VLV_TVIDEO_DIP_CTL(pipe) \ 3557 _PIPE(pipe, VLV_VIDEO_DIP_CTL_A, VLV_VIDEO_DIP_CTL_B) 3558 #define VLV_TVIDEO_DIP_DATA(pipe) \ 3559 _PIPE(pipe, VLV_VIDEO_DIP_DATA_A, VLV_VIDEO_DIP_DATA_B) 3560 #define VLV_TVIDEO_DIP_GCP(pipe) \ 3561 _PIPE(pipe, VLV_VIDEO_DIP_GDCP_PAYLOAD_A, VLV_VIDEO_DIP_GDCP_PAYLOAD_B) 3562 3563 /* Haswell DIP controls */ 3564 #define HSW_VIDEO_DIP_CTL_A 0x60200 3565 #define HSW_VIDEO_DIP_AVI_DATA_A 0x60220 3566 #define HSW_VIDEO_DIP_VS_DATA_A 0x60260 3567 #define HSW_VIDEO_DIP_SPD_DATA_A 0x602A0 3568 #define HSW_VIDEO_DIP_GMP_DATA_A 0x602E0 3569 #define HSW_VIDEO_DIP_VSC_DATA_A 0x60320 3570 #define HSW_VIDEO_DIP_AVI_ECC_A 0x60240 3571 #define HSW_VIDEO_DIP_VS_ECC_A 0x60280 3572 #define HSW_VIDEO_DIP_SPD_ECC_A 0x602C0 3573 #define HSW_VIDEO_DIP_GMP_ECC_A 0x60300 3574 #define HSW_VIDEO_DIP_VSC_ECC_A 0x60344 3575 #define HSW_VIDEO_DIP_GCP_A 0x60210 3576 3577 #define HSW_VIDEO_DIP_CTL_B 0x61200 3578 #define HSW_VIDEO_DIP_AVI_DATA_B 0x61220 3579 #define HSW_VIDEO_DIP_VS_DATA_B 0x61260 3580 #define HSW_VIDEO_DIP_SPD_DATA_B 0x612A0 3581 #define HSW_VIDEO_DIP_GMP_DATA_B 0x612E0 3582 #define HSW_VIDEO_DIP_VSC_DATA_B 0x61320 3583 #define HSW_VIDEO_DIP_BVI_ECC_B 0x61240 3584 #define HSW_VIDEO_DIP_VS_ECC_B 0x61280 3585 #define HSW_VIDEO_DIP_SPD_ECC_B 0x612C0 3586 #define HSW_VIDEO_DIP_GMP_ECC_B 0x61300 3587 #define HSW_VIDEO_DIP_VSC_ECC_B 0x61344 3588 #define HSW_VIDEO_DIP_GCP_B 0x61210 3589 3590 #define HSW_TVIDEO_DIP_CTL(pipe) \ 3591 _PIPE(pipe, HSW_VIDEO_DIP_CTL_A, HSW_VIDEO_DIP_CTL_B) 3592 #define HSW_TVIDEO_DIP_AVI_DATA(pipe) \ 3593 _PIPE(pipe, HSW_VIDEO_DIP_AVI_DATA_A, HSW_VIDEO_DIP_AVI_DATA_B) 3594 #define HSW_TVIDEO_DIP_SPD_DATA(pipe) \ 3595 _PIPE(pipe, HSW_VIDEO_DIP_SPD_DATA_A, HSW_VIDEO_DIP_SPD_DATA_B) 3596 #define HSW_TVIDEO_DIP_GCP(pipe) \ 3597 _PIPE(pipe, HSW_VIDEO_DIP_GCP_A, HSW_VIDEO_DIP_GCP_B) 3598 3599 #define _TRANS_HTOTAL_B 0xe1000 3600 #define _TRANS_HBLANK_B 0xe1004 3601 #define _TRANS_HSYNC_B 0xe1008 3602 #define _TRANS_VTOTAL_B 0xe100c 3603 #define _TRANS_VBLANK_B 0xe1010 3604 #define _TRANS_VSYNC_B 0xe1014 3605 #define _TRANS_VSYNCSHIFT_B 0xe1028 3606 3607 #define TRANS_HTOTAL(pipe) _PIPE(pipe, _TRANS_HTOTAL_A, _TRANS_HTOTAL_B) 3608 #define TRANS_HBLANK(pipe) _PIPE(pipe, _TRANS_HBLANK_A, _TRANS_HBLANK_B) 3609 #define TRANS_HSYNC(pipe) _PIPE(pipe, _TRANS_HSYNC_A, _TRANS_HSYNC_B) 3610 #define TRANS_VTOTAL(pipe) _PIPE(pipe, _TRANS_VTOTAL_A, _TRANS_VTOTAL_B) 3611 #define TRANS_VBLANK(pipe) _PIPE(pipe, _TRANS_VBLANK_A, _TRANS_VBLANK_B) 3612 #define TRANS_VSYNC(pipe) _PIPE(pipe, _TRANS_VSYNC_A, _TRANS_VSYNC_B) 3613 #define TRANS_VSYNCSHIFT(pipe) _PIPE(pipe, _TRANS_VSYNCSHIFT_A, \ 3614 _TRANS_VSYNCSHIFT_B) 3615 3616 #define _TRANSB_DATA_M1 0xe1030 3617 #define _TRANSB_DATA_N1 0xe1034 3618 #define _TRANSB_DATA_M2 0xe1038 3619 #define _TRANSB_DATA_N2 0xe103c 3620 #define _TRANSB_DP_LINK_M1 0xe1040 3621 #define _TRANSB_DP_LINK_N1 0xe1044 3622 #define _TRANSB_DP_LINK_M2 0xe1048 3623 #define _TRANSB_DP_LINK_N2 0xe104c 3624 3625 #define TRANSDATA_M1(pipe) _PIPE(pipe, _TRANSA_DATA_M1, _TRANSB_DATA_M1) 3626 #define TRANSDATA_N1(pipe) _PIPE(pipe, _TRANSA_DATA_N1, _TRANSB_DATA_N1) 3627 #define TRANSDATA_M2(pipe) _PIPE(pipe, _TRANSA_DATA_M2, _TRANSB_DATA_M2) 3628 #define TRANSDATA_N2(pipe) _PIPE(pipe, _TRANSA_DATA_N2, _TRANSB_DATA_N2) 3629 #define TRANSDPLINK_M1(pipe) _PIPE(pipe, _TRANSA_DP_LINK_M1, _TRANSB_DP_LINK_M1) 3630 #define TRANSDPLINK_N1(pipe) _PIPE(pipe, _TRANSA_DP_LINK_N1, _TRANSB_DP_LINK_N1) 3631 #define TRANSDPLINK_M2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_M2, _TRANSB_DP_LINK_M2) 3632 #define TRANSDPLINK_N2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_N2, _TRANSB_DP_LINK_N2) 3633 3634 #define _TRANSACONF 0xf0008 3635 #define _TRANSBCONF 0xf1008 3636 #define TRANSCONF(plane) _PIPE(plane, _TRANSACONF, _TRANSBCONF) 3637 #define TRANS_DISABLE (0<<31) 3638 #define TRANS_ENABLE (1<<31) 3639 #define TRANS_STATE_MASK (1<<30) 3640 #define TRANS_STATE_DISABLE (0<<30) 3641 #define TRANS_STATE_ENABLE (1<<30) 3642 #define TRANS_FSYNC_DELAY_HB1 (0<<27) 3643 #define TRANS_FSYNC_DELAY_HB2 (1<<27) 3644 #define TRANS_FSYNC_DELAY_HB3 (2<<27) 3645 #define TRANS_FSYNC_DELAY_HB4 (3<<27) 3646 #define TRANS_DP_AUDIO_ONLY (1<<26) 3647 #define TRANS_DP_VIDEO_AUDIO (0<<26) 3648 #define TRANS_INTERLACE_MASK (7<<21) 3649 #define TRANS_PROGRESSIVE (0<<21) 3650 #define TRANS_INTERLACED (3<<21) 3651 #define TRANS_LEGACY_INTERLACED_ILK (2<<21) 3652 #define TRANS_8BPC (0<<5) 3653 #define TRANS_10BPC (1<<5) 3654 #define TRANS_6BPC (2<<5) 3655 #define TRANS_12BPC (3<<5) 3656 3657 #define _TRANSA_CHICKEN2 0xf0064 3658 #define _TRANSB_CHICKEN2 0xf1064 3659 #define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2) 3660 #define TRANS_AUTOTRAIN_GEN_STALL_DIS (1<<31) 3661 3662 #define SOUTH_CHICKEN1 0xc2000 3663 #define FDIA_PHASE_SYNC_SHIFT_OVR 19 3664 #define FDIA_PHASE_SYNC_SHIFT_EN 18 3665 #define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2))) 3666 #define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2))) 3667 #define SOUTH_CHICKEN2 0xc2004 3668 #define DPLS_EDP_PPS_FIX_DIS (1<<0) 3669 3670 #define _FDI_RXA_CHICKEN 0xc200c 3671 #define _FDI_RXB_CHICKEN 0xc2010 3672 #define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1) 3673 #define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0) 3674 #define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN) 3675 3676 #define SOUTH_DSPCLK_GATE_D 0xc2020 3677 #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29) 3678 3679 /* CPU: FDI_TX */ 3680 #define _FDI_TXA_CTL 0x60100 3681 #define _FDI_TXB_CTL 0x61100 3682 #define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL) 3683 #define FDI_TX_DISABLE (0<<31) 3684 #define FDI_TX_ENABLE (1<<31) 3685 #define FDI_LINK_TRAIN_PATTERN_1 (0<<28) 3686 #define FDI_LINK_TRAIN_PATTERN_2 (1<<28) 3687 #define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28) 3688 #define FDI_LINK_TRAIN_NONE (3<<28) 3689 #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25) 3690 #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25) 3691 #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25) 3692 #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25) 3693 #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22) 3694 #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22) 3695 #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22) 3696 #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22) 3697 /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level. 3698 SNB has different settings. */ 3699 /* SNB A-stepping */ 3700 #define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22) 3701 #define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22) 3702 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22) 3703 #define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22) 3704 /* SNB B-stepping */ 3705 #define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22) 3706 #define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22) 3707 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22) 3708 #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22) 3709 #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22) 3710 #define FDI_DP_PORT_WIDTH_X1 (0<<19) 3711 #define FDI_DP_PORT_WIDTH_X2 (1<<19) 3712 #define FDI_DP_PORT_WIDTH_X3 (2<<19) 3713 #define FDI_DP_PORT_WIDTH_X4 (3<<19) 3714 #define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18) 3715 /* Ironlake: hardwired to 1 */ 3716 #define FDI_TX_PLL_ENABLE (1<<14) 3717 3718 /* Ivybridge has different bits for lolz */ 3719 #define FDI_LINK_TRAIN_PATTERN_1_IVB (0<<8) 3720 #define FDI_LINK_TRAIN_PATTERN_2_IVB (1<<8) 3721 #define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2<<8) 3722 #define FDI_LINK_TRAIN_NONE_IVB (3<<8) 3723 3724 /* both Tx and Rx */ 3725 #define FDI_COMPOSITE_SYNC (1<<11) 3726 #define FDI_LINK_TRAIN_AUTO (1<<10) 3727 #define FDI_SCRAMBLING_ENABLE (0<<7) 3728 #define FDI_SCRAMBLING_DISABLE (1<<7) 3729 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */ 3730 #define _FDI_RXA_CTL 0xf000c 3731 #define _FDI_RXB_CTL 0xf100c 3732 #define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL) 3733 #define FDI_RX_ENABLE (1<<31) 3734 /* train, dp width same as FDI_TX */ 3735 #define FDI_FS_ERRC_ENABLE (1<<27) 3736 #define FDI_FE_ERRC_ENABLE (1<<26) 3737 #define FDI_DP_PORT_WIDTH_X8 (7<<19) 3738 #define FDI_8BPC (0<<16) 3739 #define FDI_10BPC (1<<16) 3740 #define FDI_6BPC (2<<16) 3741 #define FDI_12BPC (3<<16) 3742 #define FDI_LINK_REVERSE_OVERWRITE (1<<15) 3743 #define FDI_DMI_LINK_REVERSE_MASK (1<<14) 3744 #define FDI_RX_PLL_ENABLE (1<<13) 3745 #define FDI_FS_ERR_CORRECT_ENABLE (1<<11) 3746 #define FDI_FE_ERR_CORRECT_ENABLE (1<<10) 3747 #define FDI_FS_ERR_REPORT_ENABLE (1<<9) 3748 #define FDI_FE_ERR_REPORT_ENABLE (1<<8) 3749 #define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6) 3750 #define FDI_PCDCLK (1<<4) 3751 /* CPT */ 3752 #define FDI_AUTO_TRAINING (1<<10) 3753 #define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8) 3754 #define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8) 3755 #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8) 3756 #define FDI_LINK_TRAIN_NORMAL_CPT (3<<8) 3757 #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8) 3758 /* LPT */ 3759 #define FDI_PORT_WIDTH_2X_LPT (1<<19) 3760 #define FDI_PORT_WIDTH_1X_LPT (0<<19) 3761 3762 #define _FDI_RXA_MISC 0xf0010 3763 #define _FDI_RXB_MISC 0xf1010 3764 #define _FDI_RXA_TUSIZE1 0xf0030 3765 #define _FDI_RXA_TUSIZE2 0xf0038 3766 #define _FDI_RXB_TUSIZE1 0xf1030 3767 #define _FDI_RXB_TUSIZE2 0xf1038 3768 #define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC) 3769 #define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1) 3770 #define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2) 3771 3772 /* FDI_RX interrupt register format */ 3773 #define FDI_RX_INTER_LANE_ALIGN (1<<10) 3774 #define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */ 3775 #define FDI_RX_BIT_LOCK (1<<8) /* train 1 */ 3776 #define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7) 3777 #define FDI_RX_FS_CODE_ERR (1<<6) 3778 #define FDI_RX_FE_CODE_ERR (1<<5) 3779 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4) 3780 #define FDI_RX_HDCP_LINK_FAIL (1<<3) 3781 #define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2) 3782 #define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1) 3783 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0) 3784 3785 #define _FDI_RXA_IIR 0xf0014 3786 #define _FDI_RXA_IMR 0xf0018 3787 #define _FDI_RXB_IIR 0xf1014 3788 #define _FDI_RXB_IMR 0xf1018 3789 #define FDI_RX_IIR(pipe) _PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR) 3790 #define FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR) 3791 3792 #define FDI_PLL_CTL_1 0xfe000 3793 #define FDI_PLL_CTL_2 0xfe004 3794 3795 /* CRT */ 3796 #define PCH_ADPA 0xe1100 3797 #define ADPA_TRANS_SELECT_MASK (1<<30) 3798 #define ADPA_TRANS_A_SELECT 0 3799 #define ADPA_TRANS_B_SELECT (1<<30) 3800 #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */ 3801 #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24) 3802 #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24) 3803 #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24) 3804 #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24) 3805 #define ADPA_CRT_HOTPLUG_ENABLE (1<<23) 3806 #define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22) 3807 #define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22) 3808 #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21) 3809 #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21) 3810 #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20) 3811 #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20) 3812 #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18) 3813 #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18) 3814 #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18) 3815 #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18) 3816 #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17) 3817 #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17) 3818 #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16) 3819 3820 /* or SDVOB */ 3821 #define VLV_HDMIB 0x61140 3822 #define HDMIB 0xe1140 3823 #define PORT_ENABLE (1U << 31) 3824 #define TRANSCODER(pipe) ((pipe) << 30) 3825 #define TRANSCODER_CPT(pipe) ((pipe) << 29) 3826 #define TRANSCODER_MASK (1 << 30) 3827 #define TRANSCODER_MASK_CPT (3 << 29) 3828 #define COLOR_FORMAT_8bpc (0) 3829 #define COLOR_FORMAT_12bpc (3 << 26) 3830 #define SDVOB_HOTPLUG_ENABLE (1 << 23) 3831 #define SDVO_ENCODING (0) 3832 #define TMDS_ENCODING (2 << 10) 3833 #define NULL_PACKET_VSYNC_ENABLE (1 << 9) 3834 /* CPT */ 3835 #define HDMI_MODE_SELECT (1 << 9) 3836 #define DVI_MODE_SELECT (0) 3837 #define SDVOB_BORDER_ENABLE (1 << 7) 3838 #define AUDIO_ENABLE (1 << 6) 3839 #define VSYNC_ACTIVE_HIGH (1 << 4) 3840 #define HSYNC_ACTIVE_HIGH (1 << 3) 3841 #define PORT_DETECTED (1 << 2) 3842 3843 /* PCH SDVOB multiplex with HDMIB */ 3844 #define PCH_SDVOB HDMIB 3845 3846 #define HDMIC 0xe1150 3847 #define HDMID 0xe1160 3848 3849 #define PCH_LVDS 0xe1180 3850 #define LVDS_DETECTED (1 << 1) 3851 3852 #define BLC_PWM_CPU_CTL2 0x48250 3853 #define PWM_ENABLE (1U << 31) 3854 #define PWM_PIPE_A (0 << 29) 3855 #define PWM_PIPE_B (1 << 29) 3856 #define BLC_PWM_CPU_CTL 0x48254 3857 3858 #define BLC_PWM_PCH_CTL1 0xc8250 3859 #define PWM_PCH_ENABLE (1U << 31) 3860 #define PWM_POLARITY_ACTIVE_LOW (1 << 29) 3861 #define PWM_POLARITY_ACTIVE_HIGH (0 << 29) 3862 #define PWM_POLARITY_ACTIVE_LOW2 (1 << 28) 3863 #define PWM_POLARITY_ACTIVE_HIGH2 (0 << 28) 3864 3865 #define BLC_PWM_PCH_CTL2 0xc8254 3866 3867 #define PCH_PP_STATUS 0xc7200 3868 #define PCH_PP_CONTROL 0xc7204 3869 #define PANEL_UNLOCK_REGS (0xabcd << 16) 3870 #define PANEL_UNLOCK_MASK (0xffff << 16) 3871 #define EDP_FORCE_VDD (1 << 3) 3872 #define EDP_BLC_ENABLE (1 << 2) 3873 #define PANEL_POWER_RESET (1 << 1) 3874 #define PANEL_POWER_OFF (0 << 0) 3875 #define PANEL_POWER_ON (1 << 0) 3876 #define PCH_PP_ON_DELAYS 0xc7208 3877 #define PANEL_PORT_SELECT_MASK (3 << 30) 3878 #define PANEL_PORT_SELECT_LVDS (0 << 30) 3879 #define PANEL_PORT_SELECT_DPA (1 << 30) 3880 #define EDP_PANEL (1 << 30) 3881 #define PANEL_PORT_SELECT_DPC (2U << 30) 3882 #define PANEL_PORT_SELECT_DPD (3U << 30) 3883 #define PANEL_POWER_UP_DELAY_MASK (0x1fff0000) 3884 #define PANEL_POWER_UP_DELAY_SHIFT 16 3885 #define PANEL_LIGHT_ON_DELAY_MASK (0x1fff) 3886 #define PANEL_LIGHT_ON_DELAY_SHIFT 0 3887 3888 #define PCH_PP_OFF_DELAYS 0xc720c 3889 #define PANEL_POWER_DOWN_DELAY_MASK (0x1fff0000) 3890 #define PANEL_POWER_DOWN_DELAY_SHIFT 16 3891 #define PANEL_LIGHT_OFF_DELAY_MASK (0x1fff) 3892 #define PANEL_LIGHT_OFF_DELAY_SHIFT 0 3893 3894 #define PCH_PP_DIVISOR 0xc7210 3895 #define PP_REFERENCE_DIVIDER_MASK (0xffffff00) 3896 #define PP_REFERENCE_DIVIDER_SHIFT 8 3897 #define PANEL_POWER_CYCLE_DELAY_MASK (0x1f) 3898 #define PANEL_POWER_CYCLE_DELAY_SHIFT 0 3899 3900 #define PCH_DP_B 0xe4100 3901 #define PCH_DPB_AUX_CH_CTL 0xe4110 3902 #define PCH_DPB_AUX_CH_DATA1 0xe4114 3903 #define PCH_DPB_AUX_CH_DATA2 0xe4118 3904 #define PCH_DPB_AUX_CH_DATA3 0xe411c 3905 #define PCH_DPB_AUX_CH_DATA4 0xe4120 3906 #define PCH_DPB_AUX_CH_DATA5 0xe4124 3907 3908 #define PCH_DP_C 0xe4200 3909 #define PCH_DPC_AUX_CH_CTL 0xe4210 3910 #define PCH_DPC_AUX_CH_DATA1 0xe4214 3911 #define PCH_DPC_AUX_CH_DATA2 0xe4218 3912 #define PCH_DPC_AUX_CH_DATA3 0xe421c 3913 #define PCH_DPC_AUX_CH_DATA4 0xe4220 3914 #define PCH_DPC_AUX_CH_DATA5 0xe4224 3915 3916 #define PCH_DP_D 0xe4300 3917 #define PCH_DPD_AUX_CH_CTL 0xe4310 3918 #define PCH_DPD_AUX_CH_DATA1 0xe4314 3919 #define PCH_DPD_AUX_CH_DATA2 0xe4318 3920 #define PCH_DPD_AUX_CH_DATA3 0xe431c 3921 #define PCH_DPD_AUX_CH_DATA4 0xe4320 3922 #define PCH_DPD_AUX_CH_DATA5 0xe4324 3923 3924 /* CPT */ 3925 #define PORT_TRANS_A_SEL_CPT 0 3926 #define PORT_TRANS_B_SEL_CPT (1<<29) 3927 #define PORT_TRANS_C_SEL_CPT (2<<29) 3928 #define PORT_TRANS_SEL_MASK (3<<29) 3929 #define PORT_TRANS_SEL_CPT(pipe) ((pipe) << 29) 3930 3931 #define TRANS_DP_CTL_A 0xe0300 3932 #define TRANS_DP_CTL_B 0xe1300 3933 #define TRANS_DP_CTL_C 0xe2300 3934 #define TRANS_DP_CTL(pipe) (TRANS_DP_CTL_A + (pipe) * 0x01000) 3935 #define TRANS_DP_OUTPUT_ENABLE (1<<31) 3936 #define TRANS_DP_PORT_SEL_B (0<<29) 3937 #define TRANS_DP_PORT_SEL_C (1<<29) 3938 #define TRANS_DP_PORT_SEL_D (2<<29) 3939 #define TRANS_DP_PORT_SEL_NONE (3<<29) 3940 #define TRANS_DP_PORT_SEL_MASK (3<<29) 3941 #define TRANS_DP_AUDIO_ONLY (1<<26) 3942 #define TRANS_DP_ENH_FRAMING (1<<18) 3943 #define TRANS_DP_8BPC (0<<9) 3944 #define TRANS_DP_10BPC (1<<9) 3945 #define TRANS_DP_6BPC (2<<9) 3946 #define TRANS_DP_12BPC (3<<9) 3947 #define TRANS_DP_BPC_MASK (3<<9) 3948 #define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4) 3949 #define TRANS_DP_VSYNC_ACTIVE_LOW 0 3950 #define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3) 3951 #define TRANS_DP_HSYNC_ACTIVE_LOW 0 3952 #define TRANS_DP_SYNC_MASK (3<<3) 3953 3954 /* SNB eDP training params */ 3955 /* SNB A-stepping */ 3956 #define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22) 3957 #define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22) 3958 #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22) 3959 #define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22) 3960 /* SNB B-stepping */ 3961 #define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0<<22) 3962 #define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1<<22) 3963 #define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a<<22) 3964 #define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39<<22) 3965 #define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38<<22) 3966 #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22) 3967 3968 /* IVB */ 3969 #define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 <<22) 3970 #define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a <<22) 3971 #define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f <<22) 3972 #define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 <<22) 3973 #define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 <<22) 3974 #define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 <<22) 3975 #define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x33 <<22) 3976 3977 /* legacy values */ 3978 #define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 <<22) 3979 #define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 <<22) 3980 #define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 <<22) 3981 #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 <<22) 3982 #define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 <<22) 3983 3984 #define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f<<22) 3985 3986 #define FORCEWAKE 0xA18C 3987 #define FORCEWAKE_VLV 0x1300b0 3988 #define FORCEWAKE_ACK_VLV 0x1300b4 3989 #define FORCEWAKE_ACK 0x130090 3990 #define FORCEWAKE_MT 0xa188 /* multi-threaded */ 3991 #define FORCEWAKE_MT_ACK 0x130040 3992 #define ECOBUS 0xa180 3993 #define FORCEWAKE_MT_ENABLE (1<<5) 3994 3995 #define GTFIFODBG 0x120000 3996 #define GT_FIFO_CPU_ERROR_MASK 7 3997 #define GT_FIFO_OVFERR (1<<2) 3998 #define GT_FIFO_IAWRERR (1<<1) 3999 #define GT_FIFO_IARDERR (1<<0) 4000 4001 #define GT_FIFO_FREE_ENTRIES 0x120008 4002 #define GT_FIFO_NUM_RESERVED_ENTRIES 20 4003 4004 #define GEN6_UCGCTL1 0x9400 4005 # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5) 4006 # define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7) 4007 4008 #define GEN6_UCGCTL2 0x9404 4009 # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13) 4010 # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12) 4011 # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11) 4012 4013 #define GEN6_RPNSWREQ 0xA008 4014 #define GEN6_TURBO_DISABLE (1<<31) 4015 #define GEN6_FREQUENCY(x) ((x)<<25) 4016 #define GEN6_OFFSET(x) ((x)<<19) 4017 #define GEN6_AGGRESSIVE_TURBO (0<<15) 4018 #define GEN6_RC_VIDEO_FREQ 0xA00C 4019 #define GEN6_RC_CONTROL 0xA090 4020 #define GEN6_RC_CTL_RC6pp_ENABLE (1<<16) 4021 #define GEN6_RC_CTL_RC6p_ENABLE (1<<17) 4022 #define GEN6_RC_CTL_RC6_ENABLE (1<<18) 4023 #define GEN6_RC_CTL_RC1e_ENABLE (1<<20) 4024 #define GEN6_RC_CTL_RC7_ENABLE (1<<22) 4025 #define GEN6_RC_CTL_EI_MODE(x) ((x)<<27) 4026 #define GEN6_RC_CTL_HW_ENABLE (1<<31) 4027 #define GEN6_RP_DOWN_TIMEOUT 0xA010 4028 #define GEN6_RP_INTERRUPT_LIMITS 0xA014 4029 #define GEN6_RPSTAT1 0xA01C 4030 #define GEN6_CAGF_SHIFT 8 4031 #define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT) 4032 #define GEN6_RP_CONTROL 0xA024 4033 #define GEN6_RP_MEDIA_TURBO (1<<11) 4034 #define GEN6_RP_MEDIA_MODE_MASK (3<<9) 4035 #define GEN6_RP_MEDIA_HW_TURBO_MODE (3<<9) 4036 #define GEN6_RP_MEDIA_HW_NORMAL_MODE (2<<9) 4037 #define GEN6_RP_MEDIA_HW_MODE (1<<9) 4038 #define GEN6_RP_MEDIA_SW_MODE (0<<9) 4039 #define GEN6_RP_MEDIA_IS_GFX (1<<8) 4040 #define GEN6_RP_ENABLE (1<<7) 4041 #define GEN6_RP_UP_IDLE_MIN (0x1<<3) 4042 #define GEN6_RP_UP_BUSY_AVG (0x2<<3) 4043 #define GEN6_RP_UP_BUSY_CONT (0x4<<3) 4044 #define GEN6_RP_DOWN_IDLE_CONT (0x1<<0) 4045 #define GEN6_RP_UP_THRESHOLD 0xA02C 4046 #define GEN6_RP_DOWN_THRESHOLD 0xA030 4047 #define GEN6_RP_CUR_UP_EI 0xA050 4048 #define GEN6_CURICONT_MASK 0xffffff 4049 #define GEN6_RP_CUR_UP 0xA054 4050 #define GEN6_CURBSYTAVG_MASK 0xffffff 4051 #define GEN6_RP_PREV_UP 0xA058 4052 #define GEN6_RP_CUR_DOWN_EI 0xA05C 4053 #define GEN6_CURIAVG_MASK 0xffffff 4054 #define GEN6_RP_CUR_DOWN 0xA060 4055 #define GEN6_RP_PREV_DOWN 0xA064 4056 #define GEN6_RP_UP_EI 0xA068 4057 #define GEN6_RP_DOWN_EI 0xA06C 4058 #define GEN6_RP_IDLE_HYSTERSIS 0xA070 4059 #define GEN6_RC_STATE 0xA094 4060 #define GEN6_RC1_WAKE_RATE_LIMIT 0xA098 4061 #define GEN6_RC6_WAKE_RATE_LIMIT 0xA09C 4062 #define GEN6_RC6pp_WAKE_RATE_LIMIT 0xA0A0 4063 #define GEN6_RC_EVALUATION_INTERVAL 0xA0A8 4064 #define GEN6_RC_IDLE_HYSTERSIS 0xA0AC 4065 #define GEN6_RC_SLEEP 0xA0B0 4066 #define GEN6_RC1e_THRESHOLD 0xA0B4 4067 #define GEN6_RC6_THRESHOLD 0xA0B8 4068 #define GEN6_RC6p_THRESHOLD 0xA0BC 4069 #define GEN6_RC6pp_THRESHOLD 0xA0C0 4070 #define GEN6_PMINTRMSK 0xA168 4071 4072 #define GEN6_PMISR 0x44020 4073 #define GEN6_PMIMR 0x44024 /* rps_lock */ 4074 #define GEN6_PMIIR 0x44028 4075 #define GEN6_PMIER 0x4402C 4076 #define GEN6_PM_MBOX_EVENT (1<<25) 4077 #define GEN6_PM_THERMAL_EVENT (1<<24) 4078 #define GEN6_PM_RP_DOWN_TIMEOUT (1<<6) 4079 #define GEN6_PM_RP_UP_THRESHOLD (1<<5) 4080 #define GEN6_PM_RP_DOWN_THRESHOLD (1<<4) 4081 #define GEN6_PM_RP_UP_EI_EXPIRED (1<<2) 4082 #define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1) 4083 #define GEN6_PM_DEFERRED_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \ 4084 GEN6_PM_RP_DOWN_THRESHOLD | \ 4085 GEN6_PM_RP_DOWN_TIMEOUT) 4086 4087 #define GEN6_GT_GFX_RC6_LOCKED 0x138104 4088 #define GEN6_GT_GFX_RC6 0x138108 4089 #define GEN6_GT_GFX_RC6p 0x13810C 4090 #define GEN6_GT_GFX_RC6pp 0x138110 4091 4092 #define GEN6_PCODE_MAILBOX 0x138124 4093 #define GEN6_PCODE_READY (1<<31) 4094 #define GEN6_READ_OC_PARAMS 0xc 4095 #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8 4096 #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9 4097 #define GEN6_PCODE_DATA 0x138128 4098 #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 4099 4100 #define GEN6_GT_CORE_STATUS 0x138060 4101 #define GEN6_CORE_CPD_STATE_MASK (7<<4) 4102 #define GEN6_RCn_MASK 7 4103 #define GEN6_RC0 0 4104 #define GEN6_RC3 2 4105 #define GEN6_RC6 3 4106 #define GEN6_RC7 4 4107 4108 #define G4X_AUD_VID_DID 0x62020 4109 #define INTEL_AUDIO_DEVCL 0x808629FB 4110 #define INTEL_AUDIO_DEVBLC 0x80862801 4111 #define INTEL_AUDIO_DEVCTG 0x80862802 4112 4113 #define G4X_AUD_CNTL_ST 0x620B4 4114 #define G4X_ELDV_DEVCL_DEVBLC (1 << 13) 4115 #define G4X_ELDV_DEVCTG (1 << 14) 4116 #define G4X_ELD_ADDR (0xf << 5) 4117 #define G4X_ELD_ACK (1 << 4) 4118 #define G4X_HDMIW_HDMIEDID 0x6210C 4119 4120 #define IBX_HDMIW_HDMIEDID_A 0xE2050 4121 #define IBX_AUD_CNTL_ST_A 0xE20B4 4122 #define IBX_ELD_BUFFER_SIZE (0x1f << 10) 4123 #define IBX_ELD_ADDRESS (0x1f << 5) 4124 #define IBX_ELD_ACK (1 << 4) 4125 #define IBX_AUD_CNTL_ST2 0xE20C0 4126 #define IBX_ELD_VALIDB (1 << 0) 4127 #define IBX_CP_READYB (1 << 1) 4128 4129 #define CPT_HDMIW_HDMIEDID_A 0xE5050 4130 #define CPT_AUD_CNTL_ST_A 0xE50B4 4131 #define CPT_AUD_CNTRL_ST2 0xE50C0 4132 4133 /* These are the 4 32-bit write offset registers for each stream 4134 * output buffer. It determines the offset from the 4135 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to. 4136 */ 4137 #define GEN7_SO_WRITE_OFFSET(n) (0x5280 + (n) * 4) 4138 4139 #define IBX_AUD_CONFIG_A 0xe2000 4140 #define CPT_AUD_CONFIG_A 0xe5000 4141 #define AUD_CONFIG_N_VALUE_INDEX (1 << 29) 4142 #define AUD_CONFIG_N_PROG_ENABLE (1 << 28) 4143 #define AUD_CONFIG_UPPER_N_SHIFT 20 4144 #define AUD_CONFIG_UPPER_N_VALUE (0xff << 20) 4145 #define AUD_CONFIG_LOWER_N_SHIFT 4 4146 #define AUD_CONFIG_LOWER_N_VALUE (0xfff << 4) 4147 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16 4148 #define AUD_CONFIG_PIXEL_CLOCK_HDMI (0xf << 16) 4149 #define AUD_CONFIG_DISABLE_NCTS (1 << 3) 4150 4151 /* HSW Power Wells */ 4152 #define HSW_PWR_WELL_CTL1 0x45400 /* BIOS */ 4153 #define HSW_PWR_WELL_CTL2 0x45404 /* Driver */ 4154 #define HSW_PWR_WELL_CTL3 0x45408 /* KVMR */ 4155 #define HSW_PWR_WELL_CTL4 0x4540C /* Debug */ 4156 #define HSW_PWR_WELL_ENABLE (1<<31) 4157 #define HSW_PWR_WELL_STATE (1<<30) 4158 #define HSW_PWR_WELL_CTL5 0x45410 4159 #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31) 4160 #define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20) 4161 #define HSW_PWR_WELL_FORCE_ON (1<<19) 4162 #define HSW_PWR_WELL_CTL6 0x45414 4163 4164 /* Per-pipe DDI Function Control */ 4165 #define PIPE_DDI_FUNC_CTL_A 0x60400 4166 #define PIPE_DDI_FUNC_CTL_B 0x61400 4167 #define PIPE_DDI_FUNC_CTL_C 0x62400 4168 #define PIPE_DDI_FUNC_CTL_EDP 0x6F400 4169 #define DDI_FUNC_CTL(pipe) _PIPE(pipe, \ 4170 PIPE_DDI_FUNC_CTL_A, \ 4171 PIPE_DDI_FUNC_CTL_B) 4172 #define PIPE_DDI_FUNC_ENABLE (1<<31) 4173 /* Those bits are ignored by pipe EDP since it can only connect to DDI A */ 4174 #define PIPE_DDI_PORT_MASK (0xf<<28) 4175 #define PIPE_DDI_SELECT_PORT(x) ((x)<<28) 4176 #define PIPE_DDI_MODE_SELECT_HDMI (0<<24) 4177 #define PIPE_DDI_MODE_SELECT_DVI (1<<24) 4178 #define PIPE_DDI_MODE_SELECT_DP_SST (2<<24) 4179 #define PIPE_DDI_MODE_SELECT_DP_MST (3<<24) 4180 #define PIPE_DDI_MODE_SELECT_FDI (4<<24) 4181 #define PIPE_DDI_BPC_8 (0<<20) 4182 #define PIPE_DDI_BPC_10 (1<<20) 4183 #define PIPE_DDI_BPC_6 (2<<20) 4184 #define PIPE_DDI_BPC_12 (3<<20) 4185 #define PIPE_DDI_BFI_ENABLE (1<<4) 4186 #define PIPE_DDI_PORT_WIDTH_X1 (0<<1) 4187 #define PIPE_DDI_PORT_WIDTH_X2 (1<<1) 4188 #define PIPE_DDI_PORT_WIDTH_X4 (3<<1) 4189 4190 /* DisplayPort Transport Control */ 4191 #define DP_TP_CTL_A 0x64040 4192 #define DP_TP_CTL_B 0x64140 4193 #define DP_TP_CTL(port) _PORT(port, \ 4194 DP_TP_CTL_A, \ 4195 DP_TP_CTL_B) 4196 #define DP_TP_CTL_ENABLE (1<<31) 4197 #define DP_TP_CTL_MODE_SST (0<<27) 4198 #define DP_TP_CTL_MODE_MST (1<<27) 4199 #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1<<18) 4200 #define DP_TP_CTL_FDI_AUTOTRAIN (1<<15) 4201 #define DP_TP_CTL_LINK_TRAIN_MASK (7<<8) 4202 #define DP_TP_CTL_LINK_TRAIN_PAT1 (0<<8) 4203 #define DP_TP_CTL_LINK_TRAIN_PAT2 (1<<8) 4204 #define DP_TP_CTL_LINK_TRAIN_NORMAL (3<<8) 4205 4206 /* DisplayPort Transport Status */ 4207 #define DP_TP_STATUS_A 0x64044 4208 #define DP_TP_STATUS_B 0x64144 4209 #define DP_TP_STATUS(port) _PORT(port, \ 4210 DP_TP_STATUS_A, \ 4211 DP_TP_STATUS_B) 4212 #define DP_TP_STATUS_AUTOTRAIN_DONE (1<<12) 4213 4214 /* DDI Buffer Control */ 4215 #define DDI_BUF_CTL_A 0x64000 4216 #define DDI_BUF_CTL_B 0x64100 4217 #define DDI_BUF_CTL(port) _PORT(port, \ 4218 DDI_BUF_CTL_A, \ 4219 DDI_BUF_CTL_B) 4220 #define DDI_BUF_CTL_ENABLE (1<<31) 4221 #define DDI_BUF_EMP_400MV_0DB_HSW (0<<24) /* Sel0 */ 4222 #define DDI_BUF_EMP_400MV_3_5DB_HSW (1<<24) /* Sel1 */ 4223 #define DDI_BUF_EMP_400MV_6DB_HSW (2<<24) /* Sel2 */ 4224 #define DDI_BUF_EMP_400MV_9_5DB_HSW (3<<24) /* Sel3 */ 4225 #define DDI_BUF_EMP_600MV_0DB_HSW (4<<24) /* Sel4 */ 4226 #define DDI_BUF_EMP_600MV_3_5DB_HSW (5<<24) /* Sel5 */ 4227 #define DDI_BUF_EMP_600MV_6DB_HSW (6<<24) /* Sel6 */ 4228 #define DDI_BUF_EMP_800MV_0DB_HSW (7<<24) /* Sel7 */ 4229 #define DDI_BUF_EMP_800MV_3_5DB_HSW (8<<24) /* Sel8 */ 4230 #define DDI_BUF_EMP_MASK (0xf<<24) 4231 #define DDI_BUF_IS_IDLE (1<<7) 4232 #define DDI_PORT_WIDTH_X1 (0<<1) 4233 #define DDI_PORT_WIDTH_X2 (1<<1) 4234 #define DDI_PORT_WIDTH_X4 (3<<1) 4235 #define DDI_INIT_DISPLAY_DETECTED (1<<0) 4236 4237 /* DDI Buffer Translations */ 4238 #define DDI_BUF_TRANS_A 0x64E00 4239 #define DDI_BUF_TRANS_B 0x64E60 4240 #define DDI_BUF_TRANS(port) _PORT(port, \ 4241 DDI_BUF_TRANS_A, \ 4242 DDI_BUF_TRANS_B) 4243 4244 /* Sideband Interface (SBI) is programmed indirectly, via 4245 * SBI_ADDR, which contains the register offset; and SBI_DATA, 4246 * which contains the payload */ 4247 #define SBI_ADDR 0xC6000 4248 #define SBI_DATA 0xC6004 4249 #define SBI_CTL_STAT 0xC6008 4250 #define SBI_CTL_OP_CRRD (0x6<<8) 4251 #define SBI_CTL_OP_CRWR (0x7<<8) 4252 #define SBI_RESPONSE_FAIL (0x1<<1) 4253 #define SBI_RESPONSE_SUCCESS (0x0<<1) 4254 #define SBI_BUSY (0x1<<0) 4255 #define SBI_READY (0x0<<0) 4256 4257 /* SBI offsets */ 4258 #define SBI_SSCDIVINTPHASE6 0x0600 4259 #define SBI_SSCDIVINTPHASE_DIVSEL_MASK ((0x7f)<<1) 4260 #define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x)<<1) 4261 #define SBI_SSCDIVINTPHASE_INCVAL_MASK ((0x7f)<<8) 4262 #define SBI_SSCDIVINTPHASE_INCVAL(x) ((x)<<8) 4263 #define SBI_SSCDIVINTPHASE_DIR(x) ((x)<<15) 4264 #define SBI_SSCDIVINTPHASE_PROPAGATE (1<<0) 4265 #define SBI_SSCCTL 0x020c 4266 #define SBI_SSCCTL6 0x060C 4267 #define SBI_SSCCTL_DISABLE (1<<0) 4268 #define SBI_SSCAUXDIV6 0x0610 4269 #define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x)<<4) 4270 #define SBI_DBUFF0 0x2a00 4271 4272 /* LPT PIXCLK_GATE */ 4273 #define PIXCLK_GATE 0xC6020 4274 #define PIXCLK_GATE_UNGATE 1<<0 4275 #define PIXCLK_GATE_GATE 0<<0 4276 4277 /* SPLL */ 4278 #define SPLL_CTL 0x46020 4279 #define SPLL_PLL_ENABLE (1<<31) 4280 #define SPLL_PLL_SCC (1<<28) 4281 #define SPLL_PLL_NON_SCC (2<<28) 4282 #define SPLL_PLL_FREQ_810MHz (0<<26) 4283 #define SPLL_PLL_FREQ_1350MHz (1<<26) 4284 4285 /* WRPLL */ 4286 #define WRPLL_CTL1 0x46040 4287 #define WRPLL_CTL2 0x46060 4288 #define WRPLL_PLL_ENABLE (1<<31) 4289 #define WRPLL_PLL_SELECT_SSC (0x01<<28) 4290 #define WRPLL_PLL_SELECT_NON_SCC (0x02<<28) 4291 #define WRPLL_PLL_SELECT_LCPLL_2700 (0x03<<28) 4292 /* WRPLL divider programming */ 4293 #define WRPLL_DIVIDER_REFERENCE(x) ((x)<<0) 4294 #define WRPLL_DIVIDER_POST(x) ((x)<<8) 4295 #define WRPLL_DIVIDER_FEEDBACK(x) ((x)<<16) 4296 4297 /* Port clock selection */ 4298 #define PORT_CLK_SEL_A 0x46100 4299 #define PORT_CLK_SEL_B 0x46104 4300 #define PORT_CLK_SEL(port) _PORT(port, \ 4301 PORT_CLK_SEL_A, \ 4302 PORT_CLK_SEL_B) 4303 #define PORT_CLK_SEL_LCPLL_2700 (0<<29) 4304 #define PORT_CLK_SEL_LCPLL_1350 (1<<29) 4305 #define PORT_CLK_SEL_LCPLL_810 (2<<29) 4306 #define PORT_CLK_SEL_SPLL (3<<29) 4307 #define PORT_CLK_SEL_WRPLL1 (4<<29) 4308 #define PORT_CLK_SEL_WRPLL2 (5<<29) 4309 4310 /* Pipe clock selection */ 4311 #define PIPE_CLK_SEL_A 0x46140 4312 #define PIPE_CLK_SEL_B 0x46144 4313 #define PIPE_CLK_SEL(pipe) _PIPE(pipe, \ 4314 PIPE_CLK_SEL_A, \ 4315 PIPE_CLK_SEL_B) 4316 /* For each pipe, we need to select the corresponding port clock */ 4317 #define PIPE_CLK_SEL_DISABLED (0x0<<29) 4318 #define PIPE_CLK_SEL_PORT(x) ((x+1)<<29) 4319 4320 /* LCPLL Control */ 4321 #define LCPLL_CTL 0x130040 4322 #define LCPLL_PLL_DISABLE (1<<31) 4323 #define LCPLL_PLL_LOCK (1<<30) 4324 #define LCPLL_CD_CLOCK_DISABLE (1<<25) 4325 #define LCPLL_CD2X_CLOCK_DISABLE (1<<23) 4326 4327 /* Pipe WM_LINETIME - watermark line time */ 4328 #define PIPE_WM_LINETIME_A 0x45270 4329 #define PIPE_WM_LINETIME_B 0x45274 4330 #define PIPE_WM_LINETIME(pipe) _PIPE(pipe, \ 4331 PIPE_WM_LINETIME_A, \ 4332 PIPE_WM_LINETIME_A) 4333 #define PIPE_WM_LINETIME_MASK (0x1ff) 4334 #define PIPE_WM_LINETIME_TIME(x) ((x)) 4335 #define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff<<16) 4336 #define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x)<<16) 4337 4338 /* SFUSE_STRAP */ 4339 #define SFUSE_STRAP 0xc2014 4340 #define SFUSE_STRAP_DDIB_DETECTED (1<<2) 4341 #define SFUSE_STRAP_DDIC_DETECTED (1<<1) 4342 #define SFUSE_STRAP_DDID_DETECTED (1<<0) 4343 4344 #endif /* _I915_REG_H_ */ 4345