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Searched refs:PIPECONF (Results 1 – 7 of 7) sorted by relevance

/trueos/sys/dev/drm2/i915/
HDintel_display.c879 int reg = PIPECONF(pipe); in intel_wait_for_pipe_off()
1090 reg = PIPECONF(pipe); in assert_pipe()
1536 pipeconf_val = I915_READ(PIPECONF(pipe)); in intel_enable_transcoder()
1622 reg = PIPECONF(pipe); in intel_enable_pipe()
1659 reg = PIPECONF(pipe); in intel_disable_pipe()
2574 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; in ironlake_fdi_pll_enable()
2631 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; in ironlake_fdi_disable()
2665 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; in ironlake_fdi_disable()
2889 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5; in ironlake_pch_enable()
4081 pipeconf = I915_READ(PIPECONF(pipe)); in i9xx_crtc_mode_set()
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HDintel_crt.c354 pipeconf_reg = PIPECONF(pipe); in intel_crt_load_detect()
HDintel_sprite.c429 if (!(I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE)) in intel_update_plane()
HDintel_tv.c1034 int pipeconf_reg = PIPECONF(pipe); in intel_tv_mode_set()
HDintel_overlay.c913 … (I915_READ(PIPECONF(crtc->pipe)) & (PIPECONF_DOUBLE_WIDE | PIPECONF_ENABLE)) != PIPECONF_ENABLE) in check_overlay_possible_on_crtc()
HDi915_reg.h2603 #define PIPECONF(pipe) _PIPE(pipe, _PIPEACONF, _PIPEBCONF) macro
HDi915_irq.c129 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE; in i915_pipe_enabled()