Searched refs:Orders (Results 1 – 6 of 6) sorted by relevance
| /trueos/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| HD | ScheduleDAGSDNodes.cpp | 701 SmallVectorImpl<std::pair<unsigned, MachineInstr*> > &Orders, in ProcessSDDbgValues()
718 Orders.push_back(std::make_pair(DVOrder, DbgMI)); in ProcessSDDbgValues()
732 SmallVectorImpl<std::pair<unsigned, MachineInstr*> > &Orders, in ProcessSourceNode()
738 ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, 0); in ProcessSourceNode()
748 Orders.push_back(std::make_pair(Order, (MachineInstr*)0)); in ProcessSourceNode()
752 Orders.push_back(std::make_pair(Order, prior(Emitter.getInsertPos()))); in ProcessSourceNode()
753 ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, Order); in ProcessSourceNode()
801 SmallVector<std::pair<unsigned, MachineInstr*>, 32> Orders; in EmitSchedule() local
841 ProcessSourceNode(N, DAG, Emitter, VRBaseMap, Orders, Seen); in EmitSchedule()
848 ProcessSourceNode(SU->getNode(), DAG, Emitter, VRBaseMap, Orders, in EmitSchedule()
[all …]
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| /trueos/contrib/llvm/utils/TableGen/ |
| HD | CodeGenRegisters.h | 244 std::vector<SmallVector<Record*, 16> > Orders; variable
351 return Orders[No];
355 unsigned getNumOrders() const { return Orders.size(); } in getNumOrders()
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| HD | CodeGenRegisters.cpp | 686 Orders.resize(1 + AltOrders->size()); in CodeGenRegisterClass()
690 Orders[0].push_back((*Elements)[i]); in CodeGenRegisterClass()
700 Orders[1 + i].append(Order.begin(), Order.end()); in CodeGenRegisterClass()
759 Orders.resize(Super.Orders.size()); in inheritProperties()
760 for (unsigned i = 0, ie = Super.Orders.size(); i != ie; ++i) in inheritProperties()
761 for (unsigned j = 0, je = Super.Orders[i].size(); j != je; ++j) in inheritProperties()
762 if (contains(RegBank.getReg(Super.Orders[i][j]))) in inheritProperties()
763 Orders[i].push_back(Super.Orders[i][j]); in inheritProperties()
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| /trueos/contrib/gcc/doc/ |
| HD | gcc.texi | 89 @tab Orders: @tex sales@@gnu.org @end tex
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| /trueos/crypto/openssl/doc/crypto/ |
| HD | lhash.pod | 94 /* Orders 'arg1' and 'arg2' (implemented elsewhere) */
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| /trueos/contrib/llvm/tools/clang/lib/CodeGen/ |
| HD | CGBuiltin.cpp | 1125 llvm::AtomicOrdering Orders[5] = { in EmitBuiltinExpr() local
1139 Ptr, NewVal, Orders[i]); in EmitBuiltinExpr()
1192 llvm::AtomicOrdering Orders[3] = { in EmitBuiltinExpr() local
1203 Store->setOrdering(Orders[i]); in EmitBuiltinExpr()
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