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Searched refs:Op2 (Results 1 – 25 of 46) sorted by relevance

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/trueos/contrib/llvm/lib/Target/XCore/Disassembler/
HDXCoreDisassembler.cpp252 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) { in Decode2OpInstruction() argument
265 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 0, 2); in Decode2OpInstruction()
270 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2, in Decode3OpInstruction() argument
280 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 2, 2); in Decode3OpInstruction()
358 unsigned Op1, Op2; in Decode2RInstruction() local
359 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); in Decode2RInstruction()
364 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); in Decode2RInstruction()
371 unsigned Op1, Op2; in Decode2RImmInstruction() local
372 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); in Decode2RImmInstruction()
377 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); in Decode2RImmInstruction()
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/trueos/sys/contrib/dev/acpica/compiler/
HDasltree.c1182 ACPI_PARSE_OBJECT *Op2) in TrLinkPeerNode() argument
1190 Op2, Op2 ? UtGetOpName(Op2->Asl.ParseOpcode) : NULL); in TrLinkPeerNode()
1193 if ((!Op1) && (!Op2)) in TrLinkPeerNode()
1201 if (!Op2) in TrLinkPeerNode()
1208 return (Op2); in TrLinkPeerNode()
1211 if (Op1 == Op2) in TrLinkPeerNode()
1221 Op1->Asl.Parent = Op2->Asl.Parent; in TrLinkPeerNode()
1234 Next->Asl.Next = Op2; in TrLinkPeerNode()
1319 ACPI_PARSE_OBJECT *Op2) in TrLinkChildNode() argument
1327 Op2, Op2 ? UtGetOpName(Op2->Asl.ParseOpcode): NULL); in TrLinkChildNode()
[all …]
HDaslcompiler.h751 ACPI_PARSE_OBJECT *Op2);
756 ACPI_PARSE_OBJECT *Op2);
/trueos/contrib/llvm/include/llvm/Target/
HDTargetSelectionDAGInfo.h59 SDValue Op1, SDValue Op2, in EmitTargetCodeForMemcpy() argument
76 SDValue Op1, SDValue Op2, in EmitTargetCodeForMemmove() argument
92 SDValue Op1, SDValue Op2, in EmitTargetCodeForMemset() argument
106 SDValue Op1, SDValue Op2, in EmitTargetCodeForMemcmp() argument
147 SDValue Op1, SDValue Op2, in EmitTargetCodeForStrcmp() argument
/trueos/contrib/llvm/include/llvm/CodeGen/
HDSelectionDAG.h576 SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2,
582 Ops.push_back(Op2);
831 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2);
832 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2,
834 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2,
836 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2,
848 SDValue Op1, SDValue Op2);
850 SDValue Op1, SDValue Op2, SDValue Op3);
864 EVT VT2, SDValue Op1, SDValue Op2);
866 EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3);
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HDISDOpcodes.h789 CondCode getSetCCOrOperation(CondCode Op1, CondCode Op2, bool isInteger);
795 CondCode getSetCCAndOperation(CondCode Op1, CondCode Op2, bool isInteger);
HDFastISel.h278 unsigned Op2, bool Op2IsKill);
HDSelectionDAGNodes.h746 const SDValue &Op2) {
752 Ops[2].setInitial(Op2);
760 const SDValue &Op2, const SDValue &Op3) {
766 Ops[2].setInitial(Op2);
/trueos/contrib/llvm/lib/CodeGen/SelectionDAG/
HDLegalizeVectorOps.cpp587 SDValue Op2 = Op.getOperand(2); in ExpandSELECT() local
590 && Op1.getValueType() == Op2.getValueType() && "Invalid type"); in ExpandSELECT()
623 Op2 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op2); in ExpandSELECT()
630 Op2 = DAG.getNode(ISD::AND, DL, MaskTy, Op2, NotMask); in ExpandSELECT()
631 SDValue Val = DAG.getNode(ISD::OR, DL, MaskTy, Op1, Op2); in ExpandSELECT()
662 SDValue Op2 = Op.getOperand(2); in ExpandVSELECT() local
690 Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2); in ExpandVSELECT()
697 Op2 = DAG.getNode(ISD::AND, DL, VT, Op2, NotMask); in ExpandVSELECT()
698 SDValue Val = DAG.getNode(ISD::OR, DL, VT, Op1, Op2); in ExpandVSELECT()
HDSelectionDAG.cpp271 ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2, in getSetCCOrOperation() argument
273 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) in getSetCCOrOperation()
277 unsigned Op = Op1 | Op2; // Combine all of the condition bits. in getSetCCOrOperation()
295 ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2, in getSetCCAndOperation() argument
297 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) in getSetCCAndOperation()
302 ISD::CondCode Result = ISD::CondCode(Op1 & Op2); in getSetCCAndOperation()
759 SDValue Op1, SDValue Op2, in FindModifiedNodeSlot() argument
764 SDValue Ops[] = { Op1, Op2 }; in FindModifiedNodeSlot()
5098 SDNode *SelectionDAG::UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2) { in UpdateNodeOperands() argument
5102 if (Op1 == N->getOperand(0) && Op2 == N->getOperand(1)) in UpdateNodeOperands()
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HDSelectionDAGBuilder.cpp2733 SDValue Op2 = getValue(I.getOperand(1)); in visitFSub() local
2735 Op2.getValueType(), Op2)); in visitFSub()
2744 SDValue Op2 = getValue(I.getOperand(1)); in visitBinary() local
2746 Op1.getValueType(), Op1, Op2)); in visitBinary()
2751 SDValue Op2 = getValue(I.getOperand(1)); in visitShift() local
2753 EVT ShiftTy = TM.getTargetLowering()->getShiftAmountTy(Op2.getValueType()); in visitShift()
2756 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) { in visitShift()
2758 unsigned Op2Size = Op2.getValueType().getSizeInBits(); in visitShift()
2763 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2); in visitShift()
2769 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits())) in visitShift()
[all …]
HDLegalizeIntegerTypes.cpp181 SDValue Op2 = GetPromotedInteger(N->getOperand(2)); in PromoteIntRes_Atomic1() local
185 Op2, N->getMemOperand(), N->getOrdering(), in PromoteIntRes_Atomic1()
194 SDValue Op2 = GetPromotedInteger(N->getOperand(2)); in PromoteIntRes_Atomic2() local
198 Op2, Op3, N->getMemOperand(), N->getOrdering(), in PromoteIntRes_Atomic2()
863 SDValue Op2 = GetPromotedInteger(N->getOperand(2)); in PromoteIntOp_ATOMIC_STORE() local
865 N->getChain(), N->getBasePtr(), Op2, N->getMemOperand(), in PromoteIntOp_ATOMIC_STORE()
1419 unsigned Op1, Op2; in ExpandShiftWithKnownAmountBit() local
1422 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break; in ExpandShiftWithKnownAmountBit()
1424 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break; in ExpandShiftWithKnownAmountBit()
1433 SDValue Sh1 = DAG.getNode(Op2, dl, NVT, InL, DAG.getConstant(1, ShTy)); in ExpandShiftWithKnownAmountBit()
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/trueos/contrib/llvm/lib/Target/X86/AsmParser/
HDX86AsmParser.cpp152 ICToken Op2 = OperandStack.pop_back_val(); in execute() local
159 Val = Op1.second + Op2.second; in execute()
163 Val = Op1.second - Op2.second; in execute()
167 assert (Op1.first == IC_IMM && Op2.first == IC_IMM && in execute()
169 Val = Op1.second * Op2.second; in execute()
173 assert (Op1.first == IC_IMM && Op2.first == IC_IMM && in execute()
175 assert (Op2.second != 0 && "Division by zero!"); in execute()
176 Val = Op1.second / Op2.second; in execute()
2129 X86Operand &Op2 = *(X86Operand*)Operands.begin()[2]; in ParseInstruction() local
2130 if (Op.isReg() && Op.getReg() == X86::DX && isDstOp(Op2)) { in ParseInstruction()
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/trueos/contrib/llvm/lib/Analysis/
HDConstantFolding.cpp1541 if (ConstantFP *Op2 = dyn_cast<ConstantFP>(Operands[1])) { in ConstantFoldCall() local
1542 if (Op2->getType() != Op1->getType()) in ConstantFoldCall()
1547 Op2V = Op2->getValueAPF().convertToFloat(); in ConstantFoldCall()
1549 Op2V = Op2->getValueAPF().convertToDouble(); in ConstantFoldCall()
1552 APFloat APF = Op2->getValueAPF(); in ConstantFoldCall()
1586 if (ConstantInt *Op2 = dyn_cast<ConstantInt>(Operands[1])) { in ConstantFoldCall() local
1600 Res = Op1->getValue().sadd_ov(Op2->getValue(), Overflow); in ConstantFoldCall()
1603 Res = Op1->getValue().uadd_ov(Op2->getValue(), Overflow); in ConstantFoldCall()
1606 Res = Op1->getValue().ssub_ov(Op2->getValue(), Overflow); in ConstantFoldCall()
1609 Res = Op1->getValue().usub_ov(Op2->getValue(), Overflow); in ConstantFoldCall()
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/trueos/contrib/llvm/lib/Transforms/Scalar/
HDLoopRerollPass.cpp958 Value *Op2 = J2->getOperand(j); in reroll() local
964 if (Instruction *Op2I = dyn_cast<Instruction>(Op2)) in reroll()
968 DenseMap<Value *, Value *>::iterator BMI = BaseMap.find(Op2); in reroll()
970 Op2 = BMI->second; in reroll()
972 (Instruction*) Op2) != Roots[i].end()) in reroll()
973 Op2 = IV; in reroll()
975 if (J1->getOperand(Swapped ? unsigned(!j) : j) != Op2) { in reroll()
982 J1->getOperand(!j) == Op2) { in reroll()
/trueos/contrib/llvm/lib/Target/AArch64/Utils/
HDAArch64BaseInfo.cpp786 uint32_t Op0 = 3, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0; in fromString() local
791 Ops[4].getAsInteger(10, Op2); in fromString()
792 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2; in fromString()
818 uint32_t Op2 = Bits & 0x7; in toString() local
831 + "_c" + utostr(CRm) + "_" + utostr(Op2); in toString()
/trueos/contrib/llvm/include/llvm/Analysis/
HDScalarEvolution.h589 const SCEV *getAddExpr(const SCEV *Op0, const SCEV *Op1, const SCEV *Op2,
594 Ops.push_back(Op2);
607 const SCEV *getMulExpr(const SCEV *Op0, const SCEV *Op1, const SCEV *Op2,
612 Ops.push_back(Op2);
/trueos/contrib/llvm/lib/Target/ARM/
HDARMSelectionDAGInfo.h60 SDValue Op1, SDValue Op2,
HDARMFastISel.cpp118 unsigned Op2, bool Op2IsKill);
375 unsigned Op2, bool Op2IsKill) { in FastEmitInst_rrr() argument
383 Op2 = constrainOperandRegClass(II, Op1, 3); in FastEmitInst_rrr()
389 .addReg(Op2, Op2IsKill * RegState::Kill)); in FastEmitInst_rrr()
394 .addReg(Op2, Op2IsKill * RegState::Kill)); in FastEmitInst_rrr()
1900 unsigned Op2 = getRegForValue(I->getOperand(1)); in SelectBinaryFPOp() local
1901 if (Op2 == 0) return false; in SelectBinaryFPOp()
1906 .addReg(Op1).addReg(Op2)); in SelectBinaryFPOp()
/trueos/contrib/llvm/lib/Target/Hexagon/
HDHexagonPeephole.cpp299 MachineOperand Op2 = MI->getOperand(S2); in runOnMachineFunction() local
300 ChangeOpInto(MI->getOperand(S1), Op2); in runOnMachineFunction()
HDHexagonHardwareLoops.cpp524 const MachineOperand &Op2 = CondI->getOperand(2); in getLoopTripCount() local
528 if (Op2.isImm() || Op1.getReg() == IVReg) in getLoopTripCount()
529 EndValue = &Op2; in getLoopTripCount()
/trueos/contrib/llvm/lib/AsmParser/
HDLLParser.cpp3422 BasicBlock *Op1, *Op2; in ParseBr() local
3436 ParseTypeAndBasicBlock(Op2, Loc2, PFS)) in ParseBr()
3439 Inst = BranchInst::Create(Op1, Op2, Op0); in ParseBr()
3757 Value *Op0, *Op1, *Op2; in ParseSelect() local
3762 ParseTypeAndValue(Op2, PFS)) in ParseSelect()
3765 if (const char *Reason = SelectInst::areInvalidOperands(Op0, Op1, Op2)) in ParseSelect()
3768 Inst = SelectInst::Create(Op0, Op1, Op2); in ParseSelect()
3811 Value *Op0, *Op1, *Op2; in ParseInsertElement() local
3816 ParseTypeAndValue(Op2, PFS)) in ParseInsertElement()
3819 if (!InsertElementInst::isValidOperands(Op0, Op1, Op2)) in ParseInsertElement()
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/trueos/contrib/llvm/lib/Target/R600/
HDR600InstrFormats.td24 bit Op2 = 0;
50 let TSFlags{11} = Op2;
/trueos/contrib/llvm/lib/Transforms/InstCombine/
HDInstCombineCompares.cpp2510 Value *Op1 = 0, *Op2 = 0; in visitICmpInst() local
2514 Op2 = ConstantExpr::getICmp(I.getPredicate(), C, RHSC); in visitICmpInst()
2522 if ((Op1 && Op2) || (LHSI->hasOneUse() && (Op1 || Op2))) { in visitICmpInst()
2526 if (!Op2) in visitICmpInst()
2527 Op2 = Builder->CreateICmp(I.getPredicate(), LHSI->getOperand(2), in visitICmpInst()
2529 return SelectInst::Create(LHSI->getOperand(0), Op1, Op2); in visitICmpInst()
3320 Value *Op1 = 0, *Op2 = 0; in visitFCmpInst() local
3326 Op2 = Builder->CreateFCmp(I.getPredicate(), in visitFCmpInst()
3330 Op2 = ConstantExpr::getCompare(I.getPredicate(), C, RHSC); in visitFCmpInst()
3338 return SelectInst::Create(LHSI->getOperand(0), Op1, Op2); in visitFCmpInst()
/trueos/contrib/llvm/include/llvm/Support/
HDPatternMatch.h1101 m_Intrinsic(const T0 &Op0, const T1 &Op1, const T2 &Op2) {
1102 return m_CombineAnd(m_Intrinsic<IntrID>(Op0, Op1), m_Argument<2>(Op2));
1107 m_Intrinsic(const T0 &Op0, const T1 &Op1, const T2 &Op2, const T3 &Op3) {
1108 return m_CombineAnd(m_Intrinsic<IntrID>(Op0, Op1, Op2), m_Argument<3>(Op3));

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