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Searched refs:NewVT (Results 1 – 10 of 10) sorted by relevance

/trueos/contrib/llvm/lib/CodeGen/SelectionDAG/
HDLegalizeVectorTypes.cpp152 EVT NewVT = N->getValueType(0).getVectorElementType(); in ScalarizeVecRes_BITCAST() local
154 NewVT, N->getOperand(0)); in ScalarizeVecRes_BITCAST()
168 EVT NewVT = N->getValueType(0).getVectorElementType(); in ScalarizeVecRes_CONVERT_RNDSAT() local
170 return DAG.getConvertRndSat(NewVT, SDLoc(N), in ScalarizeVecRes_CONVERT_RNDSAT()
171 Op0, DAG.getValueType(NewVT), in ScalarizeVecRes_CONVERT_RNDSAT()
185 EVT NewVT = N->getValueType(0).getVectorElementType(); in ScalarizeVecRes_FP_ROUND() local
188 NewVT, Op, N->getOperand(1)); in ScalarizeVecRes_FP_ROUND()
1006 EVT NewVT = Inputs[0].getValueType(); in SplitVecRes_VECTOR_SHUFFLE() local
1007 unsigned NewElts = NewVT.getVectorNumElements(); in SplitVecRes_VECTOR_SHUFFLE()
1064 EVT EltVT = NewVT.getVectorElementType(); in SplitVecRes_VECTOR_SHUFFLE()
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HDLegalizeTypesGeneric.cpp210 EVT NewVT = TLI.getTypeToTransformTo(*DAG.getContext(), OldVT); in ExpandRes_EXTRACT_VECTOR_ELT() local
223 NewVT, 2*OldElts), in ExpandRes_EXTRACT_VECTOR_ELT()
230 Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, Idx); in ExpandRes_EXTRACT_VECTOR_ELT()
234 Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, Idx); in ExpandRes_EXTRACT_VECTOR_ELT()
368 EVT NewVT = TLI.getTypeToTransformTo(*DAG.getContext(), OldVT); in ExpandOp_BUILD_VECTOR() local
390 NewVT, NewElts.size()), in ExpandOp_BUILD_VECTOR()
HDDAGCombiner.cpp2172 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); in visitMULHS() local
2173 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { in visitMULHS()
2174 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0); in visitMULHS()
2175 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1); in visitMULHS()
2176 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); in visitMULHS()
2177 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, in visitMULHS()
2208 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); in visitMULHU() local
2209 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { in visitMULHU()
2210 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0); in visitMULHU()
2211 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1); in visitMULHU()
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HDSelectionDAG.cpp3646 EVT NewVT = VT; in FindOptimalMemOpLowering() local
3651 NewVT = (VT.getSizeInBits() > 64) ? MVT::i64 : MVT::i32; in FindOptimalMemOpLowering()
3652 if (TLI.isOperationLegalOrCustom(ISD::STORE, NewVT) && in FindOptimalMemOpLowering()
3653 TLI.isSafeMemOpType(NewVT.getSimpleVT())) in FindOptimalMemOpLowering()
3655 else if (NewVT == MVT::i64 && in FindOptimalMemOpLowering()
3659 NewVT = MVT::f64; in FindOptimalMemOpLowering()
3666 NewVT = (MVT::SimpleValueType)(NewVT.getSimpleVT().SimpleTy - 1); in FindOptimalMemOpLowering()
3667 if (NewVT == MVT::i8) in FindOptimalMemOpLowering()
3669 } while (!TLI.isSafeMemOpType(NewVT.getSimpleVT())); in FindOptimalMemOpLowering()
3671 NewVTSize = NewVT.getSizeInBits() / 8; in FindOptimalMemOpLowering()
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HDLegalizeDAG.cpp3110 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), NewEltVT, in ExpandNode() local
3112 assert(NewVT.bitsEq(VT)); in ExpandNode()
3115 Op0 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op0); in ExpandNode()
3116 Op1 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op1); in ExpandNode()
3119 unsigned int factor = NewVT.getVectorNumElements()/VT.getVectorNumElements(); in ExpandNode()
3135 VT = NewVT; in ExpandNode()
/trueos/contrib/llvm/lib/CodeGen/
HDTargetLoweringBase.cpp865 MVT NewVT = MVT::getVectorVT(EltTy, NumElts); in getVectorTypeBreakdownMVT() local
866 if (!TLI->isTypeLegal(NewVT)) in getVectorTypeBreakdownMVT()
867 NewVT = EltTy; in getVectorTypeBreakdownMVT()
868 IntermediateVT = NewVT; in getVectorTypeBreakdownMVT()
870 unsigned NewVTSize = NewVT.getSizeInBits(); in getVectorTypeBreakdownMVT()
876 MVT DestVT = TLI->getRegisterType(NewVT); in getVectorTypeBreakdownMVT()
878 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. in getVectorTypeBreakdownMVT()
1158 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts); in getVectorTypeBreakdown() local
1159 if (!isTypeLegal(NewVT)) in getVectorTypeBreakdown()
1160 NewVT = EltTy; in getVectorTypeBreakdown()
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/trueos/contrib/llvm/lib/Transforms/InstCombine/
HDInstCombineCalls.cpp668 VectorType *NewVT = cast<VectorType>(II->getType()); in visitCallInst() local
669 unsigned NewWidth = NewVT->getElementType()->getIntegerBitWidth(); in visitCallInst()
682 ConstantInt::get(NewVT->getElementType(), CV0E * CV1E)); in visitCallInst()
/trueos/contrib/llvm/lib/Target/X86/
HDX86ISelLowering.cpp6674 MVT NewVT; in RewriteAsNarrowerShuffle() local
6678 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break; in RewriteAsNarrowerShuffle()
6679 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break; in RewriteAsNarrowerShuffle()
6680 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break; in RewriteAsNarrowerShuffle()
6681 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break; in RewriteAsNarrowerShuffle()
6682 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break; in RewriteAsNarrowerShuffle()
6683 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break; in RewriteAsNarrowerShuffle()
6701 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0)); in RewriteAsNarrowerShuffle()
6702 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1)); in RewriteAsNarrowerShuffle()
6703 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]); in RewriteAsNarrowerShuffle()
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/trueos/contrib/llvm/lib/Target/R600/
HDR600ISelLowering.cpp1234 EVT NewVT = MVT::v4i32; in LowerLOAD() local
1237 NewVT = VT; in LowerLOAD()
1240 Result = DAG.getNode(ISD::BUILD_VECTOR, DL, NewVT, Slots, NumElements); in LowerLOAD()
/trueos/contrib/llvm/lib/Target/ARM/
HDARMISelLowering.cpp5599 EVT NewVT = getExtensionTo64Bits(OrigTy); in AddRequiredExtensionForVMULL() local
5601 return DAG.getNode(ExtOpcode, SDLoc(N), NewVT, N); in AddRequiredExtensionForVMULL()