| /trueos/contrib/llvm/lib/Target/ARM/ |
| HD | ARMLoadStoreOptimizer.cpp | 94 const MemOpQueue &MemOps, unsigned DefReg,
104 MemOpQueue &MemOps,
120 unsigned Scratch, MemOpQueue &MemOps,
123 void AdvanceRS(MachineBasicBlock &MBB, MemOpQueue &MemOps);
378 SmallVectorImpl<MachineOperand *> &UsesOfImpDefs, const MemOpQueue &MemOps, in findUsesOfImpDef() argument
387 for (unsigned i = 0; i < MemOps.size(); ++i) { in findUsesOfImpDef()
388 MachineInstr &MI = *MemOps[i].MBBI; in findUsesOfImpDef()
389 unsigned MIPosition = MemOps[i].Position; in findUsesOfImpDef()
526 unsigned Scratch, MemOpQueue &MemOps, in MergeLDR_STR() argument
529 int Offset = MemOps[SIndex].Offset; in MergeLDR_STR()
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| HD | ARMISelLowering.cpp | 2901 SmallVector<SDValue, 4> MemOps; in StoreByValRegs() local
2916 MemOps.push_back(Store); in StoreByValRegs()
2923 if (!MemOps.empty()) in StoreByValRegs()
2925 &MemOps[0], MemOps.size()); in StoreByValRegs()
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| /trueos/contrib/llvm/lib/Target/XCore/ |
| HD | XCoreISelLowering.cpp | 1126 SmallVector<SDValue, 4> MemOps; in LowerCCCArguments() local
1207 MemOps.push_back(Store); in LowerCCCArguments()
1236 MemOps.push_back(DAG.getMemcpy(Chain, dl, FIN, ArgDI->SDV, in LowerCCCArguments()
1247 if (!MemOps.empty()) { in LowerCCCArguments()
1248 MemOps.push_back(Chain); in LowerCCCArguments()
1249 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &MemOps[0], in LowerCCCArguments()
1250 MemOps.size()); in LowerCCCArguments()
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| /trueos/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| HD | SelectionDAG.cpp | 3597 static bool FindOptimalMemOpLowering(std::vector<EVT> &MemOps, in FindOptimalMemOpLowering() argument
3691 MemOps.push_back(VT); in FindOptimalMemOpLowering()
3714 std::vector<EVT> MemOps; in getMemcpyLoadsAndStores() local
3732 if (!FindOptimalMemOpLowering(MemOps, Limit, Size, in getMemcpyLoadsAndStores()
3739 Type *Ty = MemOps[0].getTypeForEVT(*DAG.getContext()); in getMemcpyLoadsAndStores()
3759 unsigned NumMemOps = MemOps.size(); in getMemcpyLoadsAndStores()
3762 EVT VT = MemOps[i]; in getMemcpyLoadsAndStores()
3830 std::vector<EVT> MemOps; in getMemmoveLoadsAndStores() local
3844 if (!FindOptimalMemOpLowering(MemOps, Limit, Size, in getMemmoveLoadsAndStores()
3850 Type *Ty = MemOps[0].getTypeForEVT(*DAG.getContext()); in getMemmoveLoadsAndStores()
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| /trueos/contrib/llvm/lib/Target/AArch64/ |
| HD | AArch64ISelLowering.cpp | 1064 SmallVector<SDValue, 8> MemOps; in SaveVarArgRegisters() local
1084 MemOps.push_back(Store); in SaveVarArgRegisters()
1108 MemOps.push_back(Store); in SaveVarArgRegisters()
1123 if (!MemOps.empty()) { in SaveVarArgRegisters()
1124 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, &MemOps[0], in SaveVarArgRegisters()
1125 MemOps.size()); in SaveVarArgRegisters()
2803 SmallVector<SDValue, 4> MemOps; in LowerVASTART() local
2808 MemOps.push_back(DAG.getStore(Chain, DL, Stack, VAList, in LowerVASTART()
2823 MemOps.push_back(DAG.getStore(Chain, DL, GRTop, GRTopAddr, in LowerVASTART()
2839 MemOps.push_back(DAG.getStore(Chain, DL, VRTop, VRTopAddr, in LowerVASTART()
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| /trueos/contrib/llvm/lib/Target/PowerPC/ |
| HD | PPCISelLowering.cpp | 2093 SmallVector<SDValue, 8> MemOps; in LowerFormalArguments_32SVR4() local
2138 MemOps.push_back(Store); in LowerFormalArguments_32SVR4()
2157 MemOps.push_back(Store); in LowerFormalArguments_32SVR4()
2165 if (!MemOps.empty()) in LowerFormalArguments_32SVR4()
2167 MVT::Other, &MemOps[0], MemOps.size()); in LowerFormalArguments_32SVR4()
2260 SmallVector<SDValue, 8> MemOps; in LowerFormalArguments_64SVR4() local
2352 MemOps.push_back(Store); in LowerFormalArguments_64SVR4()
2374 MemOps.push_back(Store); in LowerFormalArguments_64SVR4()
2496 MemOps.push_back(Store); in LowerFormalArguments_64SVR4()
2503 if (!MemOps.empty()) in LowerFormalArguments_64SVR4()
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| /trueos/contrib/llvm/lib/Target/Hexagon/ |
| HD | HexagonISelLowering.cpp | 854 SmallVector<SDValue, 4> MemOps; in LowerFormalArguments() local
918 if (!MemOps.empty()) in LowerFormalArguments()
919 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &MemOps[0], in LowerFormalArguments()
920 MemOps.size()); in LowerFormalArguments()
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| HD | HexagonInstrInfoV4.td | 2102 // Define 'def Pats' for MemOps with register addend.
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| /trueos/contrib/llvm/lib/Target/SystemZ/ |
| HD | SystemZISelLowering.cpp | 730 SDValue MemOps[SystemZ::NumArgFPRs]; in LowerFormalArguments() local
738 MemOps[I] = DAG.getStore(ArgValue.getValue(1), DL, ArgValue, FIN, in LowerFormalArguments()
745 &MemOps[NumFixedFPRs], in LowerFormalArguments()
1734 SDValue MemOps[NumFields]; in lowerVASTART() local
1741 MemOps[I] = DAG.getStore(Chain, DL, Fields[I], FieldAddr, in lowerVASTART()
1746 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps, NumFields); in lowerVASTART()
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| /trueos/contrib/llvm/lib/Target/X86/ |
| HD | X86ISelLowering.cpp | 2366 SmallVector<SDValue, 8> MemOps; in LowerFormalArguments() local
2381 MemOps.push_back(Store); in LowerFormalArguments()
2405 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl, in LowerFormalArguments()
2410 if (!MemOps.empty()) in LowerFormalArguments()
2412 &MemOps[0], MemOps.size()); in LowerFormalArguments()
10855 SmallVector<SDValue, 8> MemOps; in LowerVASTART() local
10862 MemOps.push_back(Store); in LowerVASTART()
10871 MemOps.push_back(Store); in LowerVASTART()
10881 MemOps.push_back(Store); in LowerVASTART()
10890 MemOps.push_back(Store); in LowerVASTART()
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