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Searched refs:MRM0r (Results 1 – 11 of 11) sorted by relevance

/trueos/contrib/llvm/utils/TableGen/
HDX86RecognizableInstr.cpp62 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, enumerator
157 (form >= X86Local::MRM0r && form <= X86Local::MRM7r) || in needsModRMForDecode()
173 (form >= X86Local::MRM0r && form <= X86Local::MRM7r)) in isRegFormat()
799 case X86Local::MRM0r: in emitInstructionSpecifier()
917 case X86Local::MRM0r: in emitDecodePath()
925 filter = new ExtendedFilter(true, Form - X86Local::MRM0r); in emitDecodePath()
960 case X86Local::MRM0r: in emitDecodePath()
968 filter = new ExtendedFilter(true, Form - X86Local::MRM0r); in emitDecodePath()
1034 case X86Local::MRM0r: in emitDecodePath()
1042 filter = new ExtendedFilter(true, Form - X86Local::MRM0r); in emitDecodePath()
[all …]
/trueos/contrib/llvm/lib/Target/X86/MCTargetDesc/
HDX86BaseInfo.h264 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3 enumerator
630 case X86II::MRM0r: case X86II::MRM1r: in getMemoryOperandNo()
HDX86MCCodeEmitter.cpp866 case X86II::MRM0r: case X86II::MRM1r: in EmitVEXOpcodePrefix()
1343 case X86II::MRM0r: case X86II::MRM1r: in EncodeInstruction()
1351 (TSFlags & X86II::FormMask)-X86II::MRM0r, in EncodeInstruction()
/trueos/contrib/llvm/lib/Target/X86/
HDX86InstrShiftRotate.td474 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
477 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
480 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
483 def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
488 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
491 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
496 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
500 def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst),
507 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
511 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
[all …]
HDX86InstrSystem.td377 def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
381 def SLDT32r : I<0x00, MRM0r, (outs GR32:$dst), (ins),
386 def SLDT64r : RI<0x00, MRM0r, (outs GR64:$dst), (ins),
489 def RDFSBASE : I<0xAE, MRM0r, (outs GR32:$dst), (ins),
492 def RDFSBASE64 : RI<0xAE, MRM0r, (outs GR64:$dst), (ins),
HDX86InstrArithmetic.td454 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
469 def INC64r : RI<0xFF, MRM0r, (outs GR64:$dst), (ins GR64:$src1), "inc{q}\t$dst",
478 def INC64_16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
483 def INC64_32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
501 def INC32_16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
504 def INC32_32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
1224 defm ADD : ArithBinOp_RF<0x00, 0x02, 0x04, "add", MRM0r, MRM0m,
1264 def TEST8ri : BinOpRI_F<0xF6, "test", Xi8 , X86testpat, MRM0r>;
1265 def TEST16ri : BinOpRI_F<0xF6, "test", Xi16, X86testpat, MRM0r>;
1266 def TEST32ri : BinOpRI_F<0xF6, "test", Xi32, X86testpat, MRM0r>;
[all …]
HDX86InstrCMovSetCC.td84 def r : I<opc, MRM0r, (outs GR8:$dst), (ins),
HDX86CodeEmitter.cpp1060 case X86II::MRM0r: case X86II::MRM1r: in emitVEXOpcodePrefix()
1356 case X86II::MRM0r: case X86II::MRM1r: in emitInstruction()
1364 (Desc->TSFlags & X86II::FormMask)-X86II::MRM0r); in emitInstruction()
HDX86InstrInfo.td881 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
885 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
929 def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", [],
1099 def MOV64ri32 : RIi32<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
HDX86InstrFormats.td25 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
HDX86InstrSSE.td7509 def EXTRQI : Ii8<0x78, MRM0r, (outs VR128:$dst),