1 /*
2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef MLX4_DEVICE_H
34 #define MLX4_DEVICE_H
35
36 #include <linux/pci.h>
37 #include <linux/completion.h>
38 #include <linux/radix-tree.h>
39 #include <linux/types.h>
40 #include <linux/bitops.h>
41 #include <linux/workqueue.h>
42 #include <asm/atomic.h>
43
44 #include <linux/clocksource.h>
45
46 #define MAX_MSIX_P_PORT 17
47 #define MAX_MSIX 64
48 #define MSIX_LEGACY_SZ 4
49 #define MIN_MSIX_P_PORT 5
50
51 #define MLX4_ROCE_MAX_GIDS 128
52 #define MLX4_ROCE_PF_GIDS 16
53
54 #define MLX4_NUM_UP 8
55 #define MLX4_NUM_TC 8
56 #define MLX4_MAX_100M_UNITS_VAL 255 /*
57 * work around: can't set values
58 * greater then this value when
59 * using 100 Mbps units.
60 */
61 #define MLX4_RATELIMIT_100M_UNITS 3 /* 100 Mbps */
62 #define MLX4_RATELIMIT_1G_UNITS 4 /* 1 Gbps */
63 #define MLX4_RATELIMIT_DEFAULT 0x00ff
64
65 #define CORE_CLOCK_MASK 0xffffffffffffULL
66
67 enum {
68 MLX4_FLAG_MSI_X = 1 << 0,
69 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1,
70 MLX4_FLAG_MASTER = 1 << 2,
71 MLX4_FLAG_SLAVE = 1 << 3,
72 MLX4_FLAG_SRIOV = 1 << 4,
73 MLX4_FLAG_DEV_NUM_STR = 1 << 5,
74 MLX4_FLAG_OLD_REG_MAC = 1 << 6,
75 };
76
77 enum {
78 MLX4_PORT_CAP_IS_SM = 1 << 1,
79 MLX4_PORT_CAP_DEV_MGMT_SUP = 1 << 19,
80 };
81
82 enum {
83 MLX4_MAX_PORTS = 2,
84 MLX4_MAX_PORT_PKEYS = 128
85 };
86
87 /* base qkey for use in sriov tunnel-qp/proxy-qp communication.
88 * These qkeys must not be allowed for general use. This is a 64k range,
89 * and to test for violation, we use the mask (protect against future chg).
90 */
91 #define MLX4_RESERVED_QKEY_BASE (0xFFFF0000)
92 #define MLX4_RESERVED_QKEY_MASK (0xFFFF0000)
93
94 enum {
95 MLX4_BOARD_ID_LEN = 64,
96 MLX4_VSD_LEN = 208
97 };
98
99 enum {
100 MLX4_MAX_NUM_PF = 16,
101 MLX4_MAX_NUM_VF = 64,
102 MLX4_MFUNC_MAX = 80,
103 MLX4_MAX_EQ_NUM = 1024,
104 MLX4_MFUNC_EQ_NUM = 4,
105 MLX4_MFUNC_MAX_EQES = 8,
106 MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1)
107 };
108
109 /* Driver supports 3 diffrent device methods to manage traffic steering:
110 * -device managed - High level API for ib and eth flow steering. FW is
111 * managing flow steering tables.
112 * - B0 steering mode - Common low level API for ib and (if supported) eth.
113 * - A0 steering mode - Limited low level API for eth. In case of IB,
114 * B0 mode is in use.
115 */
116 enum {
117 MLX4_STEERING_MODE_A0,
118 MLX4_STEERING_MODE_B0,
119 MLX4_STEERING_MODE_DEVICE_MANAGED
120 };
121
mlx4_steering_mode_str(int steering_mode)122 static inline const char *mlx4_steering_mode_str(int steering_mode)
123 {
124 switch (steering_mode) {
125 case MLX4_STEERING_MODE_A0:
126 return "A0 steering";
127
128 case MLX4_STEERING_MODE_B0:
129 return "B0 steering";
130
131 case MLX4_STEERING_MODE_DEVICE_MANAGED:
132 return "Device managed flow steering";
133
134 default:
135 return "Unrecognize steering mode";
136 }
137 }
138
139 enum {
140 MLX4_DEV_CAP_FLAG_RC = 1LL << 0,
141 MLX4_DEV_CAP_FLAG_UC = 1LL << 1,
142 MLX4_DEV_CAP_FLAG_UD = 1LL << 2,
143 MLX4_DEV_CAP_FLAG_XRC = 1LL << 3,
144 MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6,
145 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7,
146 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
147 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
148 MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12,
149 MLX4_DEV_CAP_FLAG_BLH = 1LL << 15,
150 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16,
151 MLX4_DEV_CAP_FLAG_APM = 1LL << 17,
152 MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
153 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19,
154 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20,
155 MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21,
156 MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30,
157 MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32,
158 MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34,
159 MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37,
160 MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38,
161 MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40,
162 MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41,
163 MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42,
164 MLX4_DEV_CAP_FLAG_CROSS_CHANNEL = 1LL << 44,
165 MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48,
166 MLX4_DEV_CAP_FLAG_COUNTERS_EXT = 1LL << 49,
167 MLX4_DEV_CAP_FLAG_SET_PORT_ETH_SCHED = 1LL << 53,
168 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55,
169 MLX4_DEV_CAP_FLAG_FAST_DROP = 1LL << 57,
170 MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59,
171 MLX4_DEV_CAP_FLAG_64B_EQE = 1LL << 61,
172 MLX4_DEV_CAP_FLAG_64B_CQE = 1LL << 62
173 };
174
175 enum {
176 MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0,
177 MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1,
178 MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2,
179 MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3,
180 MLX4_DEV_CAP_FLAG2_FSM = 1LL << 4,
181 MLX4_DEV_CAP_FLAG2_VLAN_CONTROL = 1LL << 5,
182 MLX4_DEV_CAP_FLAG2_UPDATE_QP = 1LL << 6,
183 MLX4_DEV_CAP_FLAG2_LB_SRC_CHK = 1LL << 7,
184 MLX4_DEV_CAP_FLAG2_DMFS_IPOIB = 1LL << 8,
185 MLX4_DEV_CAP_FLAG2_ETS_CFG = 1LL << 9,
186 MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP = 1LL << 10,
187 MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN = 1LL << 11,
188 MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT = 1LL << 12,
189 MLX4_DEV_CAP_FLAG2_TS = 1LL << 13,
190 MLX4_DEV_CAP_FLAG2_DRIVER_VERSION_TO_FW = 1LL << 14,
191 MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN = 1LL << 15,
192 MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS = 1LL << 16,
193 MLX4_DEV_CAP_FLAG2_FS_EN_NCSI = 1LL << 17,
194 MLX4_DEV_CAP_FLAG2_80_VFS = 1LL << 18,
195 MLX4_DEV_CAP_FLAG2_DMFS_TAG_MODE = 1LL << 19,
196 MLX4_DEV_CAP_FLAG2_ROCEV2 = 1LL << 20,
197 MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL = 1LL << 21,
198 MLX4_DEV_CAP_FLAG2_CQE_STRIDE = 1LL << 22,
199 MLX4_DEV_CAP_FLAG2_EQE_STRIDE = 1LL << 23,
200 MLX4_DEV_CAP_FLAG2_UPDATE_QP_SRC_CHECK_LB = 1LL << 24,
201 MLX4_DEV_CAP_FLAG2_RX_CSUM_MODE = 1LL << 25,
202 };
203
204 /* bit enums for an 8-bit flags field indicating special use
205 * QPs which require special handling in qp_reserve_range.
206 * Currently, this only includes QPs used by the ETH interface,
207 * where we expect to use blueflame. These QPs must not have
208 * bits 6 and 7 set in their qp number.
209 *
210 * This enum may use only bits 0..7.
211 */
212 enum {
213 MLX4_RESERVE_BF_QP = 1 << 7,
214 };
215
216 enum {
217 MLX4_DEV_CAP_CQ_FLAG_IO = 1 << 0
218 };
219
220 enum {
221 MLX4_DEV_CAP_64B_EQE_ENABLED = 1LL << 0,
222 MLX4_DEV_CAP_64B_CQE_ENABLED = 1LL << 1
223 };
224
225 enum {
226 MLX4_USER_DEV_CAP_64B_CQE = 1L << 0
227 };
228
229 enum {
230 MLX4_FUNC_CAP_64B_EQE_CQE = 1L << 0
231 };
232
233
234 #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
235
236 enum {
237 MLX4_BMME_FLAG_WIN_TYPE_2B = 1 << 1,
238 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6,
239 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7,
240 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9,
241 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10,
242 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11,
243 };
244
245 enum mlx4_event {
246 MLX4_EVENT_TYPE_COMP = 0x00,
247 MLX4_EVENT_TYPE_PATH_MIG = 0x01,
248 MLX4_EVENT_TYPE_COMM_EST = 0x02,
249 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03,
250 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13,
251 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14,
252 MLX4_EVENT_TYPE_CQ_ERROR = 0x04,
253 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
254 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06,
255 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
256 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
257 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
258 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
259 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08,
260 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09,
261 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
262 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e,
263 MLX4_EVENT_TYPE_CMD = 0x0a,
264 MLX4_EVENT_TYPE_VEP_UPDATE = 0x19,
265 MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18,
266 MLX4_EVENT_TYPE_OP_REQUIRED = 0x1a,
267 MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b,
268 MLX4_EVENT_TYPE_FLR_EVENT = 0x1c,
269 MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d,
270 MLX4_EVENT_TYPE_RECOVERABLE_ERROR_EVENT = 0x3e,
271 MLX4_EVENT_TYPE_NONE = 0xff,
272 };
273
274 enum {
275 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1,
276 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4
277 };
278
279 enum {
280 MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_BAD_CABLE = 1,
281 MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_UNSUPPORTED_CABLE = 2,
282 };
283
284 enum {
285 MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0,
286 };
287
288 enum slave_port_state {
289 SLAVE_PORT_DOWN = 0,
290 SLAVE_PENDING_UP,
291 SLAVE_PORT_UP,
292 };
293
294 enum slave_port_gen_event {
295 SLAVE_PORT_GEN_EVENT_DOWN = 0,
296 SLAVE_PORT_GEN_EVENT_UP,
297 SLAVE_PORT_GEN_EVENT_NONE,
298 };
299
300 enum slave_port_state_event {
301 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN,
302 MLX4_PORT_STATE_DEV_EVENT_PORT_UP,
303 MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID,
304 MLX4_PORT_STATE_IB_EVENT_GID_INVALID,
305 };
306
307 enum {
308 MLX4_PERM_LOCAL_READ = 1 << 10,
309 MLX4_PERM_LOCAL_WRITE = 1 << 11,
310 MLX4_PERM_REMOTE_READ = 1 << 12,
311 MLX4_PERM_REMOTE_WRITE = 1 << 13,
312 MLX4_PERM_ATOMIC = 1 << 14,
313 MLX4_PERM_BIND_MW = 1 << 15,
314 };
315
316 enum {
317 MLX4_OPCODE_NOP = 0x00,
318 MLX4_OPCODE_SEND_INVAL = 0x01,
319 MLX4_OPCODE_RDMA_WRITE = 0x08,
320 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09,
321 MLX4_OPCODE_SEND = 0x0a,
322 MLX4_OPCODE_SEND_IMM = 0x0b,
323 MLX4_OPCODE_LSO = 0x0e,
324 MLX4_OPCODE_RDMA_READ = 0x10,
325 MLX4_OPCODE_ATOMIC_CS = 0x11,
326 MLX4_OPCODE_ATOMIC_FA = 0x12,
327 MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14,
328 MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15,
329 MLX4_OPCODE_BIND_MW = 0x18,
330 MLX4_OPCODE_FMR = 0x19,
331 MLX4_OPCODE_LOCAL_INVAL = 0x1b,
332 MLX4_OPCODE_CONFIG_CMD = 0x1f,
333
334 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
335 MLX4_RECV_OPCODE_SEND = 0x01,
336 MLX4_RECV_OPCODE_SEND_IMM = 0x02,
337 MLX4_RECV_OPCODE_SEND_INVAL = 0x03,
338
339 MLX4_CQE_OPCODE_ERROR = 0x1e,
340 MLX4_CQE_OPCODE_RESIZE = 0x16,
341 };
342
343 enum {
344 MLX4_STAT_RATE_OFFSET = 5
345 };
346
347 enum mlx4_protocol {
348 MLX4_PROT_IB_IPV6 = 0,
349 MLX4_PROT_ETH,
350 MLX4_PROT_IB_IPV4,
351 MLX4_PROT_FCOE
352 };
353
354 enum {
355 MLX4_MTT_FLAG_PRESENT = 1
356 };
357
358 enum {
359 MLX4_MAX_MTT_SHIFT = 31
360 };
361
362 enum mlx4_qp_region {
363 MLX4_QP_REGION_FW = 0,
364 MLX4_QP_REGION_ETH_ADDR,
365 MLX4_QP_REGION_FC_ADDR,
366 MLX4_QP_REGION_FC_EXCH,
367 MLX4_NUM_QP_REGION
368 };
369
370 enum mlx4_port_type {
371 MLX4_PORT_TYPE_NONE = 0,
372 MLX4_PORT_TYPE_IB = 1,
373 MLX4_PORT_TYPE_ETH = 2,
374 MLX4_PORT_TYPE_AUTO = 3,
375 MLX4_PORT_TYPE_NA = 4
376 };
377
378 enum mlx4_special_vlan_idx {
379 MLX4_NO_VLAN_IDX = 0,
380 MLX4_VLAN_MISS_IDX,
381 MLX4_VLAN_REGULAR
382 };
383
384 enum mlx4_steer_type {
385 MLX4_MC_STEER = 0,
386 MLX4_UC_STEER,
387 MLX4_NUM_STEERS
388 };
389
390 enum {
391 MLX4_NUM_FEXCH = 64 * 1024,
392 };
393
394 enum {
395 MLX4_MAX_FAST_REG_PAGES = 511,
396 };
397
398 enum {
399 MLX4_DEV_PMC_SUBTYPE_GUID_INFO = 0x14,
400 MLX4_DEV_PMC_SUBTYPE_PORT_INFO = 0x15,
401 MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE = 0x16,
402 };
403
404 /* Port mgmt change event handling */
405 enum {
406 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK = 1 << 0,
407 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK = 1 << 1,
408 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK = 1 << 2,
409 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK = 1 << 3,
410 MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4,
411 };
412
413 #define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \
414 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK)
415
mlx4_fw_ver(u64 major,u64 minor,u64 subminor)416 static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
417 {
418 return (major << 32) | (minor << 16) | subminor;
419 }
420
421 struct mlx4_phys_caps {
422 u32 gid_phys_table_len[MLX4_MAX_PORTS + 1];
423 u32 pkey_phys_table_len[MLX4_MAX_PORTS + 1];
424 u32 num_phys_eqs;
425 u32 base_sqpn;
426 u32 base_proxy_sqpn;
427 u32 base_tunnel_sqpn;
428 };
429
430 struct mlx4_caps {
431 u64 fw_ver;
432 u32 function;
433 int num_ports;
434 int vl_cap[MLX4_MAX_PORTS + 1];
435 int ib_mtu_cap[MLX4_MAX_PORTS + 1];
436 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1];
437 u64 def_mac[MLX4_MAX_PORTS + 1];
438 int eth_mtu_cap[MLX4_MAX_PORTS + 1];
439 int gid_table_len[MLX4_MAX_PORTS + 1];
440 int pkey_table_len[MLX4_MAX_PORTS + 1];
441 int trans_type[MLX4_MAX_PORTS + 1];
442 int vendor_oui[MLX4_MAX_PORTS + 1];
443 int wavelength[MLX4_MAX_PORTS + 1];
444 u64 trans_code[MLX4_MAX_PORTS + 1];
445 int local_ca_ack_delay;
446 int num_uars;
447 u32 uar_page_size;
448 int bf_reg_size;
449 int bf_regs_per_page;
450 int max_sq_sg;
451 int max_rq_sg;
452 int num_qps;
453 int max_wqes;
454 int max_sq_desc_sz;
455 int max_rq_desc_sz;
456 int max_qp_init_rdma;
457 int max_qp_dest_rdma;
458 u32 *qp0_proxy;
459 u32 *qp1_proxy;
460 u32 *qp0_tunnel;
461 u32 *qp1_tunnel;
462 int num_srqs;
463 int max_srq_wqes;
464 int max_srq_sge;
465 int reserved_srqs;
466 int num_cqs;
467 int max_cqes;
468 int reserved_cqs;
469 int num_eqs;
470 int reserved_eqs;
471 int num_comp_vectors;
472 int comp_pool;
473 int num_mpts;
474 int max_fmr_maps;
475 u64 num_mtts;
476 int fmr_reserved_mtts;
477 int reserved_mtts;
478 int reserved_mrws;
479 int reserved_uars;
480 int num_mgms;
481 int num_amgms;
482 int reserved_mcgs;
483 int num_qp_per_mgm;
484 int steering_mode;
485 int num_pds;
486 int reserved_pds;
487 int max_xrcds;
488 int reserved_xrcds;
489 int mtt_entry_sz;
490 u32 max_msg_sz;
491 u32 page_size_cap;
492 u64 flags;
493 u64 flags2;
494 u32 bmme_flags;
495 u32 reserved_lkey;
496 u16 stat_rate_support;
497 u8 cq_timestamp;
498 u8 port_width_cap[MLX4_MAX_PORTS + 1];
499 int max_gso_sz;
500 int max_rss_tbl_sz;
501 int reserved_qps_cnt[MLX4_NUM_QP_REGION];
502 int reserved_qps;
503 int reserved_qps_base[MLX4_NUM_QP_REGION];
504 int log_num_macs;
505 int log_num_vlans;
506 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
507 u8 supported_type[MLX4_MAX_PORTS + 1];
508 u8 suggested_type[MLX4_MAX_PORTS + 1];
509 u8 default_sense[MLX4_MAX_PORTS + 1];
510 u32 port_mask[MLX4_MAX_PORTS + 1];
511 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1];
512 u32 max_counters;
513 u8 port_ib_mtu[MLX4_MAX_PORTS + 1];
514 u16 sqp_demux;
515 u32 sync_qp;
516 u32 cq_flags;
517 u32 eqe_size;
518 u32 cqe_size;
519 u8 eqe_factor;
520 u32 userspace_caps; /* userspace must be aware to */
521 u32 function_caps; /* functions must be aware to */
522 u8 fast_drop;
523 u16 hca_core_clock;
524 u32 max_basic_counters;
525 u32 max_extended_counters;
526 u8 def_counter_index[MLX4_MAX_PORTS + 1];
527 };
528
529 struct mlx4_buf_list {
530 void *buf;
531 dma_addr_t map;
532 };
533
534 struct mlx4_buf {
535 struct mlx4_buf_list direct;
536 struct mlx4_buf_list *page_list;
537 int nbufs;
538 int npages;
539 int page_shift;
540 };
541
542 struct mlx4_mtt {
543 u32 offset;
544 int order;
545 int page_shift;
546 };
547
548 enum {
549 MLX4_DB_PER_PAGE = PAGE_SIZE / 4
550 };
551
552 struct mlx4_db_pgdir {
553 struct list_head list;
554 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE);
555 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2);
556 unsigned long *bits[2];
557 __be32 *db_page;
558 dma_addr_t db_dma;
559 };
560
561 struct mlx4_ib_user_db_page;
562
563 struct mlx4_db {
564 __be32 *db;
565 union {
566 struct mlx4_db_pgdir *pgdir;
567 struct mlx4_ib_user_db_page *user_page;
568 } u;
569 dma_addr_t dma;
570 int index;
571 int order;
572 };
573
574 struct mlx4_hwq_resources {
575 struct mlx4_db db;
576 struct mlx4_mtt mtt;
577 struct mlx4_buf buf;
578 };
579
580 struct mlx4_mr {
581 struct mlx4_mtt mtt;
582 u64 iova;
583 u64 size;
584 u32 key;
585 u32 pd;
586 u32 access;
587 int enabled;
588 };
589
590 enum mlx4_mw_type {
591 MLX4_MW_TYPE_1 = 1,
592 MLX4_MW_TYPE_2 = 2,
593 };
594
595 struct mlx4_mw {
596 u32 key;
597 u32 pd;
598 enum mlx4_mw_type type;
599 int enabled;
600 };
601
602 struct mlx4_fmr {
603 struct mlx4_mr mr;
604 struct mlx4_mpt_entry *mpt;
605 __be64 *mtts;
606 dma_addr_t dma_handle;
607 int max_pages;
608 int max_maps;
609 int maps;
610 u8 page_shift;
611 };
612
613 struct mlx4_uar {
614 unsigned long pfn;
615 int index;
616 struct list_head bf_list;
617 unsigned free_bf_bmap;
618 void __iomem *map;
619 void __iomem *bf_map;
620 };
621
622 struct mlx4_bf {
623 unsigned long offset;
624 int buf_size;
625 struct mlx4_uar *uar;
626 void __iomem *reg;
627 };
628
629 struct mlx4_cq {
630 void (*comp) (struct mlx4_cq *);
631 void (*event) (struct mlx4_cq *, enum mlx4_event);
632
633 struct mlx4_uar *uar;
634
635 u32 cons_index;
636
637 __be32 *set_ci_db;
638 __be32 *arm_db;
639 int arm_sn;
640
641 int cqn;
642 unsigned vector;
643
644 atomic_t refcount;
645 struct completion free;
646 int eqn;
647 u16 irq;
648 };
649
650 struct mlx4_qp {
651 void (*event) (struct mlx4_qp *, enum mlx4_event);
652
653 int qpn;
654
655 atomic_t refcount;
656 struct completion free;
657 };
658
659 struct mlx4_srq {
660 void (*event) (struct mlx4_srq *, enum mlx4_event);
661
662 int srqn;
663 int max;
664 int max_gs;
665 int wqe_shift;
666
667 atomic_t refcount;
668 struct completion free;
669 };
670
671 struct mlx4_av {
672 __be32 port_pd;
673 u8 reserved1;
674 u8 g_slid;
675 __be16 dlid;
676 u8 reserved2;
677 u8 gid_index;
678 u8 stat_rate;
679 u8 hop_limit;
680 __be32 sl_tclass_flowlabel;
681 u8 dgid[16];
682 };
683
684 struct mlx4_eth_av {
685 __be32 port_pd;
686 u8 reserved1;
687 u8 smac_idx;
688 u16 reserved2;
689 u8 reserved3;
690 u8 gid_index;
691 u8 stat_rate;
692 u8 hop_limit;
693 __be32 sl_tclass_flowlabel;
694 u8 dgid[16];
695 u8 s_mac[6];
696 u8 reserved4[2];
697 __be16 vlan;
698 u8 mac[6];
699 };
700
701 union mlx4_ext_av {
702 struct mlx4_av ib;
703 struct mlx4_eth_av eth;
704 };
705
706 struct mlx4_if_stat_control {
707 u8 reserved1[3];
708 /* Extended counters enabled */
709 u8 cnt_mode;
710 /* Number of interfaces */
711 __be32 num_of_if;
712 __be32 reserved[2];
713 };
714
715 struct mlx4_if_stat_basic {
716 struct mlx4_if_stat_control control;
717 struct {
718 __be64 IfRxFrames;
719 __be64 IfRxOctets;
720 __be64 IfTxFrames;
721 __be64 IfTxOctets;
722 } counters[];
723 };
724 #define MLX4_IF_STAT_BSC_SZ(ports)(sizeof(struct mlx4_if_stat_extended) +\
725 sizeof(((struct mlx4_if_stat_extended *)0)->\
726 counters[0]) * ports)
727
728 struct mlx4_if_stat_extended {
729 struct mlx4_if_stat_control control;
730 struct {
731 __be64 IfRxUnicastFrames;
732 __be64 IfRxUnicastOctets;
733 __be64 IfRxMulticastFrames;
734 __be64 IfRxMulticastOctets;
735 __be64 IfRxBroadcastFrames;
736 __be64 IfRxBroadcastOctets;
737 __be64 IfRxNoBufferFrames;
738 __be64 IfRxNoBufferOctets;
739 __be64 IfRxErrorFrames;
740 __be64 IfRxErrorOctets;
741 __be32 reserved[39];
742 __be64 IfTxUnicastFrames;
743 __be64 IfTxUnicastOctets;
744 __be64 IfTxMulticastFrames;
745 __be64 IfTxMulticastOctets;
746 __be64 IfTxBroadcastFrames;
747 __be64 IfTxBroadcastOctets;
748 __be64 IfTxDroppedFrames;
749 __be64 IfTxDroppedOctets;
750 __be64 IfTxRequestedFramesSent;
751 __be64 IfTxGeneratedFramesSent;
752 __be64 IfTxTsoOctets;
753 } __packed counters[];
754 };
755 #define MLX4_IF_STAT_EXT_SZ(ports) (sizeof(struct mlx4_if_stat_extended) +\
756 sizeof(((struct mlx4_if_stat_extended *)\
757 0)->counters[0]) * ports)
758
759 union mlx4_counter {
760 struct mlx4_if_stat_control control;
761 struct mlx4_if_stat_basic basic;
762 struct mlx4_if_stat_extended ext;
763 };
764 #define MLX4_IF_STAT_SZ(ports) MLX4_IF_STAT_EXT_SZ(ports)
765
766 struct mlx4_quotas {
767 int qp;
768 int cq;
769 int srq;
770 int mpt;
771 int mtt;
772 int counter;
773 int xrcd;
774 };
775
776 struct mlx4_dev {
777 struct pci_dev *pdev;
778 unsigned long flags;
779 unsigned long num_slaves;
780 struct mlx4_caps caps;
781 struct mlx4_phys_caps phys_caps;
782 struct mlx4_quotas quotas;
783 struct radix_tree_root qp_table_tree;
784 u8 rev_id;
785 char board_id[MLX4_BOARD_ID_LEN];
786 u16 vsd_vendor_id;
787 char vsd[MLX4_VSD_LEN];
788 int num_vfs;
789 int numa_node;
790 int oper_log_mgm_entry_size;
791 u64 regid_promisc_array[MLX4_MAX_PORTS + 1];
792 u64 regid_allmulti_array[MLX4_MAX_PORTS + 1];
793 };
794
795 struct mlx4_clock_params {
796 u64 offset;
797 u8 bar;
798 u8 size;
799 };
800
801 struct mlx4_eqe {
802 u8 reserved1;
803 u8 type;
804 u8 reserved2;
805 u8 subtype;
806 union {
807 u32 raw[6];
808 struct {
809 __be32 cqn;
810 } __packed comp;
811 struct {
812 u16 reserved1;
813 __be16 token;
814 u32 reserved2;
815 u8 reserved3[3];
816 u8 status;
817 __be64 out_param;
818 } __packed cmd;
819 struct {
820 __be32 qpn;
821 } __packed qp;
822 struct {
823 __be32 srqn;
824 } __packed srq;
825 struct {
826 __be32 cqn;
827 u32 reserved1;
828 u8 reserved2[3];
829 u8 syndrome;
830 } __packed cq_err;
831 struct {
832 u32 reserved1[2];
833 __be32 port;
834 } __packed port_change;
835 struct {
836 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4
837 u32 reserved;
838 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE];
839 } __packed comm_channel_arm;
840 struct {
841 u8 port;
842 u8 reserved[3];
843 __be64 mac;
844 } __packed mac_update;
845 struct {
846 __be32 slave_id;
847 } __packed flr_event;
848 struct {
849 __be16 current_temperature;
850 __be16 warning_threshold;
851 } __packed warming;
852 struct {
853 u8 reserved[3];
854 u8 port;
855 union {
856 struct {
857 __be16 mstr_sm_lid;
858 __be16 port_lid;
859 __be32 changed_attr;
860 u8 reserved[3];
861 u8 mstr_sm_sl;
862 __be64 gid_prefix;
863 } __packed port_info;
864 struct {
865 __be32 block_ptr;
866 __be32 tbl_entries_mask;
867 } __packed tbl_change_info;
868 } params;
869 } __packed port_mgmt_change;
870 struct {
871 u8 reserved[3];
872 u8 port;
873 u32 reserved1[5];
874 } __packed bad_cable;
875 } event;
876 u8 slave_id;
877 u8 reserved3[2];
878 u8 owner;
879 } __packed;
880
881 struct mlx4_init_port_param {
882 int set_guid0;
883 int set_node_guid;
884 int set_si_guid;
885 u16 mtu;
886 int port_width_cap;
887 u16 vl_cap;
888 u16 max_gid;
889 u16 max_pkey;
890 u64 guid0;
891 u64 node_guid;
892 u64 si_guid;
893 };
894
895 #define mlx4_foreach_port(port, dev, type) \
896 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
897 if ((type) == (dev)->caps.port_mask[(port)])
898
899 #define mlx4_foreach_non_ib_transport_port(port, dev) \
900 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
901 if (((dev)->caps.port_mask[port] != MLX4_PORT_TYPE_IB))
902
903 #define mlx4_foreach_ib_transport_port(port, dev) \
904 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
905 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \
906 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
907
908 #define MLX4_INVALID_SLAVE_ID 0xFF
909
910 #define MLX4_SINK_COUNTER_INDEX 0xff
911
912 void handle_port_mgmt_change_event(struct work_struct *work);
913
mlx4_master_func_num(struct mlx4_dev * dev)914 static inline int mlx4_master_func_num(struct mlx4_dev *dev)
915 {
916 return dev->caps.function;
917 }
918
mlx4_is_master(struct mlx4_dev * dev)919 static inline int mlx4_is_master(struct mlx4_dev *dev)
920 {
921 return dev->flags & MLX4_FLAG_MASTER;
922 }
923
mlx4_num_reserved_sqps(struct mlx4_dev * dev)924 static inline int mlx4_num_reserved_sqps(struct mlx4_dev *dev)
925 {
926 return dev->phys_caps.base_sqpn + 8 +
927 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev);
928 }
929
mlx4_is_qp_reserved(struct mlx4_dev * dev,u32 qpn)930 static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn)
931 {
932 return (qpn < dev->phys_caps.base_sqpn + 8 +
933 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev));
934 }
935
mlx4_is_guest_proxy(struct mlx4_dev * dev,int slave,u32 qpn)936 static inline int mlx4_is_guest_proxy(struct mlx4_dev *dev, int slave, u32 qpn)
937 {
938 int guest_proxy_base = dev->phys_caps.base_proxy_sqpn + slave * 8;
939
940 if (qpn >= guest_proxy_base && qpn < guest_proxy_base + 8)
941 return 1;
942
943 return 0;
944 }
945
mlx4_is_mfunc(struct mlx4_dev * dev)946 static inline int mlx4_is_mfunc(struct mlx4_dev *dev)
947 {
948 return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER);
949 }
950
mlx4_is_slave(struct mlx4_dev * dev)951 static inline int mlx4_is_slave(struct mlx4_dev *dev)
952 {
953 return dev->flags & MLX4_FLAG_SLAVE;
954 }
955
956 int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
957 struct mlx4_buf *buf);
958 void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
mlx4_buf_offset(struct mlx4_buf * buf,int offset)959 static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset)
960 {
961 if (BITS_PER_LONG == 64 || buf->nbufs == 1)
962 return (u8 *)buf->direct.buf + offset;
963 else
964 return (u8 *)buf->page_list[offset >> PAGE_SHIFT].buf +
965 (offset & (PAGE_SIZE - 1));
966 }
967
968 int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn);
969 void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
970 int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
971 void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
972
973 int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar);
974 void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar);
975 int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf, int node);
976 void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf);
977
978 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
979 struct mlx4_mtt *mtt);
980 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
981 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
982
983 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
984 int npages, int page_shift, struct mlx4_mr *mr);
985 int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr);
986 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr);
987 int mlx4_mw_alloc(struct mlx4_dev *dev, u32 pd, enum mlx4_mw_type type,
988 struct mlx4_mw *mw);
989 void mlx4_mw_free(struct mlx4_dev *dev, struct mlx4_mw *mw);
990 int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw);
991 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
992 int start_index, int npages, u64 *page_list);
993 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
994 struct mlx4_buf *buf);
995
996 int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order);
997 void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db);
998
999 int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres,
1000 int size, int max_direct);
1001 void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres,
1002 int size);
1003
1004 int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
1005 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq,
1006 unsigned vector, int collapsed, int timestamp_en);
1007 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);
1008
1009 int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
1010 int *base, u8 flags);
1011 void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
1012
1013 int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp);
1014 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp);
1015
1016 int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn,
1017 struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq);
1018 void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
1019 int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
1020 int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark);
1021
1022 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
1023 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
1024
1025 int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1026 int block_mcast_loopback, enum mlx4_protocol prot);
1027 int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1028 enum mlx4_protocol prot);
1029 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1030 u8 port, int block_mcast_loopback,
1031 enum mlx4_protocol protocol, u64 *reg_id);
1032 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1033 enum mlx4_protocol protocol, u64 reg_id);
1034
1035 enum {
1036 MLX4_DOMAIN_UVERBS = 0x1000,
1037 MLX4_DOMAIN_ETHTOOL = 0x2000,
1038 MLX4_DOMAIN_RFS = 0x3000,
1039 MLX4_DOMAIN_NIC = 0x5000,
1040 };
1041
1042 enum mlx4_net_trans_rule_id {
1043 MLX4_NET_TRANS_RULE_ID_ETH = 0,
1044 MLX4_NET_TRANS_RULE_ID_IB,
1045 MLX4_NET_TRANS_RULE_ID_IPV6,
1046 MLX4_NET_TRANS_RULE_ID_IPV4,
1047 MLX4_NET_TRANS_RULE_ID_TCP,
1048 MLX4_NET_TRANS_RULE_ID_UDP,
1049 MLX4_NET_TRANS_RULE_NUM, /* should be last */
1050 MLX4_NET_TRANS_RULE_DUMMY = -1, /* force enum to be signed */
1051 };
1052
1053 extern const u16 __sw_id_hw[];
1054
map_hw_to_sw_id(u16 header_id)1055 static inline int map_hw_to_sw_id(u16 header_id)
1056 {
1057
1058 int i;
1059 for (i = 0; i < MLX4_NET_TRANS_RULE_NUM; i++) {
1060 if (header_id == __sw_id_hw[i])
1061 return i;
1062 }
1063 return -EINVAL;
1064 }
1065
1066 enum mlx4_net_trans_promisc_mode {
1067 MLX4_FS_REGULAR = 1,
1068 MLX4_FS_ALL_DEFAULT,
1069 MLX4_FS_MC_DEFAULT,
1070 MLX4_FS_UC_SNIFFER,
1071 MLX4_FS_MC_SNIFFER,
1072 MLX4_FS_MODE_NUM, /* should be last */
1073 MLX4_FS_MODE_DUMMY = -1, /* force enum to be signed */
1074 };
1075
1076 struct mlx4_spec_eth {
1077 u8 dst_mac[6];
1078 u8 dst_mac_msk[6];
1079 u8 src_mac[6];
1080 u8 src_mac_msk[6];
1081 u8 ether_type_enable;
1082 __be16 ether_type;
1083 __be16 vlan_id_msk;
1084 __be16 vlan_id;
1085 };
1086
1087 struct mlx4_spec_tcp_udp {
1088 __be16 dst_port;
1089 __be16 dst_port_msk;
1090 __be16 src_port;
1091 __be16 src_port_msk;
1092 };
1093
1094 struct mlx4_spec_ipv4 {
1095 __be32 dst_ip;
1096 __be32 dst_ip_msk;
1097 __be32 src_ip;
1098 __be32 src_ip_msk;
1099 };
1100
1101 struct mlx4_spec_ib {
1102 __be32 l3_qpn;
1103 __be32 qpn_msk;
1104 u8 dst_gid[16];
1105 u8 dst_gid_msk[16];
1106 };
1107
1108 struct mlx4_spec_list {
1109 struct list_head list;
1110 enum mlx4_net_trans_rule_id id;
1111 union {
1112 struct mlx4_spec_eth eth;
1113 struct mlx4_spec_ib ib;
1114 struct mlx4_spec_ipv4 ipv4;
1115 struct mlx4_spec_tcp_udp tcp_udp;
1116 };
1117 };
1118
1119 enum mlx4_net_trans_hw_rule_queue {
1120 MLX4_NET_TRANS_Q_FIFO,
1121 MLX4_NET_TRANS_Q_LIFO,
1122 };
1123
1124 struct mlx4_net_trans_rule {
1125 struct list_head list;
1126 enum mlx4_net_trans_hw_rule_queue queue_mode;
1127 bool exclusive;
1128 bool allow_loopback;
1129 enum mlx4_net_trans_promisc_mode promisc_mode;
1130 u8 port;
1131 u16 priority;
1132 u32 qpn;
1133 };
1134
1135 struct mlx4_net_trans_rule_hw_ctrl {
1136 __be16 prio;
1137 u8 type;
1138 u8 flags;
1139 u8 rsvd1;
1140 u8 funcid;
1141 u8 vep;
1142 u8 port;
1143 __be32 qpn;
1144 __be32 rsvd2;
1145 };
1146
1147 struct mlx4_net_trans_rule_hw_ib {
1148 u8 size;
1149 u8 rsvd1;
1150 __be16 id;
1151 u32 rsvd2;
1152 __be32 l3_qpn;
1153 __be32 qpn_mask;
1154 u8 dst_gid[16];
1155 u8 dst_gid_msk[16];
1156 } __packed;
1157
1158 struct mlx4_net_trans_rule_hw_eth {
1159 u8 size;
1160 u8 rsvd;
1161 __be16 id;
1162 u8 rsvd1[6];
1163 u8 dst_mac[6];
1164 u16 rsvd2;
1165 u8 dst_mac_msk[6];
1166 u16 rsvd3;
1167 u8 src_mac[6];
1168 u16 rsvd4;
1169 u8 src_mac_msk[6];
1170 u8 rsvd5;
1171 u8 ether_type_enable;
1172 __be16 ether_type;
1173 __be16 vlan_tag_msk;
1174 __be16 vlan_tag;
1175 } __packed;
1176
1177 struct mlx4_net_trans_rule_hw_tcp_udp {
1178 u8 size;
1179 u8 rsvd;
1180 __be16 id;
1181 __be16 rsvd1[3];
1182 __be16 dst_port;
1183 __be16 rsvd2;
1184 __be16 dst_port_msk;
1185 __be16 rsvd3;
1186 __be16 src_port;
1187 __be16 rsvd4;
1188 __be16 src_port_msk;
1189 } __packed;
1190
1191 struct mlx4_net_trans_rule_hw_ipv4 {
1192 u8 size;
1193 u8 rsvd;
1194 __be16 id;
1195 __be32 rsvd1;
1196 __be32 dst_ip;
1197 __be32 dst_ip_msk;
1198 __be32 src_ip;
1199 __be32 src_ip_msk;
1200 } __packed;
1201
1202 struct _rule_hw {
1203 union {
1204 struct {
1205 u8 size;
1206 u8 rsvd;
1207 __be16 id;
1208 };
1209 struct mlx4_net_trans_rule_hw_eth eth;
1210 struct mlx4_net_trans_rule_hw_ib ib;
1211 struct mlx4_net_trans_rule_hw_ipv4 ipv4;
1212 struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp;
1213 };
1214 };
1215
1216 int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn,
1217 enum mlx4_net_trans_promisc_mode mode);
1218 int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port,
1219 enum mlx4_net_trans_promisc_mode mode);
1220 int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
1221 int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
1222 int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
1223 int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
1224
1225 int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1226 void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1227 int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port);
1228 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
1229 void mlx4_set_stats_bitmap(struct mlx4_dev *dev, unsigned long *stats_bitmap);
1230 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
1231 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);
1232 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
1233 u8 promisc);
1234 int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev *dev, u8 port, u8 *prio2tc);
1235 int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev *dev, u8 port, u8 *tc_tx_bw,
1236 u8 *pg, u16 *ratelimit);
1237 int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx);
1238 int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
1239 void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan);
1240
1241 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
1242 int npages, u64 iova, u32 *lkey, u32 *rkey);
1243 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
1244 int max_maps, u8 page_shift, struct mlx4_fmr *fmr);
1245 int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
1246 void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
1247 u32 *lkey, u32 *rkey);
1248 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
1249 int mlx4_SYNC_TPT(struct mlx4_dev *dev);
1250 int mlx4_query_diag_counters(struct mlx4_dev *mlx4_dev, int array_length,
1251 u8 op_modifier, u32 in_offset[],
1252 u32 counter_out[]);
1253
1254 int mlx4_test_interrupts(struct mlx4_dev *dev);
1255 int mlx4_assign_eq(struct mlx4_dev *dev, char* name, int * vector);
1256 void mlx4_release_eq(struct mlx4_dev *dev, int vec);
1257
1258 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port);
1259 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port);
1260
1261 int mlx4_counter_alloc(struct mlx4_dev *dev, u8 port, u32 *idx);
1262 void mlx4_counter_free(struct mlx4_dev *dev, u8 port, u32 idx);
1263
1264 int mlx4_flow_attach(struct mlx4_dev *dev,
1265 struct mlx4_net_trans_rule *rule, u64 *reg_id);
1266 int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id);
1267 int map_sw_to_hw_steering_mode(struct mlx4_dev *dev,
1268 enum mlx4_net_trans_promisc_mode flow_type);
1269 int map_sw_to_hw_steering_id(struct mlx4_dev *dev,
1270 enum mlx4_net_trans_rule_id id);
1271 int hw_rule_sz(struct mlx4_dev *dev, enum mlx4_net_trans_rule_id id);
1272
1273 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port,
1274 int i, int val);
1275
1276 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey);
1277
1278 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave);
1279 int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port);
1280 int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port);
1281 int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr, u16 lid, u8 sl);
1282 int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, u8 port_subtype_change);
1283 enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port);
1284 int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int event, enum slave_port_gen_event *gen_event);
1285
1286 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid);
1287 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave);
1288 int mlx4_get_slave_from_roce_gid(struct mlx4_dev *dev, int port, u8 *gid, int *slave_id);
1289 int mlx4_get_roce_gid_from_slave(struct mlx4_dev *dev, int port, int slave_id, u8 *gid);
1290
1291 int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev *dev, u32 min_range_qpn, u32 max_range_qpn);
1292
1293 int mlx4_read_clock(struct mlx4_dev *dev);
1294 int mlx4_get_internal_clock_params(struct mlx4_dev *dev,
1295 struct mlx4_clock_params *params);
1296
1297 #endif /* MLX4_DEVICE_H */
1298