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Searched refs:MCID (Results 1 – 25 of 47) sorted by relevance

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/trueos/contrib/llvm/include/llvm/MC/
HDMCInstrDesc.h99 namespace MCID {
210 return Flags & (1 << MCID::Variadic); in isVariadic()
216 return Flags & (1 << MCID::HasOptionalDef); in hasOptionalDef()
223 return Flags & (1 << MCID::Pseudo); in isPseudo()
228 return Flags & (1 << MCID::Return); in isReturn()
233 return Flags & (1 << MCID::Call); in isCall()
240 return Flags & (1 << MCID::Barrier); in isBarrier()
250 return Flags & (1 << MCID::Terminator); in isTerminator()
258 return Flags & (1 << MCID::Branch); in isBranch()
264 return Flags & (1 << MCID::IndirectBranch); in isIndirectBranch()
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/trueos/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/
HDHexagonMCInst.cpp33 const uint64_t F = MCID->TSFlags; in getType()
40 return (!MCID->isPseudo() && in isCanon()
52 const uint64_t F = MCID->TSFlags; in isSolo()
58 const uint64_t F = MCID->TSFlags; in isNewValue()
64 const uint64_t F = MCID->TSFlags; in hasNewValue()
70 const uint64_t F = MCID->TSFlags; in getNewValue()
118 const uint64_t F = MCID->TSFlags; in isExtended()
124 const uint64_t F = MCID->TSFlags; in isExtendable()
130 const uint64_t F = MCID->TSFlags; in getBitCount()
136 const uint64_t F = MCID->TSFlags; in getCExtOpNum()
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HDHexagonMCInst.h27 const MCInstrDesc *MCID; variable
34 MCInst(), MCID(0), packetStart(0), packetEnd(0) {}; in HexagonMCInst()
36 MCInst(), MCID(&mcid), packetStart(0), packetEnd(0) {}; in HexagonMCInst()
50 void setDesc(const MCInstrDesc& mcid) { MCID = &mcid; }; in setDesc()
51 const MCInstrDesc& getDesc(void) const { return *MCID; }; in getDesc()
/trueos/contrib/llvm/include/llvm/CodeGen/
HDMachineInstr.h70 const MCInstrDesc *MCID; // Instruction descriptor.
112 MachineInstr(MachineFunction&, const MCInstrDesc &MCID,
257 const MCInstrDesc &getDesc() const { return *MCID; }
261 int getOpcode() const { return MCID->Opcode; }
329 return hasProperty(MCID::Variadic, Type);
335 return hasProperty(MCID::HasOptionalDef, Type);
342 return hasProperty(MCID::Pseudo, Type);
346 return hasProperty(MCID::Return, Type);
350 return hasProperty(MCID::Call, Type);
357 return hasProperty(MCID::Barrier, Type);
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HDMachineInstrBuilder.h225 const MCInstrDesc &MCID) { in BuildMI() argument
226 return MachineInstrBuilder(MF, MF.CreateMachineInstr(MCID, DL)); in BuildMI()
234 const MCInstrDesc &MCID, in BuildMI() argument
236 return MachineInstrBuilder(MF, MF.CreateMachineInstr(MCID, DL)) in BuildMI()
247 const MCInstrDesc &MCID, in BuildMI() argument
250 MachineInstr *MI = MF.CreateMachineInstr(MCID, DL); in BuildMI()
258 const MCInstrDesc &MCID, in BuildMI() argument
261 MachineInstr *MI = MF.CreateMachineInstr(MCID, DL); in BuildMI()
269 const MCInstrDesc &MCID, in BuildMI() argument
273 return BuildMI(BB, MII, DL, MCID, DestReg); in BuildMI()
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/trueos/contrib/llvm/lib/Target/ARM/
HDARMCodeEmitter.cpp99 const MCInstrDesc &MCID,
105 const MCInstrDesc &MCID) const;
463 const MCInstrDesc &MCID = MI.getDesc(); in getMachineOpValue() local
465 unsigned Reloc = ((MCID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm) in getMachineOpValue()
776 const MCInstrDesc &MCID = MI.getDesc(); in emitLEApcrelJTInstruction() local
785 Binary |= getAddrModeSBit(MI, MCID); in emitLEApcrelJTInstruction()
929 const MCInstrDesc &MCID, in getMachineSoRegOpValue() argument
999 const MCInstrDesc &MCID) const { in getAddrModeSBit()
1000 for (unsigned i = MI.getNumOperands(), e = MCID.getNumOperands(); i >= e;--i){ in getAddrModeSBit()
1011 const MCInstrDesc &MCID = MI.getDesc(); in emitDataProcessingInstruction() local
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HDThumb2SizeReduction.cpp213 static bool HasImplicitCPSRDef(const MCInstrDesc &MCID) { in HasImplicitCPSRDef() argument
214 for (const uint16_t *Regs = MCID.getImplicitDefs(); *Regs; ++Regs) in HasImplicitCPSRDef()
551 const MCInstrDesc &MCID = MI->getDesc(); in ReduceSpecial() local
552 if (MCID.hasOptionalDef() && in ReduceSpecial()
553 MI->getOperand(MCID.getNumOperands()-1).getReg() == ARM::CPSR) in ReduceSpecial()
700 const MCInstrDesc &MCID = MI->getDesc(); in ReduceTo2Addr() local
701 if (MCID.hasOptionalDef()) { in ReduceTo2Addr()
702 unsigned NumOps = MCID.getNumOperands(); in ReduceTo2Addr()
728 unsigned NumOps = MCID.getNumOperands(); in ReduceTo2Addr()
730 if (i < NumOps && MCID.OpInfo[i].isOptionalDef()) in ReduceTo2Addr()
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HDARMHazardRecognizer.cpp22 const MCInstrDesc &MCID = MI->getDesc(); in hasRAWHazard() local
23 unsigned Domain = MCID.TSFlags & ARMII::DomainMask; in hasRAWHazard()
26 unsigned Opcode = MCID.getOpcode(); in hasRAWHazard()
43 const MCInstrDesc &MCID = MI->getDesc(); in getHazardType() local
44 if (LastMI && (MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainGeneral) { in getHazardType()
HDMLxExpansionPass.cpp186 const MCInstrDesc &MCID = MI->getDesc(); in hasRAWHazard() local
187 unsigned Domain = MCID.TSFlags & ARMII::DomainMask; in hasRAWHazard()
190 unsigned Opcode = MCID.getOpcode(); in hasRAWHazard()
343 const MCInstrDesc &MCID = MI->getDesc(); in ExpandFPMLxInstructions() local
351 unsigned Domain = MCID.TSFlags & ARMII::DomainMask; in ExpandFPMLxInstructions()
361 if (!TII->isFpMLxInstruction(MCID.getOpcode(), in ExpandFPMLxInstructions()
HDThumb1RegisterInfo.cpp241 const MCInstrDesc &MCID = TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3); in emitThumbRegPlusImmediate() local
243 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, MCID, DestReg) in emitThumbRegPlusImmediate()
291 const MCInstrDesc &MCID = TII.get(ExtraOpc); in emitThumbRegPlusImmediate() local
292 AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, MCID, DestReg)) in emitThumbRegPlusImmediate()
319 const MCInstrDesc &MCID = TII.get(ARM::tRSB); in emitThumbConstant() local
320 AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, MCID, DestReg)) in emitThumbConstant()
HDThumb2ITBlockPass.cpp141 const MCInstrDesc &MCID = MI->getDesc(); in MoveCopyOutOfITBlock() local
143 MI->getOperand(MCID.getNumOperands() - 1).getReg() == ARM::CPSR) in MoveCopyOutOfITBlock()
/trueos/contrib/llvm/lib/CodeGen/
HDScoreboardHazardRecognizer.cpp128 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in getHazardType() local
129 if (MCID == NULL) { in getHazardType()
133 unsigned idx = MCID->getSchedClass(); in getHazardType()
184 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in EmitInstruction() local
185 assert(MCID && "The scheduler must filter non-machineinstrs"); in EmitInstruction()
186 if (DAG->TII->isZeroCost(MCID->Opcode)) in EmitInstruction()
193 unsigned idx = MCID->getSchedClass(); in EmitInstruction()
HDTargetInstrInfo.cpp40 TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum, in getRegClass() argument
43 if (OpNum >= MCID.getNumOperands()) in getRegClass()
46 short RegClass = MCID.OpInfo[OpNum].RegClass; in getRegClass()
47 if (MCID.OpInfo[OpNum].isLookupPtrRegClass()) in getRegClass()
121 const MCInstrDesc &MCID = MI->getDesc(); in commuteInstruction() local
122 bool HasDef = MCID.getNumDefs(); in commuteInstruction()
186 const MCInstrDesc &MCID = MI->getDesc(); in findCommutedOpIndices() local
187 if (!MCID.isCommutable()) in findCommutedOpIndices()
191 SrcOpIdx1 = MCID.getNumDefs(); in findCommutedOpIndices()
221 const MCInstrDesc &MCID = MI->getDesc(); in PredicateInstruction() local
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HDMachineInstr.cpp521 if (MCID->ImplicitDefs) in addImplicitDefUseOperands()
522 for (const uint16_t *ImpDefs = MCID->getImplicitDefs(); *ImpDefs; ++ImpDefs) in addImplicitDefUseOperands()
524 if (MCID->ImplicitUses) in addImplicitDefUseOperands()
525 for (const uint16_t *ImpUses = MCID->getImplicitUses(); *ImpUses; ++ImpUses) in addImplicitDefUseOperands()
534 : MCID(&tid), Parent(0), Operands(0), NumOperands(0), in MachineInstr()
538 if (unsigned NumOps = MCID->getNumOperands() + in MachineInstr()
539 MCID->getNumImplicitDefs() + MCID->getNumImplicitUses()) { in MachineInstr()
551 : MCID(&MI.getDesc()), Parent(0), Operands(0), NumOperands(0), in MachineInstr()
623 assert(MCID && "Cannot add operands before providing an instr descriptor"); in addOperand()
655 assert((isImpReg || Op.isRegMask() || MCID->isVariadic() || in addOperand()
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HDMachineVerifier.cpp774 const MCInstrDesc &MCID = MI->getDesc(); in visitMachineInstrBefore() local
775 if (MI->getNumOperands() < MCID.getNumOperands()) { in visitMachineInstrBefore()
777 *OS << MCID.getNumOperands() << " operands expected, but " in visitMachineInstrBefore()
818 const MCInstrDesc &MCID = MI->getDesc(); in visitMachineOperand() local
821 if (MONum < MCID.getNumDefs()) { in visitMachineOperand()
822 const MCOperandInfo &MCOI = MCID.OpInfo[MONum]; in visitMachineOperand()
829 } else if (MONum < MCID.getNumOperands()) { in visitMachineOperand()
830 const MCOperandInfo &MCOI = MCID.OpInfo[MONum]; in visitMachineOperand()
834 !(MI->isVariadic() && MONum == MCID.getNumOperands()-1)) { in visitMachineOperand()
841 int TiedTo = MCID.getOperandConstraint(MONum, MCOI::TIED_TO); in visitMachineOperand()
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HDPeepholeOptimizer.cpp503 const MCInstrDesc &MCID = MI->getDesc(); in isLoadFoldable() local
504 if (MCID.getNumDefs() != 1) in isLoadFoldable()
523 const MCInstrDesc &MCID = MI->getDesc(); in isMoveImmediate() local
526 if (MCID.getNumDefs() != 1) in isMoveImmediate()
/trueos/contrib/llvm/lib/Target/PowerPC/
HDPPCHazardRecognizers.cpp27 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in EmitInstruction() local
28 if (!MCID) in EmitInstruction()
94 const MCInstrDesc &MCID = TM.getInstrInfo()->get(Opcode); in GetInstrType() local
96 isLoad = MCID.mayLoad(); in GetInstrType()
97 isStore = MCID.mayStore(); in GetInstrType()
99 uint64_t TSFlags = MCID.TSFlags; in GetInstrType()
/trueos/contrib/llvm/lib/Target/SystemZ/
HDSystemZInstrBuilder.h31 const MCInstrDesc &MCID = MI->getDesc(); in addFrameReference() local
33 if (MCID.mayLoad()) in addFrameReference()
35 if (MCID.mayStore()) in addFrameReference()
HDSystemZInstrInfo.cpp195 const MCInstrDesc &MCID = MI->getDesc(); in isSimpleMove() local
196 if ((MCID.TSFlags & Flag) && in isSimpleMove()
624 const MCInstrDesc &MCID = MI->getDesc(); in isSimpleBD12Move() local
625 return ((MCID.TSFlags & Flag) && in isSimpleBD12Move()
1123 const MCInstrDesc &MCID = get(Opcode); in getOpcodeForOffset() local
1124 int64_t Offset2 = (MCID.TSFlags & SystemZII::Is128Bit ? Offset + 8 : Offset); in getOpcodeForOffset()
1142 if (MCID.TSFlags & SystemZII::Has20BitOffset) in getOpcodeForOffset()
/trueos/contrib/llvm/lib/CodeGen/SelectionDAG/
HDScheduleDAGFast.cpp257 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); in CopyAndMoveSuccessors() local
258 for (unsigned i = 0; i != MCID.getNumOperands(); ++i) { in CopyAndMoveSuccessors()
259 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) { in CopyAndMoveSuccessors()
264 if (MCID.isCommutable()) in CopyAndMoveSuccessors()
435 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); in getPhysicalRegisterVT() local
436 assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!"); in getPhysicalRegisterVT()
437 unsigned NumRes = MCID.getNumDefs(); in getPhysicalRegisterVT()
438 for (const uint16_t *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) { in getPhysicalRegisterVT()
513 const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode()); in DelayForLiveRegsBottomUp() local
514 if (!MCID.ImplicitDefs) in DelayForLiveRegsBottomUp()
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HDScheduleDAGRRList.cpp1002 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); in CopyAndMoveSuccessors() local
1003 for (unsigned i = 0; i != MCID.getNumOperands(); ++i) { in CopyAndMoveSuccessors()
1004 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) { in CopyAndMoveSuccessors()
1009 if (MCID.isCommutable()) in CopyAndMoveSuccessors()
1192 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); in getPhysicalRegisterVT() local
1193 assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!"); in getPhysicalRegisterVT()
1194 unsigned NumRes = MCID.getNumDefs(); in getPhysicalRegisterVT()
1195 for (const uint16_t *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) { in getPhysicalRegisterVT()
1318 const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode()); in DelayForLiveRegsBottomUp() local
1319 if (!MCID.ImplicitDefs) in DelayForLiveRegsBottomUp()
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HDInstrEmitter.cpp323 const MCInstrDesc &MCID = MIB->getDesc(); in AddRegisterOperand() local
324 bool isOptDef = IIOpNum < MCID.getNumOperands() && in AddRegisterOperand()
325 MCID.OpInfo[IIOpNum].isOptionalDef(); in AddRegisterOperand()
360 bool isTied = MCID.getOperandConstraint(Idx, MCOI::TIED_TO) != -1; in AddRegisterOperand()
839 const MCInstrDesc &MCID = TII->get(F->getMachineOpcode()); in EmitMachineNode() local
840 UsedRegs.append(MCID.getImplicitUses(), in EmitMachineNode()
841 MCID.getImplicitUses() + MCID.getNumImplicitUses()); in EmitMachineNode()
HDScheduleDAGSDNodes.cpp304 const MCInstrDesc &MCID = TII->get(Opc); in ClusterNodes() local
305 if (MCID.mayLoad()) in ClusterNodes()
439 const MCInstrDesc &MCID = TII->get(Opc); in AddSchedEdges() local
440 for (unsigned i = 0; i != MCID.getNumOperands(); ++i) { in AddSchedEdges()
441 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) { in AddSchedEdges()
446 if (MCID.isCommutable()) in AddSchedEdges()
/trueos/contrib/llvm/lib/Target/X86/
HDX86InstrBuilder.h152 const MCInstrDesc &MCID = MI->getDesc(); variable
154 if (MCID.mayLoad())
156 if (MCID.mayStore())
/trueos/contrib/llvm/lib/Target/Mips/
HDMipsInstrInfo.cpp102 const MCInstrDesc &MCID = get(Opc); in BuildCondBr() local
103 MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID); in BuildCondBr()

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