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Searched refs:LoadLatency (Results 1 – 17 of 17) sorted by relevance

/trueos/contrib/llvm/include/llvm/MC/
HDMCSchedule.h161 unsigned LoadLatency; variable
196 LoadLatency(DefaultLoadLatency), in MCSchedModel()
212 IssueWidth(iw), MicroOpBufferSize(mbs), LoadLatency(ll), HighLatency(hl), in MCSchedModel()
/trueos/contrib/llvm/lib/Target/Hexagon/
HDHexagonSchedule.td58 let LoadLatency = 1;
HDHexagonScheduleV4.td69 let LoadLatency = 1;
/trueos/contrib/llvm/lib/Target/PowerPC/
HDPPCScheduleA2.td148 let LoadLatency = 6; // Optimistic load latency assuming bypass.
HDPPCScheduleG5.td102 let LoadLatency = 3; // Optimistic load latency assuming bypass.
HDPPCScheduleE500mc.td262 let LoadLatency = 5; // Optimistic load latency assuming bypass.
HDPPCScheduleE5500.td305 let LoadLatency = 6; // Optimistic load latency assuming bypass.
/trueos/contrib/llvm/lib/Target/X86/
HDX86SchedSandyBridge.td21 let LoadLatency = 4;
HDX86SchedHaswell.td20 let LoadLatency = 4;
HDX86Schedule.td599 let LoadLatency = 4;
HDX86ScheduleAtom.td535 let LoadLatency = 3; // Expected cycles, may be overriden by OperandCycles.
HDX86ScheduleSLM.td664 let LoadLatency = 3; // Expected cycles, may be overriden by OperandCycles.
/trueos/contrib/llvm/include/llvm/Target/
HDTargetSchedule.td73 // Target hooks allow subtargets to associate LoadLatency and
82 int LoadLatency = -1; // Cycles for loads to access the cache.
/trueos/contrib/llvm/lib/CodeGen/
HDTargetInstrInfo.cpp669 return SchedModel->LoadLatency; in defaultDefLatency()
/trueos/contrib/llvm/lib/Target/ARM/
HDARMScheduleA8.td1069 let LoadLatency = 2; // Optimistic load latency assuming bypass.
HDARMScheduleSwift.td1080 let LoadLatency = 3;
HDARMScheduleA9.td1891 let LoadLatency = 2; // Optimistic load latency assuming bypass.