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Searched refs:LR (Results 1 – 25 of 134) sorted by relevance

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/trueos/contrib/llvm/lib/CodeGen/
HDLiveRangeCalc.h80 LiveRange &LR; member
94 LiveInBlock(LiveRange &LR, MachineDomTreeNode *node, SlotIndex kill) in LiveInBlock()
95 : LR(LR), DomNode(node), Kill(kill), Value(0) {} in LiveInBlock()
114 bool findReachingDefs(LiveRange &LR, MachineBasicBlock &KillMBB,
162 void extend(LiveRange &LR, SlotIndex Kill, unsigned PhysReg = 0);
167 void createDeadDefs(LiveRange &LR, unsigned Reg);
178 void extendToUses(LiveRange &LR, unsigned Reg);
218 void addLiveInBlock(LiveRange &LR,
221 LiveIn.push_back(LiveInBlock(LR, DomNode, Kill));
HDLiveRangeCalc.cpp39 void LiveRangeCalc::createDeadDefs(LiveRange &LR, unsigned Reg) { in createDeadDefs() argument
58 LR.createDeadDef(Idx, *Alloc); in createDeadDefs()
63 void LiveRangeCalc::extendToUses(LiveRange &LR, unsigned Reg) { in extendToUses() argument
102 extend(LR, Idx, Reg); in extendToUses()
128 Updater.setDest(&I->LR); in updateLiveIns()
135 void LiveRangeCalc::extend(LiveRange &LR, SlotIndex Kill, unsigned PhysReg) { in extend() argument
144 if (LR.extendInBlock(Indexes->getMBBStartIdx(KillMBB), Kill)) in extend()
151 if (findReachingDefs(LR, *KillMBB, Kill, PhysReg)) in extend()
170 bool LiveRangeCalc::findReachingDefs(LiveRange &LR, MachineBasicBlock &KillMBB, in findReachingDefs() argument
219 VNInfo *VNI = LR.extendInBlock(Start, End); in findReachingDefs()
[all …]
HDMachineVerifier.cpp217 const LiveRange &LR);
219 const LiveRange &LR);
432 const LiveRange &LR) { in report() argument
434 *OS << "- liverange: " << LR << "\n"; in report()
438 const LiveRange &LR) { in report() argument
440 *OS << "- liverange: " << LR << "\n"; in report()
1011 if (const LiveRange *LR = LiveInts->getCachedRegUnit(*Units)) { in checkLiveness() local
1012 LiveQueryResult LRQ = LR->Query(UseIdx); in checkLiveness()
1016 << ' ' << *LR << '\n'; in checkLiveness()
1020 *OS << PrintRegUnit(*Units, TRI) << ' ' << *LR << '\n'; in checkLiveness()
[all …]
HDLiveIntervalAnalysis.cpp143 if (LiveRange *LR = RegUnitRanges[i]) in print() local
144 OS << PrintRegUnit(i, TRI) << ' ' << *LR << '\n'; in print()
234 void LiveIntervals::computeRegUnitRange(LiveRange &LR, unsigned Unit) { in computeRegUnitRange() argument
247 LRCalc->createDeadDefs(LR, *Supers); in computeRegUnitRange()
258 LRCalc->extendToUses(LR, Reg); in computeRegUnitRange()
291 LiveRange *LR = RegUnitRanges[Unit]; in computeLiveInRegUnits() local
292 if (!LR) { in computeLiveInRegUnits()
293 LR = RegUnitRanges[Unit] = new LiveRange(); in computeLiveInRegUnits()
296 VNInfo *VNI = LR->createDeadDef(Begin, getVNInfoAllocator()); in computeLiveInRegUnits()
444 void LiveIntervals::extendToIndices(LiveRange &LR, in extendToIndices() argument
[all …]
HDLiveInterval.cpp685 if (LR) in print()
686 OS << "Clean updater: " << *LR << '\n'; in print()
691 assert(LR && "Can't have null LR in dirty updater."); in print()
695 for (LiveRange::const_iterator I = LR->begin(); I != WriteI; ++I) in print()
701 for (LiveRange::const_iterator I = ReadI, E = LR->end(); I != E; ++I) in print()
724 assert(LR && "Cannot add to a null destination"); in add()
732 WriteI = ReadI = LR->begin(); in add()
739 LiveRange::iterator E = LR->end(); in add()
746 ReadI = WriteI = LR->find(Seg.start); in add()
779 if (WriteI != LR->begin() && coalescable(WriteI[-1], Seg)) { in add()
[all …]
HDRegAllocFast.cpp233 void RAFast::addKillFlag(const LiveReg &LR) { in addKillFlag() argument
234 if (!LR.LastUse) return; in addKillFlag()
235 MachineOperand &MO = LR.LastUse->getOperand(LR.LastOpNum); in addKillFlag()
236 if (MO.isUse() && !LR.LastUse->isRegTiedToDefOperand(LR.LastOpNum)) { in addKillFlag()
237 if (MO.getReg() == LR.PhysReg) in addKillFlag()
240 LR.LastUse->addRegisterKilled(LR.PhysReg, TRI, true); in addKillFlag()
277 LiveReg &LR = *LRI; in spillVirtReg() local
278 assert(PhysRegState[LR.PhysReg] == LRI->VirtReg && "Broken RegState mapping"); in spillVirtReg()
280 if (LR.Dirty) { in spillVirtReg()
283 bool SpillKill = LR.LastUse != MI; in spillVirtReg()
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HDRegisterPressure.cpp503 const LiveRange *LR = getLiveRange(Reg); in recede() local
504 if (LR) { in recede()
505 LiveQueryResult LRQ = LR->Query(SlotIdx); in recede()
523 const LiveRange *LR = getLiveRange(Reg); in recede() local
524 if (LR) { in recede()
525 LiveQueryResult LRQ = LR->Query(SlotIdx); in recede()
582 const LiveRange *LR = getLiveRange(Reg); in advance() local
583 lastUse = LR && LR->Query(SlotIdx).isKill(); in advance()
717 const LiveRange *LR = getLiveRange(Reg); in bumpUpwardPressure() local
718 if (LR) { in bumpUpwardPressure()
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HDInterferenceCache.cpp207 LiveRange *LR = RegUnits[i].Fixed; in update() local
208 if (I == LR->end() || I->start >= Stop) in update()
210 I = LR->advanceTo(I, Stop); in update()
211 bool Backup = I == LR->end() || I->start >= Stop; in update()
HDExecutionDepsFix.cpp648 const LiveReg &LR = LiveRegs[rx]; in visitSoftInstr() local
650 if (!LR.Value->getCommonDomains(available)) { in visitSoftInstr()
658 if (LR.Def < i->Def) { in visitSoftInstr()
660 Regs.insert(i, LR); in visitSoftInstr()
664 Regs.push_back(LR); in visitSoftInstr()
HDLiveDebugVariables.cpp229 LiveRange *LR, const VNInfo *VNI,
498 LiveRange *LR, const VNInfo *VNI, in extendDef() argument
512 if (LR && VNI) { in extendDef()
513 LiveInterval::Segment *Segment = LR->getSegmentContaining(Start); in extendDef()
672 LiveRange *LR = &LIS.getRegUnit(Unit); in computeIntervals() local
673 const VNInfo *VNI = LR->getVNInfoAt(Idx); in computeIntervals()
675 extendDef(Idx, LocNo, LR, VNI, 0, LIS, MDT, UVS); in computeIntervals()
HDLiveRangeEdit.cpp265 if (LiveRange *LR = LIS.getCachedRegUnit(*Units)) { in eliminateDeadDef() local
266 if (VNInfo *VNI = LR->getVNInfoAt(Idx)) in eliminateDeadDef()
267 LR->removeValNo(VNI); in eliminateDeadDef()
/trueos/contrib/llvm/include/llvm/CodeGen/
HDLiveIntervalAnalysis.h163 void extendToIndices(LiveRange &LR, ArrayRef<SlotIndex> Indices);
209 bool isLiveInToMBB(const LiveRange &LR, in isLiveInToMBB() argument
211 return LR.liveAt(getMBBStartIdx(mbb)); in isLiveInToMBB()
214 bool isLiveOutOfMBB(const LiveRange &LR, in isLiveOutOfMBB() argument
216 return LR.liveAt(getMBBEndIdx(mbb).getPrevSlot()); in isLiveOutOfMBB()
368 LiveRange *LR = RegUnitRanges[Unit]; in getRegUnit() local
369 if (!LR) { in getRegUnit()
371 RegUnitRanges[Unit] = LR = new LiveRange(); in getRegUnit()
372 computeRegUnitRange(*LR, Unit); in getRegUnit()
374 return *LR; in getRegUnit()
HDLiveInterval.h521 inline raw_ostream &operator<<(raw_ostream &OS, const LiveRange &LR) {
522 LR.print(OS);
591 LiveRange *LR; variable
601 LiveRangeUpdater(LiveRange *lr = 0) : LR(lr) {} in LR() function
624 if (LR != lr && isDirty()) in setDest()
626 LR = lr; in setDest()
630 LiveRange *getDest() const { return LR; } in getDest()
/trueos/contrib/llvm/tools/clang/lib/StaticAnalyzer/Checkers/
HDPointerArithChecker.cpp44 const MemRegion *LR = LV.getAsRegion(); in checkPreStmt() local
46 if (!LR || !RV.isConstant()) in checkPreStmt()
51 if (isa<VarRegion>(LR) || isa<CodeTextRegion>(LR) || in checkPreStmt()
52 isa<CompoundLiteralRegion>(LR)) { in checkPreStmt()
HDPointerSubChecker.cpp47 const MemRegion *LR = LV.getAsRegion(); in checkPreStmt() local
50 if (!(LR && RR)) in checkPreStmt()
53 const MemRegion *BaseLR = LR->getBaseRegion(); in checkPreStmt()
/trueos/sys/arm/arm/
HDdb_trace.c78 #define LR 14 macro
310 state->registers[FP], state->registers[SP], state->registers[LR], in db_unwind_exec_insn()
349 state->registers[PC] = state->registers[LR]; in db_unwind_tab()
403 state->registers[LR]); in db_stack_trace_cmd()
404 db_printsym(state->registers[LR], DB_STGY_PROC); in db_stack_trace_cmd()
411 ~((1 << SP) | (1 << FP) | (1 << LR) | (1 << PC)); in db_stack_trace_cmd()
608 state.registers[LR] = ctx->pcb_regs.sf_lr; in db_trace_thread()
632 state.registers[LR] = (uint32_t)__builtin_return_address(0); in db_trace_self()
/trueos/contrib/llvm/lib/Target/ARM/
HDARMCallingConv.td194 def CSR_AAPCS : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6, R5, R4,
201 def CSR_AAPCS_ThisReturn : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6,
207 def CSR_iOS : CalleeSavedRegs<(add LR, R7, R6, R5, R4, (sub CSR_AAPCS, R9))>;
209 def CSR_iOS_ThisReturn : CalleeSavedRegs<(add LR, R7, R6, R5, R4,
217 // For most interrupts, all registers except SP and LR are shared with
218 // user-space. We mark LR to be saved anyway, since this is what the ARM backend
220 def CSR_GenericInt : CalleeSavedRegs<(add LR, (sequence "R%u", 12, 0))>;
223 // of R8-R12, in addition to SP and LR. As before, mark LR for saving too.
228 def CSR_FIQ : CalleeSavedRegs<(add LR, R11, (sequence "R%u", 7, 0))>;
HDARMFrameLowering.cpp186 case ARM::LR: in emitPrologue()
612 if (Reg == ARM::LR) { in emitPushInst()
680 if (Reg == ARM::LR && !isTailCall && !isVarArg && !isInterrupt && in emitPopInst()
715 Regs[0] = ARM::LR; in emitPopInst()
1186 MRI.setPhysRegUsed(ARM::LR); in processFunctionBeforeCalleeSavedScan()
1224 if (Reg == ARM::LR) in processFunctionBeforeCalleeSavedScan()
1232 case ARM::LR: in processFunctionBeforeCalleeSavedScan()
1255 case ARM::LR: in processFunctionBeforeCalleeSavedScan()
1306 MRI.setPhysRegUsed(ARM::LR); in processFunctionBeforeCalleeSavedScan()
1310 (unsigned)ARM::LR); in processFunctionBeforeCalleeSavedScan()
[all …]
HDARMRegisterInfo.td76 def LR : ARMReg<14, "lr">, DwarfRegNum<[14]>;
194 SP, LR, PC)> {
195 // Allocate LR as the first CSR since it is always saved anyway.
200 let AltOrders = [(add LR, GPR), (trunc GPR, 8)];
210 let AltOrders = [(add LR, GPRnopc), (trunc GPRnopc, 8)];
220 let AltOrders = [(add LR, GPRnopc), (trunc GPRnopc, 8)];
238 let AltOrders = [(add LR, rGPR), (trunc rGPR, 8)];
/trueos/contrib/llvm/lib/Target/XCore/
HDXCoreFrameLowering.cpp127 MBB.addLiveIn(XCore::LR); in emitPrologue()
142 unsigned Reg = MRI->getDwarfRegNum(XCore::LR, true); in emitPrologue()
149 storeToStack(MBB, MBBI, XCore::LR, LRSpillOffset + FrameSize*4, dl, TII); in emitPrologue()
150 MBB.addLiveIn(XCore::LR); in emitPrologue()
155 unsigned Reg = MRI->getDwarfRegNum(XCore::LR, true); in emitPrologue()
245 loadFromStack(MBB, MBBI, XCore::LR, LRSpillOffset, dl, TII); in emitEpilogue()
389 bool LRUsed = MF.getRegInfo().isPhysRegUsed(XCore::LR); in processFunctionBeforeCalleeSavedScan()
393 MF.getRegInfo().setPhysRegUnused(XCore::LR); in processFunctionBeforeCalleeSavedScan()
HDXCoreRegisterInfo.td41 def LR : Ri<15, "lr">, DwarfRegNum<[15]>;
57 R11, CP, DP, SP, LR)> {
HDXCoreRegisterInfo.cpp41 : XCoreGenRegisterInfo(XCore::LR) { in XCoreRegisterInfo()
66 XCore::R8, XCore::R9, XCore::R10, XCore::LR, in getCalleeSavedRegs()
79 Reserved.set(XCore::LR); in getReservedRegs()
/trueos/sys/dev/ixgbe/
HDREADME53 LR Modules
54 Intel DUAL RATE 1G/10G SFP+ LR (bailed) FTLX1471D3BCV-IT
55 Intel DUAL RATE 1G/10G SFP+ LR (bailed) AFCT-701SDZ-IN2
56 Intel DUAL RATE 1G/10G SFP+ LR (bailed) AFCT-701SDDZ-IN1
65 Finisar SFP+ LR bailed, 10g single rate FTLX8571D3BCV-IT
69 Finisar DUAL RATE 1G/10G SFP+ LR (No Bail) FTLX1471D3QCV-IT
70 Avago DUAL RATE 1G/10G SFP+ LR (No Bail) AFCT-701SDZ-IN1
96 - LAN on Motherboard (LOMs) may support DA, SR, or LR modules. Other module
106 Finisar SFP+ LR bailed, 10g single rate FTLX1471D3BCL
/trueos/contrib/llvm/include/llvm/ADT/
HDImmutableSet.h502 TreeTy *LR = getRight(L); in balanceTree() local
504 if (getHeight(LL) >= getHeight(LR)) in balanceTree()
505 return createNode(LL, L, createNode(LR,V,R)); in balanceTree()
507 assert(!isEmpty(LR) && "LR cannot be empty because it has a height >= 1"); in balanceTree()
509 TreeTy *LRL = getLeft(LR); in balanceTree()
510 TreeTy *LRR = getRight(LR); in balanceTree()
512 return createNode(createNode(LL,L,LRL), LR, createNode(LRR,V,R)); in balanceTree()
/trueos/contrib/byacc/package/debian/
HDcontrol14 specification from a file and generates an LR(1) parser for it. The

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