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Searched refs:GPR (Results 1 – 25 of 74) sorted by relevance

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/trueos/contrib/llvm/lib/Target/ARM/
HDARMInstrInfo.td348 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
546 let MIOperandInfo = (ops GPR, i32imm);
557 let MIOperandInfo = (ops GPR, GPR, i32imm);
568 let MIOperandInfo = (ops GPR, i32imm);
792 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
813 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
867 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
884 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
885 // the GPR is purely vestigal at this point.
906 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
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HDARMInstrVFP.td130 AXDI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
138 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs,
147 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs,
158 AXSI4<(outs), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, variable_ops),
170 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs,
183 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs,
233 AXXI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
240 AXXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
247 AXXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
528 (i32 (COPY_TO_REGCLASS (VCVTBSH SPR:$a), GPR))>;
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HDARMInstrThumb2.td157 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
186 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
197 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
207 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
232 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
271 let MIOperandInfo = (ops GPR:$base, rGPR:$offsreg, i32imm:$offsimm);
279 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
285 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
776 (outs GPRnopc:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi,
778 [(set GPRnopc:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]>,
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HDARMInstrThumb.td244 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
337 def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "",
338 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>,
394 def tADDrSP : T1pI<(outs GPR:$Rdn), (ins GPRsp:$sp, GPR:$Rn), IIC_iALUr,
406 def tADDspr : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, GPR:$Rm), IIC_iALUr,
423 def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>,
440 (tBX GPR:$Rm, pred:$p)>, Sched<[WriteBr]>;
478 def tBLXr : TI<(outs), (ins pred:$p, GPR:$func), IIC_Br,
480 [(ARMtcall GPR:$func)]>,
543 (tBX GPR:$dst, (ops 14, zero_reg))>,
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/trueos/contrib/gcc/config/rs6000/
HDsync.md53 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
54 (unspec_volatile:GPR
55 [(match_operand:GPR 1 "memory_operand" "Z")] UNSPECV_LL))]
63 (set (match_operand:GPR 1 "memory_operand" "=Z")
64 (match_operand:GPR 2 "gpc_reg_operand" "r"))]
70 [(set (match_operand:GPR 0 "gpc_reg_operand" "=&r")
71 (match_operand:GPR 1 "memory_operand" "+Z"))
73 (unspec:GPR
74 [(match_operand:GPR 2 "reg_or_short_operand" "rI")
75 (match_operand:GPR 3 "gpc_reg_operand" "r")]
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/trueos/contrib/gcc/config/mips/
HDmips.md405 ;; This mode macro allows 32-bit and 64-bit GPR patterns to be generated
407 (define_mode_macro GPR [SI (DI "TARGET_64BIT")])
431 ;; In GPR templates, a string like "<d>subu" will expand to "subu" in the
442 ;; Mode attributes for GPR loads and stores.
635 [(trap_if (match_operator:GPR 0 "trap_comparison_operator"
636 [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
637 (match_operand:GPR 2 "arith_operand" "dI")])
661 [(set (match_operand:GPR 0 "register_operand")
662 (plus:GPR (match_operand:GPR 1 "register_operand")
663 (match_operand:GPR 2 "arith_operand")))]
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/trueos/contrib/gcc/config/s390/
HDs390.md221 ;; These mode macros allow 31-bit and 64-bit GPR patterns to be generated
223 (define_mode_macro GPR [(DI "TARGET_64BIT") SI])
273 ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode
303 ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode
307 ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode
317 ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode
343 (compare:CC (match_operand:GPR 0 "register_operand" "")
344 (match_operand:GPR 1 "general_operand" "")))]
434 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,m")
435 (match_operand:GPR 1 "const0_operand" "")))
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/trueos/contrib/llvm/patches/
HDpatch-r275759-clang-r221170-ppc-vaarg.diff77 + llvm::Value *GPR = Builder.CreateLoad(GPRPtr, false, "gpr");
78 + // Align GPR when TY is i64.
80 + llvm::Value *GPRAnd = Builder.CreateAnd(GPR, Builder.getInt8(1));
82 + llvm::Value *GPRPlusOne = Builder.CreateAdd(GPR, Builder.getInt8(1));
83 + GPR = Builder.CreateSelect(CC64, GPRPlusOne, GPR);
91 + llvm::Value *CC = Builder.CreateICmpULT(isInt ? GPR : FPR,
94 + llvm::Value *RegConstant = Builder.CreateMul(isInt ? GPR : FPR,
112 + // Increase the GPR/FPR indexes.
114 + GPR = Builder.CreateAdd(GPR, Builder.getInt8(isI64 ? 2 : 1));
115 + Builder.CreateStore(GPR, GPRPtr);
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HDpatch-r271024-llvm-r216989-r216990-fix-movw-armv6.diff21 def : ARMPat<(ARMadde GPR:$src, so_imm_not:$imm, CPSR),
22 (SBCri GPR:$src, so_imm_not:$imm)>;
23 def : ARMPat<(ARMadde GPR:$src, imm0_65535_neg:$imm, CPSR),
24 - (SBCrr GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>;
25 + (SBCrr GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>,
/trueos/contrib/llvm/tools/lldb/source/Plugins/Process/Utility/
HDRegisterContextDarwin_x86_64.h62 struct GPR struct
138 GPRWordCount = sizeof(GPR)/sizeof(uint32_t),
150 GPR gpr;
237 DoReadGPR (lldb::tid_t tid, int flavor, GPR &gpr) = 0;
246 DoWriteGPR (lldb::tid_t tid, int flavor, const GPR &gpr) = 0;
HDRegisterContextDarwin_i386.h63 struct GPR struct
134 GPRWordCount = sizeof(GPR)/sizeof(uint32_t),
146 GPR gpr;
233 DoReadGPR (lldb::tid_t tid, int flavor, GPR &gpr) = 0;
242 DoWriteGPR (lldb::tid_t tid, int flavor, const GPR &gpr) = 0;
HDRegisterContextDarwin_arm.h110 struct GPR struct
177 GPRWordCount = sizeof(GPR)/sizeof(uint32_t),
190 GPR gpr;
288 DoReadGPR (lldb::tid_t tid, int flavor, GPR &gpr) in DoReadGPR()
303 DoWriteGPR (lldb::tid_t tid, int flavor, const GPR &gpr) = 0;
HDRegisterContextMach_i386.h31 DoReadGPR (lldb::tid_t tid, int flavor, GPR &gpr);
40 DoWriteGPR (lldb::tid_t tid, int flavor, const GPR &gpr);
HDRegisterContextMach_x86_64.h31 DoReadGPR (lldb::tid_t tid, int flavor, GPR &gpr);
40 DoWriteGPR (lldb::tid_t tid, int flavor, const GPR &gpr);
HDRegisterContextMach_arm.h32 DoReadGPR (lldb::tid_t tid, int flavor, GPR &gpr);
44 DoWriteGPR (lldb::tid_t tid, int flavor, const GPR &gpr);
HDRegisterContextMach_x86_64.cpp34 RegisterContextMach_x86_64::DoReadGPR (lldb::tid_t tid, int flavor, GPR &gpr) in DoReadGPR()
55 RegisterContextMach_x86_64::DoWriteGPR (lldb::tid_t tid, int flavor, const GPR &gpr) in DoWriteGPR()
/trueos/contrib/llvm/tools/lldb/source/Plugins/Process/POSIX/
HDRegisterContextLinux_i386.cpp16 struct GPR struct
39 GPR regs; // General purpose registers. argument
80 return sizeof(GPR); in GetGPRSize()
HDRegisterContextLinux_x86_64.cpp47 } GPR; typedef
51 GPR gpr; // General purpose registers.
120 return sizeof(GPR); in GetGPRSize()
HDRegisterContextFreeBSD_i386.cpp17 struct GPR struct
72 return sizeof(GPR); in GetGPRSize()
HDRegisterContextFreeBSD_mips64.cpp60 } GPR; typedef
81 return sizeof(GPR); in GetGPRSize()
/trueos/sys/dev/sound/pci/
HDemu10k1.c96 #define GPR(x) (EMU_FXGPREGBASE + (x)) macro
1667 emu_addefxop(sc, iMACINT0, GPR(0), EXTIN(EXTIN_SPDIF_CD_L), in emu_initefx()
1669 emu_addefxop(sc, iMACINT0, GPR(1), EXTIN(EXTIN_SPDIF_CD_R), in emu_initefx()
1673 emu_addefxop(sc, iACC3, GPR(0), GPR(0), C_00000000, in emu_initefx()
1675 emu_addefxop(sc, iACC3, GPR(1), GPR(1), C_00000000, in emu_initefx()
1680 C_00000000, GPR(0), &pc); in emu_initefx()
1682 C_00000001, GPR(1), &pc); in emu_initefx()
1685 emu_addefxop(sc, iINTERP, GPR(2), GPR(1), C_40000000, GPR(0), &pc); in emu_initefx()
1691 GPR(16), GPR(0), &pc); in emu_initefx()
1693 GPR(17), GPR(1), &pc); in emu_initefx()
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HDemu10kx.c97 #define GPR(i) (sc->gpr_base+(i)) macro
1633 GPR(sc->cache_gpr[CACHE_IDX]), \
1645 GPR(sc->cache_gpr[OUT_CACHE_IDX]), \
1646 GPR(sc->cache_gpr[OUT_CACHE_IDX]), \
1648 GPR(sc->mixer_gpr[IN_GPR_IDX]), \
1659 GPR(sc->cache_gpr[OUT_CACHE_IDX]), \
1660 GPR(sc->mixer_gpr[OUT_GPR_IDX]), \
1669 GPR(sc->cache_gpr[OUT_CACHE_IDX]), \
1670 GPR(sc->mixer_gpr[OUT_GPR_IDX]), \
1678 GPR(sc->mute_gpr[FLAG_GPR]), \
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/trueos/contrib/llvm/lib/Target/PowerPC/
HDPPCRegisterInfo.td28 // GPR - One of the 32 32-bit general-purpose registers
29 class GPR<bits<5> num, string n> : PPCReg<n> {
34 class GP8<GPR SubReg, string n> : PPCReg<n> {
68 def R#Index : GPR<Index, "r"#Index>, DwarfRegNum<[-2, Index]>;
73 def X#Index : GP8<!cast<GPR>("R"#Index), "r"#Index>,
90 def ZERO : GPR<0, "0">;
94 def FP : GPR<0 /* arbitrary */, "**FRAME POINTER**">;
98 def BP : GPR<0 /* arbitrary */, "**BASE POINTER**">;
/trueos/contrib/llvm/lib/Target/SystemZ/
HDSystemZMachineFunctionInfo.h45 void setVarArgsFirstGPR(unsigned GPR) { VarArgsFirstGPR = GPR; } in setVarArgsFirstGPR() argument
/trueos/contrib/llvm/lib/Target/AArch64/
HDAArch64InstrInfo.td293 RegisterClass GPR;
308 let GPR = GPR64xsp;
324 let GPR = GPR32wsp;
341 outs, (ins exts.GPR:$Rn, GPR32:$Rm, UXTB_operand:$Imm3),
346 outs, (ins exts.GPR:$Rn, GPR32:$Rm, UXTH_operand:$Imm3),
351 outs, (ins exts.GPR:$Rn, GPR32:$Rm, UXTW_operand:$Imm3),
357 outs, (ins exts.GPR:$Rn, GPR32:$Rm, SXTB_operand:$Imm3),
362 outs, (ins exts.GPR:$Rn, GPR32:$Rm, SXTH_operand:$Imm3),
367 outs, (ins exts.GPR:$Rn, GPR32:$Rm, SXTW_operand:$Imm3),
643 RegisterClass GPR, RegisterClass GPRsp,
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