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Searched refs:EXTRACT_SUBVECTOR (Results 1 – 17 of 17) sorted by relevance

/trueos/contrib/llvm/lib/CodeGen/SelectionDAG/
HDLegalizeVectorTypes.cpp53 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break; in ScalarizeVectorResult()
508 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break; in SplitVectorResult()
722 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx); in SplitVecRes_EXTRACT_SUBVECTOR()
724 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec, in SplitVecRes_EXTRACT_SUBVECTOR()
1140 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break; in SplitVectorOperand()
1264 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx); in SplitVecOp_EXTRACT_SUBVECTOR()
1266 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi, in SplitVecOp_EXTRACT_SUBVECTOR()
1496 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break; in WidenVectorResult()
1651 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp1, in WidenVecRes_BinaryCanTrap()
1653 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp2, in WidenVecRes_BinaryCanTrap()
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HDSelectionDAGDumper.cpp193 case ISD::EXTRACT_SUBVECTOR: return "extract_subvector"; in getOperationName()
HDSelectionDAGBuilder.cpp284 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val, in getCopyFromPartsVector()
549 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, in getCopyToPartsVector()
3128 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurSDLoc(), VT, in visitShuffleVector()
4938 Res = DAG.getNode(ISD::EXTRACT_SUBVECTOR, sdl, DestVT, in visitIntrinsicCall()
HDSelectionDAG.cpp3160 case ISD::EXTRACT_SUBVECTOR: { in getNode()
6444 Lo = getNode(ISD::EXTRACT_SUBVECTOR, DL, LoVT, N, in SplitVector()
6446 Hi = getNode(ISD::EXTRACT_SUBVECTOR, DL, HiVT, N, in SplitVector()
HDDAGCombiner.cpp1194 case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N); in visit()
9856 if (Op.getOpcode() != ISD::EXTRACT_SUBVECTOR) in visitCONCAT_VECTORS()
9938 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, in visitEXTRACT_SUBVECTOR()
HDLegalizeIntegerTypes.cpp80 case ISD::EXTRACT_SUBVECTOR: in PromoteIntegerResult()
HDLegalizeDAG.cpp3071 case ISD::EXTRACT_SUBVECTOR: in ExpandNode()
/trueos/contrib/llvm/include/llvm/CodeGen/
HDISDOpcodes.h270 EXTRACT_SUBVECTOR, enumerator
/trueos/contrib/llvm/patches/
HDpatch-r267704-llvm-r211435-fix-avx-backend.diff36 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break;
/trueos/contrib/llvm/lib/Target/R600/
HDAMDGPUISelLowering.cpp120 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Custom); in AMDGPUTargetLowering()
121 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Custom); in AMDGPUTargetLowering()
269 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG); in LowerOperation()
/trueos/contrib/llvm/lib/Target/ARM/
HDARMISelLowering.cpp123 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal); in addTypeForNEON()
4030 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i16, Extended, in lowerCTPOP16BitElements()
4033 SDValue Extracted = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v8i8, in lowerCTPOP16BitElements()
4072 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i32, Extended, in lowerCTPOP32BitElements()
4075 SDValue Extracted = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i16, N2, in lowerCTPOP32BitElements()
5084 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, in ReconstructShuffle()
5090 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, in ReconstructShuffle()
5096 SDValue VEXTSrc1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, in ReconstructShuffle()
5099 SDValue VEXTSrc2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, in ReconstructShuffle()
5849 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, in LowerSDIV()
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/trueos/contrib/llvm/include/llvm/Target/
HDTargetSelectionDAG.td473 def vector_extract_subvec : SDNode<"ISD::EXTRACT_SUBVECTOR",
478 def extract_subvector : SDNode<"ISD::EXTRACT_SUBVECTOR", SDTSubVecExtract, []>;
/trueos/contrib/llvm/lib/Target/X86/
HDX86ISelLowering.cpp91 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, in ExtractSubVector()
816 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand); in resetOperationActions()
1267 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); in resetOperationActions()
1418 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); in resetOperationActions()
1421 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal); in resetOperationActions()
5745 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask, in LowerBUILD_VECTORvXi1()
7191 V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V, in LowerVectorIntExtend()
9030 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In, in LowerTRUNCATE()
9035 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In, in LowerTRUNCATE()
9037 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In, in LowerTRUNCATE()
[all …]
/trueos/contrib/llvm/lib/Target/AArch64/
HDAArch64ISelLowering.cpp3903 V1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V0, in isKnownShuffleVector()
3905 V0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V0, in isKnownShuffleVector()
4261 if (V1.getOpcode() == ISD::EXTRACT_SUBVECTOR) { in LowerVECTOR_SHUFFLE()
HDAArch64InstrNEON.td6846 //patterns for EXTRACT_SUBVECTOR
/trueos/contrib/llvm/lib/Target/NVPTX/
HDNVPTXISelLowering.cpp1173 case ISD::EXTRACT_SUBVECTOR: in LowerOperation()
HDNVPTXVector.td869 def extract_subvec : SDNode<"ISD::EXTRACT_SUBVECTOR",