Searched refs:EVERGREEN_CRTC_CONTROL (Results 1 – 3 of 3) sorted by relevance
441 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | in radeon_card_posted()442 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); in radeon_card_posted()446 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | in radeon_card_posted()447 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) | in radeon_card_posted()448 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) | in radeon_card_posted()449 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) | in radeon_card_posted()450 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) | in radeon_card_posted()451 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); in radeon_card_posted()
222 #define EVERGREEN_CRTC_CONTROL 0x6e70 macro
153 if (!(RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[crtc]) & EVERGREEN_CRTC_MASTER_EN)) in dce4_wait_for_vblank()485 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset); in evergreen_pm_prepare()487 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); in evergreen_pm_prepare()510 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset); in evergreen_pm_finish()512 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); in evergreen_pm_finish()1368 crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN; in evergreen_mc_stop()1380 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]); in evergreen_mc_stop()1385 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp); in evergreen_mc_stop()1399 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]); in evergreen_mc_stop()1401 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp); in evergreen_mc_stop()[all …]