| /trueos/contrib/llvm/lib/Target/ARM/ |
| HD | MLxExpansionPass.cpp | 94 MachineInstr *DefMI = MRI->getVRegDef(Reg); in getAccDefMI() local 96 if (DefMI->getParent() != MBB) in getAccDefMI() 98 if (DefMI->isCopyLike()) { in getAccDefMI() 99 Reg = DefMI->getOperand(1).getReg(); in getAccDefMI() 101 DefMI = MRI->getVRegDef(Reg); in getAccDefMI() 104 } else if (DefMI->isInsertSubreg()) { in getAccDefMI() 105 Reg = DefMI->getOperand(2).getReg(); in getAccDefMI() 107 DefMI = MRI->getVRegDef(Reg); in getAccDefMI() 113 return DefMI; in getAccDefMI() 148 MachineInstr *DefMI = MRI->getVRegDef(Reg); in hasLoopHazard() local [all …]
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| HD | ARMHazardRecognizer.cpp | 19 static bool hasRAWHazard(MachineInstr *DefMI, MachineInstr *MI, in hasRAWHazard() argument 30 return MI->readsRegister(DefMI->getOperand(0).getReg(), &TRI); in hasRAWHazard() 45 MachineInstr *DefMI = LastMI; in getHazardType() local 61 DefMI = &*I; in getHazardType() 65 if (TII.isFpMLxInstruction(DefMI->getOpcode()) && in getHazardType() 67 hasRAWHazard(DefMI, MI, TII.getRegisterInfo()))) { in getHazardType()
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| HD | ARMBaseInstrInfo.cpp | 1730 MachineInstr *DefMI = canFoldIntoMOVCC(MI->getOperand(2).getReg(), MRI, this); in optimizeSelect() local 1731 bool Invert = !DefMI; in optimizeSelect() 1732 if (!DefMI) in optimizeSelect() 1733 DefMI = canFoldIntoMOVCC(MI->getOperand(1).getReg(), MRI, this); in optimizeSelect() 1734 if (!DefMI) in optimizeSelect() 1747 DefMI->getDesc(), DestReg); in optimizeSelect() 1750 const MCInstrDesc &DefDesc = DefMI->getDesc(); in optimizeSelect() 1753 NewMI.addOperand(DefMI->getOperand(i)); in optimizeSelect() 1775 DefMI->eraseFromParent(); in optimizeSelect() 2463 MachineInstr *DefMI, unsigned Reg, in FoldImmediate() argument [all …]
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| HD | ARMBaseInstrInfo.h | 215 virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, 223 const MachineInstr *DefMI, unsigned DefIdx, 278 const MachineInstr *DefMI, unsigned DefIdx, 281 const MachineInstr *DefMI, unsigned DefIdx) const;
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| /trueos/contrib/llvm/lib/CodeGen/ |
| HD | TargetSchedule.cpp | 156 const MachineInstr *DefMI, unsigned DefOperIdx, in computeOperandLatency() argument 160 return TII->defaultDefLatency(&SchedModel, DefMI); in computeOperandLatency() 165 OperLatency = TII->getOperandLatency(&InstrItins, DefMI, DefOperIdx, in computeOperandLatency() 169 unsigned DefClass = DefMI->getDesc().getSchedClass(); in computeOperandLatency() 176 unsigned InstrLatency = TII->getInstrLatency(&InstrItins, DefMI); in computeOperandLatency() 184 TII->defaultDefLatency(&SchedModel, DefMI)); in computeOperandLatency() 188 const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI); in computeOperandLatency() 189 unsigned DefIdx = findDefIdx(DefMI, DefOperIdx); in computeOperandLatency() 212 if (SCDesc->isValid() && !DefMI->getOperand(DefOperIdx).isImplicit() in computeOperandLatency() 213 && !DefMI->getDesc().OpInfo[DefOperIdx].isOptionalDef() in computeOperandLatency() [all …]
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| HD | LiveRangeEdit.cpp | 51 const MachineInstr *DefMI, in checkRematerializable() argument 53 assert(DefMI && "Missing instruction"); in checkRematerializable() 55 if (!TII.isTriviallyReMaterializable(DefMI, aa)) in checkRematerializable() 67 MachineInstr *DefMI = LIS.getInstructionFromIndex(VNI->def); in scanRemattable() local 68 if (!DefMI) in scanRemattable() 70 checkRematerializable(VNI, DefMI, aa); in scanRemattable() 167 MachineInstr *DefMI = 0, *UseMI = 0; in foldAsLoad() local 175 if (DefMI && DefMI != MI) in foldAsLoad() 179 DefMI = MI; in foldAsLoad() 189 if (!DefMI || !UseMI) in foldAsLoad() [all …]
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| HD | TargetInstrInfo.cpp | 665 const MachineInstr *DefMI) const { in defaultDefLatency() 666 if (DefMI->isTransient()) in defaultDefLatency() 668 if (DefMI->mayLoad()) in defaultDefLatency() 670 if (isHighLatencyDef(DefMI->getOpcode())) in defaultDefLatency() 692 const MachineInstr *DefMI, in hasLowDefLatency() argument 697 unsigned DefClass = DefMI->getDesc().getSchedClass(); in hasLowDefLatency() 706 const MachineInstr *DefMI, unsigned DefIdx, in getOperandLatency() argument 708 unsigned DefClass = DefMI->getDesc().getSchedClass(); in getOperandLatency() 717 const MachineInstr *DefMI) const { in computeDefOperandLatency() 721 return getInstrLatency(ItinData, DefMI); in computeDefOperandLatency() [all …]
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| HD | RegisterCoalescer.cpp | 591 MachineInstr *DefMI = LIS->getInstructionFromIndex(AValNo->def); in removeCopyByCommutingDef() local 592 if (!DefMI) in removeCopyByCommutingDef() 594 if (!DefMI->isCommutable()) in removeCopyByCommutingDef() 598 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg); in removeCopyByCommutingDef() 601 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx)) in removeCopyByCommutingDef() 604 if (!TII->findCommutedOpIndices(DefMI, Op1, Op2)) in removeCopyByCommutingDef() 613 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx); in removeCopyByCommutingDef() 639 << *DefMI); in removeCopyByCommutingDef() 643 MachineBasicBlock *MBB = DefMI->getParent(); in removeCopyByCommutingDef() 644 MachineInstr *NewMI = TII->commuteInstruction(DefMI); in removeCopyByCommutingDef() [all …]
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| HD | MachineTraceMetrics.cpp | 617 const MachineInstr *DefMI; member 621 DataDep(const MachineInstr *DefMI, unsigned DefOp, unsigned UseOp) in DataDep() 622 : DefMI(DefMI), DefOp(DefOp), UseOp(UseOp) {} in DataDep() 630 DefMI = &*DefI; in DataDep() 770 const MachineInstr *DefMI = MTM.MRI->getVRegDef(LIR.Reg); in computeCrossBlockCriticalPath() local 772 const TraceBlockInfo &DefTBI = BlockInfo[DefMI->getParent()->getNumber()]; in computeCrossBlockCriticalPath() 775 unsigned Len = LIR.Height + Cycles[DefMI].Depth; in computeCrossBlockCriticalPath() 847 BlockInfo[Dep.DefMI->getParent()->getNumber()]; in computeInstrDepths() 852 unsigned DepCycle = Cycles.lookup(Dep.DefMI).Depth; in computeInstrDepths() 854 if (!Dep.DefMI->isTransient()) in computeInstrDepths() [all …]
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| HD | InlineSpiller.cpp | 112 MachineInstr *DefMI; member 123 SpillReg(Reg), SpillVNI(VNI), SpillMBB(0), DefMI(0) {} in SibValueInfo() 126 bool hasDef() const { return DefByOrigPHI || DefMI; } in hasDef() 332 if (SVI.DefMI) in operator <<() 333 OS << " def: " << *SVI.DefMI; in operator <<() 396 DepSV.DefMI = SV.DefMI; in propagateSiblingValue() 484 return SVI->second.DefMI; in traceSiblingValue() 602 SVI->second.DefMI = MI; in traceSiblingValue() 623 return SVI->second.DefMI; in traceSiblingValue() 646 MachineInstr *DefMI = 0; in analyzeSiblingValues() local [all …]
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| HD | PHIElimination.cpp | 154 MachineInstr *DefMI = *I; in runOnMachineFunction() local 155 unsigned DefReg = DefMI->getOperand(0).getReg(); in runOnMachineFunction() 158 LIS->RemoveMachineInstrFromMaps(DefMI); in runOnMachineFunction() 159 DefMI->eraseFromParent(); in runOnMachineFunction() 392 if (MachineInstr *DefMI = MRI->getVRegDef(SrcReg)) in LowerPHINode() local 393 if (DefMI->isImplicitDef()) in LowerPHINode() 394 ImpDefs.insert(DefMI); in LowerPHINode()
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| HD | MachineCSE.cpp | 128 MachineInstr *DefMI = MRI->getVRegDef(Reg); in INITIALIZE_PASS_DEPENDENCY() local 129 if (!DefMI->isCopy()) in INITIALIZE_PASS_DEPENDENCY() 131 unsigned SrcReg = DefMI->getOperand(1).getReg(); in INITIALIZE_PASS_DEPENDENCY() 134 if (DefMI->getOperand(0).getSubReg() || DefMI->getOperand(1).getSubReg()) in INITIALIZE_PASS_DEPENDENCY() 138 DEBUG(dbgs() << "Coalescing: " << *DefMI); in INITIALIZE_PASS_DEPENDENCY() 142 DefMI->eraseFromParent(); in INITIALIZE_PASS_DEPENDENCY()
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| HD | MachineSink.cpp | 140 MachineInstr *DefMI = MRI->getVRegDef(SrcReg); in INITIALIZE_PASS_DEPENDENCY() local 141 if (DefMI->isCopyLike()) in INITIALIZE_PASS_DEPENDENCY() 143 DEBUG(dbgs() << "Coalescing: " << *DefMI); in INITIALIZE_PASS_DEPENDENCY() 330 MachineInstr *DefMI = MRI->getVRegDef(Reg); in isWorthBreakingCriticalEdge() local 331 if (DefMI->getParent() == MI->getParent()) in isWorthBreakingCriticalEdge()
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| HD | EarlyIfConversion.cpp | 244 MachineInstr *DefMI = MRI->getVRegDef(Reg); in canSpeculateInstrs() local 245 if (!DefMI || DefMI->getParent() != Head) in canSpeculateInstrs() 247 if (InsertAfter.insert(DefMI)) in canSpeculateInstrs() 248 DEBUG(dbgs() << "BB#" << MBB->getNumber() << " depends on " << *DefMI); in canSpeculateInstrs() 249 if (DefMI->isTerminator()) { in canSpeculateInstrs()
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| HD | TwoAddressInstructionPass.cpp | 407 MachineInstr *DefMI = &MI; in isKilled() local 413 if (!isPlainlyKilled(DefMI, Reg, LIS)) in isKilled() 422 DefMI = &*Begin; in isKilled() 427 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) in isKilled() 919 MachineInstr *DefMI = &*DI; in isDefTooClose() local 920 if (DefMI->getParent() != MBB || DefMI->isCopy() || DefMI->isCopyLike()) in isDefTooClose() 922 if (DefMI == MI) in isDefTooClose() 924 DenseMap<MachineInstr*, unsigned>::iterator DDI = DistanceMap.find(DefMI); in isDefTooClose() 929 if (TII->getInstrLatency(InstrItins, DefMI) > (Dist - DefDist)) in isDefTooClose()
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| HD | PeepholeOptimizer.cpp | 636 MachineInstr *DefMI = 0; in runOnMachineFunction() local 638 FoldAsLoadDefReg, DefMI); in runOnMachineFunction() 644 LocalMIs.erase(DefMI); in runOnMachineFunction() 647 DefMI->eraseFromParent(); in runOnMachineFunction()
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| HD | TailDuplication.cpp | 236 MachineInstr *DefMI = MRI->getVRegDef(VReg); in TailDuplicateAndUpdate() local 238 if (DefMI) { in TailDuplicateAndUpdate() 239 DefBB = DefMI->getParent(); in TailDuplicateAndUpdate()
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| /trueos/contrib/llvm/include/llvm/Target/ |
| HD | TargetInstrInfo.h | 782 MachineInstr *&DefMI) const { in optimizeLoadInstr() argument 792 virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, in FoldImmediate() argument 825 const MachineInstr *DefMI, unsigned DefIdx, 832 const MachineInstr *DefMI, unsigned DefIdx, 850 const MachineInstr *DefMI) const; 853 const MachineInstr *DefMI) const; 867 const MachineInstr *DefMI, unsigned DefIdx, in hasHighOperandLatency() argument 876 const MachineInstr *DefMI, unsigned DefIdx) const;
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| /trueos/contrib/llvm/include/llvm/CodeGen/ |
| HD | TargetSchedule.h | 145 unsigned computeOperandLatency(const MachineInstr *DefMI, unsigned DefOperIdx, 166 unsigned computeOutputLatency(const MachineInstr *DefMI, unsigned DefIdx,
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| HD | LiveRangeEdit.h | 170 bool checkRematerializable(VNInfo *VNI, const MachineInstr *DefMI,
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| HD | MachineTraceMetrics.h | 307 void addLiveIns(const MachineInstr *DefMI, unsigned DefOp,
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| /trueos/contrib/llvm/lib/Target/X86/ |
| HD | X86InstrInfo.h | 389 const MachineInstr *DefMI, unsigned DefIdx, 417 MachineInstr *&DefMI) const;
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| /trueos/contrib/llvm/lib/Target/PowerPC/ |
| HD | PPCInstrInfo.h | 155 virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
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| HD | PPCInstrInfo.cpp | 817 bool PPCInstrInfo::FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, in FoldImmediate() argument 821 unsigned DefOpc = DefMI->getOpcode(); in FoldImmediate() 824 if (!DefMI->getOperand(1).isImm()) in FoldImmediate() 826 if (DefMI->getOperand(1).getImm() != 0) in FoldImmediate() 880 DefMI->eraseFromParent(); in FoldImmediate()
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| /trueos/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| HD | InstrEmitter.cpp | 495 MachineInstr *DefMI = MRI->getVRegDef(VReg); in EmitSubregNode() local 497 if (DefMI && in EmitSubregNode() 498 TII->isCoalescableExtInstr(*DefMI, SrcReg, DstReg, DefSubIdx) && in EmitSubregNode()
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