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Searched refs:CPU_CONTROL_DC_ENABLE (Results 1 – 6 of 6) sorted by relevance

/trueos/sys/arm/arm/
HDcpufunc.c1302 { "cpu.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
1303 { "cpu.nocache", OR, BIC, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
1304 { "arm9.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
1306 { "arm9.dcache", BIC, OR, CPU_CONTROL_DC_ENABLE },
1321 | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
1326 | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
1356 { "cpu.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
1357 { "cpu.nocache", OR, BIC, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
1358 { "arm10.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
1360 { "arm10.dcache", BIC, OR, CPU_CONTROL_DC_ENABLE },
[all …]
HDlocore-v6.S86 tst r7, #CPU_CONTROL_DC_ENABLE
97 bic r7, #CPU_CONTROL_DC_ENABLE
304 orr r7, #CPU_CONTROL_DC_ENABLE
407 bic r0, #CPU_CONTROL_DC_ENABLE
HDlocore-v4.S152 bic r2, r2, #(CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE |\
412 bic r2, r2, #(CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE |\
448 orr r0, r0, #(CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE |\
HDidentcpu.c425 print_enadis(ctrl & CPU_CONTROL_DC_ENABLE, "DC"); in identify_arm_cpu()
/trueos/sys/arm/rockchip/
HDrk30xx_machdep.c75 cpufunc_control(CPU_CONTROL_DC_ENABLE|CPU_CONTROL_IC_ENABLE, in initarm_late_init()
76 CPU_CONTROL_DC_ENABLE|CPU_CONTROL_IC_ENABLE); in initarm_late_init()
/trueos/sys/arm/include/
HDarmreg.h239 #define CPU_CONTROL_DC_ENABLE 0x00000004 /* C: IDC/DC enable */ macro
266 #define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE