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Searched refs:ATA_CYL_LSB (Results 1 – 15 of 15) sorted by relevance

/trueos/sys/dev/ata/
HData-lowlevel.c350 length = ATA_IDX_INB(ch, ATA_CYL_LSB)|(ATA_IDX_INB(ch, ATA_CYL_MSB)<<8); in ata_end_transaction()
530 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB); in ata_generic_reset()
563 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB); in ata_generic_reset()
695 ATA_IDX_OUTB(ch, ATA_CYL_LSB, 0); in ata_generic_command()
700 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->transfersize); in ata_generic_command()
762 ((u_int64_t)(ATA_IDX_INB(ch, ATA_CYL_LSB)) << 32) | in ata_tf_read()
769 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) | in ata_tf_read()
775 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) | in ata_tf_read()
793 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 32); in ata_tf_write()
794 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8); in ata_tf_write()
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HData-all.h44 #define ATA_CYL_LSB 4 /* (RW) cylinder# LSB */ macro
/trueos/sys/dev/ata/chipsets/
HData-serverworks.c191 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10; in ata_serverworks_ch_attach()
270 temp = ATA_IDX_INW(ch, ATA_CYL_LSB); in ata_serverworks_tf_read()
280 ((ATA_IDX_INW(ch, ATA_CYL_LSB) & 0x00ff) << 8) | in ata_serverworks_tf_read()
296 ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((request->u.ata.lba >> 24) & 0xff00) | in ata_serverworks_tf_write()
306 ATA_IDX_OUTW(ch, ATA_CYL_LSB, request->u.ata.lba >> 8); in ata_serverworks_tf_write()
HData-promise.c882 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 16) | in ata_promise_mio_pm_read()
920 ATA_IDX_OUTB(ch, ATA_CYL_LSB, (value >> 16) & 0xff); in ata_promise_mio_pm_write()
972 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 16) | in ata_promise_mio_softreset()
1217 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_LSB; in ata_promise_apkt()
1233 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_LSB; in ata_promise_apkt()
HData-fsl.c180 ch->r_io[ATA_CYL_LSB].offset = 0xb0; in imx_ata_ch_attach()
HData-marvell.c440 bytep[i++] = 0x10 | ATA_CYL_LSB; in ata_marvell_edma_begin_transaction()
442 bytep[i++] = 0x10 | ATA_CYL_LSB; in ata_marvell_edma_begin_transaction()
HData-intel.c909 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10; in ata_intel_31244_ch_attach()
968 ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((request->u.ata.lba >> 24) & 0xff00) | in ata_intel_31244_tf_write()
978 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8); in ata_intel_31244_tf_write()
/trueos/sys/mips/rmi/
HDxlr_pcmcia.c108 ch->r_io[ATA_CYL_LSB].offset = XLR_PCMCIA_CYLINDER_LOW_REG; in xlr_pcmcia_attach()
/trueos/usr.sbin/bhyve/
HDahci.h43 #define ATA_CYL_LSB 4 /* (RW) cylinder# LSB */ macro
/trueos/sys/arm/xscale/ixp425/
HDavila_ata.c514 ch->r_io[ATA_CYL_LSB].offset = ATA_CYL_LSB; in avila_channel_attach()
/trueos/sys/arm/at91/
HDat91_cfata.c209 ch->r_io[ATA_CYL_LSB].offset = 0x04; in at91_channel_attach()
/trueos/sys/dev/mvs/
HDmvs.c925 length = ATA_INB(ch->r_mem,ATA_CYL_LSB) | in mvs_legacy_intr()
1153 res->lba_mid_exp = ATA_INB(ch->r_mem, ATA_CYL_LSB); in mvs_tfd_read()
1158 res->lba_mid = ATA_INB(ch->r_mem, ATA_CYL_LSB); in mvs_tfd_read()
1176 ATA_OUTB(ch->r_mem, ATA_CYL_LSB, cmd->lba_mid_exp); in mvs_tfd_write()
1177 ATA_OUTB(ch->r_mem, ATA_CYL_LSB, cmd->lba_mid); in mvs_tfd_write()
1366 ATA_OUTB(ch->r_mem, ATA_CYL_LSB, 0); in mvs_legacy_execute_transaction()
1370 ATA_OUTB(ch->r_mem, ATA_CYL_LSB, ch->transfersize); in mvs_legacy_execute_transaction()
HDmvs.h205 #define ATA_CYL_LSB 0x110 /* (RW) cylinder# LSB */ macro
/trueos/sys/dev/siis/
HDsiis.h39 #define ATA_CYL_LSB 4 /* (RW) cylinder# LSB */ macro
/trueos/sys/dev/ahci/
HDahci.h40 #define ATA_CYL_LSB 4 /* (RW) cylinder# LSB */ macro