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Searched refs:AR_MIBC (Results 1 – 15 of 15) sorted by relevance

/trueos/tools/tools/ath/common/
HDdumpregs_5210.c56 DEFBASIC(AR_MIBC, "MIBC"),
HDdumpregs_5211.c52 DEFBASIC(AR_MIBC, "MIBC"),
HDdumpregs_5416.c55 DEFBASIC(AR_MIBC, "MIBC"),
HDdumpregs_5212.c54 DEFBASIC(AR_MIBC, "MIBC"),
/trueos/sys/dev/ath/ath_hal/ar5210/
HDar5210reg.h46 #define AR_MIBC 0x0040 /* MIB control register */ macro
HDar5210_reset.c180 OS_REG_WRITE(ah, AR_MIBC, 0); /* unfreeze ctrs + clr state */ in ar5210Reset()
/trueos/sys/dev/ath/ath_hal/ar5212/
HDar5212_misc.c367 OS_REG_WRITE(ah, AR_MIBC, in ar5212EnableMibCounters()
374 OS_REG_WRITE(ah, AR_MIBC, AR_MIBC | AR_MIBC_CMC); in ar5212DisableMibCounters()
HDar5212reg.h36 #define AR_MIBC 0x0040 /* MAC MIB control register */ macro
HDar5212_ani.c690 __func__, OS_REG_READ(ah, AR_MIBC), in ar5212ProcessMibIntr()
/trueos/sys/contrib/dev/ath/ath_hal/ar9300/
HDar9300_xmit_ds.c527 OS_REG_WRITE(ah, AR_MIBC, AR_MIBC_CMC); in ar9300__cont_tx_mode()
528 OS_REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC); in ar9300__cont_tx_mode()
HDar9300_ani.c149 OS_REG_WRITE(ah, AR_MIBC, in ar9300_enable_mib_counters()
161 OS_REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC | AR_MIBC_CMC); in ar9300_disable_mib_counters()
HDar9300_misc.c1994 reg_val = OS_REG_READ(ah, AR_MIBC); in ar9300_clear_mib_counters()
1995 OS_REG_WRITE(ah, AR_MIBC, reg_val | AR_MIBC_CMC); in ar9300_clear_mib_counters()
1996 OS_REG_WRITE(ah, AR_MIBC, reg_val & ~AR_MIBC_CMC); in ar9300_clear_mib_counters()
HDar9300reg.h140 #define AR_MIBC AR_MAC_DMA_OFFSET(MAC_DMA_MIBC) macro
/trueos/sys/dev/ath/ath_hal/ar5211/
HDar5211reg.h41 #define AR_MIBC 0x0040 /* MIB control register */ macro
/trueos/sys/dev/ath/ath_hal/ar5416/
HDar5416_ani.c659 __func__, OS_REG_READ(ah, AR_MIBC), in ar5416ProcessMibIntr()