1 /*- 2 * Copyright (c) 2011 Aleksandr Rybalko. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #ifndef __AR8X16_SWITCHREG_H__ 30 #define __AR8X16_SWITCHREG_H__ 31 32 /* XXX doesn't belong here; stolen shamelessly from ath_hal/ah_internal.h */ 33 /* 34 * Register manipulation macros that expect bit field defines 35 * to follow the convention that an _S suffix is appended for 36 * a shift count, while the field mask has no suffix. 37 */ 38 #define SM(_v, _f) (((_v) << _f##_S) & (_f)) 39 #define MS(_v, _f) (((_v) & (_f)) >> _f##_S) 40 41 /* Atheros specific MII registers */ 42 #define MII_ATH_DBG_ADDR 0x1d 43 #define MII_ATH_DBG_DATA 0x1e 44 45 #define AR8X16_REG_MASK_CTRL 0x0000 46 #define AR8X16_MASK_CTRL_REV_MASK 0x000000ff 47 #define AR8X16_MASK_CTRL_VER_MASK 0x0000ff00 48 #define AR8X16_MASK_CTRL_VER_SHIFT 8 49 #define AR8X16_MASK_CTRL_SOFT_RESET (1U << 31) 50 51 #define AR8X16_REG_MODE 0x0008 52 /* DIR-615 E4 U-Boot */ 53 #define AR8X16_MODE_DIR_615_UBOOT 0x8d1003e0 54 /* From Ubiquiti RSPRO */ 55 #define AR8X16_MODE_RGMII_PORT4_ISO 0x81461bea 56 #define AR8X16_MODE_RGMII_PORT4_SWITCH 0x01261be2 57 /* AVM Fritz!Box 7390 */ 58 #define AR8X16_MODE_GMII 0x010e5b71 59 /* from avm_cpmac/linux_ar_reg.h */ 60 #define AR8X16_MODE_RESERVED 0x000e1b20 61 #define AR8X16_MODE_MAC0_GMII_EN (1u << 0) 62 #define AR8X16_MODE_MAC0_RGMII_EN (1u << 1) 63 #define AR8X16_MODE_PHY4_GMII_EN (1u << 2) 64 #define AR8X16_MODE_PHY4_RGMII_EN (1u << 3) 65 #define AR8X16_MODE_MAC0_MAC_MODE (1u << 4) 66 #define AR8X16_MODE_RGMII_RXCLK_DELAY_EN (1u << 6) 67 #define AR8X16_MODE_RGMII_TXCLK_DELAY_EN (1u << 7) 68 #define AR8X16_MODE_MAC5_MAC_MODE (1u << 14) 69 #define AR8X16_MODE_MAC5_PHY_MODE (1u << 15) 70 #define AR8X16_MODE_TXDELAY_S0 (1u << 21) 71 #define AR8X16_MODE_TXDELAY_S1 (1u << 22) 72 #define AR8X16_MODE_RXDELAY_S0 (1u << 23) 73 #define AR8X16_MODE_LED_OPEN_EN (1u << 24) 74 #define AR8X16_MODE_SPI_EN (1u << 25) 75 #define AR8X16_MODE_RXDELAY_S1 (1u << 26) 76 #define AR8X16_MODE_POWER_ON_SEL (1u << 31) 77 78 #define AR8X16_REG_ISR 0x0010 79 #define AR8X16_REG_IMR 0x0014 80 81 #define AR8X16_REG_SW_MAC_ADDR0 0x0020 82 #define AR8X16_REG_SW_MAC_ADDR1 0x0024 83 84 #define AR8X16_REG_FLOOD_MASK 0x002c 85 #define AR8X16_FLOOD_MASK_BCAST_TO_CPU (1 << 26) 86 87 #define AR8X16_REG_GLOBAL_CTRL 0x0030 88 #define AR8216_GLOBAL_CTRL_MTU_MASK 0x00000fff 89 #define AR8216_GLOBAL_CTRL_MTU_MASK_S 0 90 #define AR8316_GLOBAL_CTRL_MTU_MASK 0x00007fff 91 #define AR8316_GLOBAL_CTRL_MTU_MASK_S 0 92 #define AR8236_GLOBAL_CTRL_MTU_MASK 0x00007fff 93 #define AR8236_GLOBAL_CTRL_MTU_MASK_S 0 94 #define AR7240_GLOBAL_CTRL_MTU_MASK 0x00003fff 95 #define AR7240_GLOBAL_CTRL_MTU_MASK_S 0 96 97 #define AR8X16_REG_VLAN_CTRL 0x0040 98 #define AR8X16_VLAN_OP 0x00000007 99 #define AR8X16_VLAN_OP_NOOP 0x0 100 #define AR8X16_VLAN_OP_FLUSH 0x1 101 #define AR8X16_VLAN_OP_LOAD 0x2 102 #define AR8X16_VLAN_OP_PURGE 0x3 103 #define AR8X16_VLAN_OP_REMOVE_PORT 0x4 104 #define AR8X16_VLAN_OP_GET_NEXT 0x5 105 #define AR8X16_VLAN_OP_GET 0x6 106 #define AR8X16_VLAN_ACTIVE (1 << 3) 107 #define AR8X16_VLAN_FULL (1 << 4) 108 #define AR8X16_VLAN_PORT 0x00000f00 109 #define AR8X16_VLAN_PORT_SHIFT 8 110 #define AR8X16_VLAN_VID 0x0fff0000 111 #define AR8X16_VLAN_VID_SHIFT 16 112 #define AR8X16_VLAN_PRIO 0x70000000 113 #define AR8X16_VLAN_PRIO_SHIFT 28 114 #define AR8X16_VLAN_PRIO_EN (1U << 31) 115 116 #define AR8X16_REG_VLAN_DATA 0x0044 117 #define AR8X16_VLAN_MEMBER 0x0000003f 118 #define AR8X16_VLAN_VALID (1 << 11) 119 120 #define AR8X16_REG_ARL_CTRL0 0x0050 121 #define AR8X16_REG_ARL_CTRL1 0x0054 122 #define AR8X16_REG_ARL_CTRL2 0x0058 123 124 #define AR8X16_REG_AT_CTRL 0x005c 125 #define AR8X16_AT_CTRL_ARP_EN (1 << 20) 126 127 #define AR8X16_REG_IP_PRIORITY_1 0x0060 128 #define AR8X16_REG_IP_PRIORITY_2 0x0064 129 #define AR8X16_REG_IP_PRIORITY_3 0x0068 130 #define AR8X16_REG_IP_PRIORITY_4 0x006C 131 132 #define AR8X16_REG_TAG_PRIO 0x0070 133 134 #define AR8X16_REG_SERVICE_TAG 0x0074 135 #define AR8X16_SERVICE_TAG_MASK 0x0000ffff 136 137 #define AR8X16_REG_CPU_PORT 0x0078 138 #define AR8X16_MIRROR_PORT_SHIFT 4 139 #define AR8X16_MIRROR_PORT_MASK (0xf << AR8X16_MIRROR_PORT_SHIFT) 140 #define AR8X16_CPU_MIRROR_PORT(_p) ((_p) << AR8X16_MIRROR_PORT_SHIFT) 141 #define AR8X16_CPU_MIRROR_DIS AR8X16_CPU_MIRROR_PORT(0xf) 142 #define AR8X16_CPU_PORT_EN (1 << 8) 143 144 #define AR8X16_REG_MIB_FUNC0 0x0080 145 #define AR8X16_MIB_TIMER_MASK 0x0000ffff 146 #define AR8X16_MIB_AT_HALF_EN (1 << 16) 147 #define AR8X16_MIB_BUSY (1 << 17) 148 #define AR8X16_MIB_FUNC_SHIFT 24 149 #define AR8X16_MIB_FUNC_NO_OP 0x0 150 #define AR8X16_MIB_FUNC_FLUSH 0x1 151 #define AR8X16_MIB_FUNC_CAPTURE 0x3 152 #define AR8X16_MIB_FUNC_XXX (1 << 30) /* 0x40000000 */ 153 154 #define AR934X_MIB_ENABLE (1 << 30) 155 156 #define AR8X16_REG_MDIO_HIGH_ADDR 0x0094 157 158 #define AR8X16_REG_MDIO_CTRL 0x0098 159 #define AR8X16_MDIO_CTRL_DATA_MASK 0x0000ffff 160 #define AR8X16_MDIO_CTRL_REG_ADDR_SHIFT 16 161 #define AR8X16_MDIO_CTRL_PHY_ADDR_SHIFT 21 162 #define AR8X16_MDIO_CTRL_CMD_WRITE 0 163 #define AR8X16_MDIO_CTRL_CMD_READ (1 << 27) 164 #define AR8X16_MDIO_CTRL_MASTER_EN (1 << 30) 165 #define AR8X16_MDIO_CTRL_BUSY (1U << 31) 166 167 #define AR8X16_REG_PORT_BASE(_p) (0x0100 + (_p) * 0x0100) 168 169 #define AR8X16_REG_PORT_STS(_p) (AR8X16_REG_PORT_BASE((_p)) + 0x0000) 170 #define AR8X16_PORT_STS_SPEED_MASK 0x00000003 171 #define AR8X16_PORT_STS_SPEED_10 0 172 #define AR8X16_PORT_STS_SPEED_100 1 173 #define AR8X16_PORT_STS_SPEED_1000 2 174 #define AR8X16_PORT_STS_TXMAC (1 << 2) 175 #define AR8X16_PORT_STS_RXMAC (1 << 3) 176 #define AR8X16_PORT_STS_TXFLOW (1 << 4) 177 #define AR8X16_PORT_STS_RXFLOW (1 << 5) 178 #define AR8X16_PORT_STS_DUPLEX (1 << 6) 179 #define AR8X16_PORT_STS_LINK_UP (1 << 8) 180 #define AR8X16_PORT_STS_LINK_AUTO (1 << 9) 181 #define AR8X16_PORT_STS_LINK_PAUSE (1 << 10) 182 183 #define AR8X16_REG_PORT_CTRL(_p) (AR8X16_REG_PORT_BASE((_p)) + 0x0004) 184 #define AR8X16_PORT_CTRL_STATE_MASK 0x00000007 185 #define AR8X16_PORT_CTRL_STATE_DISABLED 0 186 #define AR8X16_PORT_CTRL_STATE_BLOCK 1 187 #define AR8X16_PORT_CTRL_STATE_LISTEN 2 188 #define AR8X16_PORT_CTRL_STATE_LEARN 3 189 #define AR8X16_PORT_CTRL_STATE_FORWARD 4 190 #define AR8X16_PORT_CTRL_LEARN_LOCK (1 << 7) 191 #define AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_SHIFT 8 192 #define AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_KEEP 0 193 #define AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_STRIP 1 194 #define AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_ADD 2 195 #define AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_DOUBLE_TAG 3 196 #define AR8X16_PORT_CTRL_IGMP_SNOOP (1 << 10) 197 #define AR8X16_PORT_CTRL_HEADER (1 << 11) 198 #define AR8X16_PORT_CTRL_MAC_LOOP (1 << 12) 199 #define AR8X16_PORT_CTRL_SINGLE_VLAN (1 << 13) 200 #define AR8X16_PORT_CTRL_LEARN (1 << 14) 201 #define AR8X16_PORT_CTRL_DOUBLE_TAG (1 << 15) 202 #define AR8X16_PORT_CTRL_MIRROR_TX (1 << 16) 203 #define AR8X16_PORT_CTRL_MIRROR_RX (1 << 17) 204 205 #define AR8X16_REG_PORT_VLAN(_p) (AR8X16_REG_PORT_BASE((_p)) + 0x0008) 206 207 #define AR8X16_PORT_VLAN_DEFAULT_ID_SHIFT 0 208 #define AR8X16_PORT_VLAN_DEST_PORTS_SHIFT 16 209 #define AR8X16_PORT_VLAN_MODE_MASK 0xc0000000 210 #define AR8X16_PORT_VLAN_MODE_SHIFT 30 211 #define AR8X16_PORT_VLAN_MODE_PORT_ONLY 0 212 #define AR8X16_PORT_VLAN_MODE_PORT_FALLBACK 1 213 #define AR8X16_PORT_VLAN_MODE_VLAN_ONLY 2 214 #define AR8X16_PORT_VLAN_MODE_SECURE 3 215 216 #define AR8X16_REG_PORT_RATE_LIM(_p) (AR8X16_REG_PORT_BASE((_p)) + 0x000c) 217 #define AR8X16_PORT_RATE_LIM_128KB 0 218 #define AR8X16_PORT_RATE_LIM_256KB 1 219 #define AR8X16_PORT_RATE_LIM_512KB 2 220 #define AR8X16_PORT_RATE_LIM_1MB 3 221 #define AR8X16_PORT_RATE_LIM_2MB 4 222 #define AR8X16_PORT_RATE_LIM_4MB 5 223 #define AR8X16_PORT_RATE_LIM_8MB 6 224 #define AR8X16_PORT_RATE_LIM_16MB 7 225 #define AR8X16_PORT_RATE_LIM_32MB 8 226 #define AR8X16_PORT_RATE_LIM_64MB 9 227 #define AR8X16_PORT_RATE_LIM_IN_EN (1 << 24) 228 #define AR8X16_PORT_RATE_LIM_OUT_EN (1 << 23) 229 #define AR8X16_PORT_RATE_LIM_IN_MASK 0x000f0000 230 #define AR8X16_PORT_RATE_LIM_IN_SHIFT 16 231 #define AR8X16_PORT_RATE_LIM_OUT_MASK 0x0000000f 232 #define AR8X16_PORT_RATE_LIM_OUT_SHIFT 0 233 234 #define AR8X16_REG_PORT_PRIORITY(_p) (AR8X16_REG_PORT_BASE((_p)) + 0x0010) 235 236 #define AR8X16_REG_STATS_BASE(_p) (0x20000 + (_p) * 0x100) 237 238 #define AR8X16_STATS_RXBROAD 0x0000 239 #define AR8X16_STATS_RXPAUSE 0x0004 240 #define AR8X16_STATS_RXMULTI 0x0008 241 #define AR8X16_STATS_RXFCSERR 0x000c 242 #define AR8X16_STATS_RXALIGNERR 0x0010 243 #define AR8X16_STATS_RXRUNT 0x0014 244 #define AR8X16_STATS_RXFRAGMENT 0x0018 245 #define AR8X16_STATS_RX64BYTE 0x001c 246 #define AR8X16_STATS_RX128BYTE 0x0020 247 #define AR8X16_STATS_RX256BYTE 0x0024 248 #define AR8X16_STATS_RX512BYTE 0x0028 249 #define AR8X16_STATS_RX1024BYTE 0x002c 250 #define AR8X16_STATS_RX1518BYTE 0x0030 251 #define AR8X16_STATS_RXMAXBYTE 0x0034 252 #define AR8X16_STATS_RXTOOLONG 0x0038 253 #define AR8X16_STATS_RXGOODBYTE 0x003c 254 #define AR8X16_STATS_RXBADBYTE 0x0044 255 #define AR8X16_STATS_RXOVERFLOW 0x004c 256 #define AR8X16_STATS_FILTERED 0x0050 257 #define AR8X16_STATS_TXBROAD 0x0054 258 #define AR8X16_STATS_TXPAUSE 0x0058 259 #define AR8X16_STATS_TXMULTI 0x005c 260 #define AR8X16_STATS_TXUNDERRUN 0x0060 261 #define AR8X16_STATS_TX64BYTE 0x0064 262 #define AR8X16_STATS_TX128BYTE 0x0068 263 #define AR8X16_STATS_TX256BYTE 0x006c 264 #define AR8X16_STATS_TX512BYTE 0x0070 265 #define AR8X16_STATS_TX1024BYTE 0x0074 266 #define AR8X16_STATS_TX1518BYTE 0x0078 267 #define AR8X16_STATS_TXMAXBYTE 0x007c 268 #define AR8X16_STATS_TXOVERSIZE 0x0080 269 #define AR8X16_STATS_TXBYTE 0x0084 270 #define AR8X16_STATS_TXCOLLISION 0x008c 271 #define AR8X16_STATS_TXABORTCOL 0x0090 272 #define AR8X16_STATS_TXMULTICOL 0x0094 273 #define AR8X16_STATS_TXSINGLECOL 0x0098 274 #define AR8X16_STATS_TXEXCDEFER 0x009c 275 #define AR8X16_STATS_TXDEFER 0x00a0 276 #define AR8X16_STATS_TXLATECOL 0x00a4 277 278 #define AR8X16_PORT_CPU 0 279 #define AR8X16_NUM_PORTS 6 280 #define AR8X16_NUM_PHYS 5 281 #define AR8X16_MAGIC 0xc000050e 282 283 #define AR8X16_PHY_ID1 0x004d 284 #define AR8X16_PHY_ID2 0xd041 285 286 #define AR8X16_PORT_MASK(_port) (1 << (_port)) 287 #define AR8X16_PORT_MASK_ALL ((1<<AR8X16_NUM_PORTS)-1) 288 #define AR8X16_PORT_MASK_BUT(_port) (AR8X16_PORT_MASK_ALL & ~(1 << (_port))) 289 290 #define AR8X16_MAX_VLANS 16 291 292 /* 293 * AR9340 switch specific definitions. 294 */ 295 296 /* XXX Linux define compatibility stuff */ 297 #define BITM(_count) ((1 << _count) - 1) 298 #define BITS(_shift, _count) (BITM(_count) << _shift) 299 300 #define AR934X_REG_OPER_MODE0 0x04 301 #define AR934X_OPER_MODE0_MAC_GMII_EN (1 << 6) 302 #define AR934X_OPER_MODE0_PHY_MII_EN (1 << 10) 303 304 #define AR934X_REG_OPER_MODE1 0x08 305 #define AR934X_REG_OPER_MODE1_PHY4_MII_EN (1 << 28) 306 307 #define AR934X_REG_FLOOD_MASK 0x2c 308 #define AR934X_FLOOD_MASK_MC_DP(_p) (1 << (16 + (_p))) 309 #define AR934X_FLOOD_MASK_BC_DP(_p) (1 << (25 + (_p))) 310 311 #define AR934X_REG_QM_CTRL 0x3c 312 #define AR934X_QM_CTRL_ARP_EN (1 << 15) 313 314 #define AR934X_REG_AT_CTRL 0x5c 315 #define AR934X_AT_CTRL_AGE_TIME BITS(0, 15) 316 #define AR934X_AT_CTRL_AGE_EN (1 << 17) 317 #define AR934X_AT_CTRL_LEARN_CHANGE (1 << 18) 318 319 #define AR934X_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100) 320 321 #define AR934X_REG_PORT_VLAN1(_port) (AR934X_REG_PORT_BASE((_port)) + 0x08) 322 #define AR934X_PORT_VLAN1_DEFAULT_SVID_S 0 323 #define AR934X_PORT_VLAN1_FORCE_DEFAULT_VID_EN (1 << 12) 324 #define AR934X_PORT_VLAN1_PORT_TLS_MODE (1 << 13) 325 #define AR934X_PORT_VLAN1_PORT_VLAN_PROP_EN (1 << 14) 326 #define AR934X_PORT_VLAN1_PORT_CLONE_EN (1 << 15) 327 #define AR934X_PORT_VLAN1_DEFAULT_CVID_S 16 328 #define AR934X_PORT_VLAN1_FORCE_PORT_VLAN_EN (1 << 28) 329 #define AR934X_PORT_VLAN1_ING_PORT_PRI_S 29 330 331 #define AR934X_REG_PORT_VLAN2(_port) (AR934X_REG_PORT_BASE((_port)) + 0x0c) 332 #define AR934X_PORT_VLAN2_PORT_VID_MEM_S 16 333 #define AR934X_PORT_VLAN2_8021Q_MODE_S 30 334 #define AR934X_PORT_VLAN2_8021Q_MODE_PORT_ONLY 0 335 #define AR934X_PORT_VLAN2_8021Q_MODE_PORT_FALLBACK 1 336 #define AR934X_PORT_VLAN2_8021Q_MODE_VLAN_ONLY 2 337 #define AR934X_PORT_VLAN2_8021Q_MODE_SECURE 3 338 339 /* 340 * AR8327 specific registers 341 */ 342 #define AR8327_NUM_PORTS 7 343 #define AR8327_NUM_PHYS 5 344 #define AR8327_PORTS_ALL 0x7f 345 346 #define AR8327_REG_MASK 0x000 347 348 #define AR8327_REG_PAD0_MODE 0x004 349 #define AR8327_REG_PAD5_MODE 0x008 350 #define AR8327_REG_PAD6_MODE 0x00c 351 352 #define AR8327_PAD_MAC_MII_RXCLK_SEL (1 << 0) 353 #define AR8327_PAD_MAC_MII_TXCLK_SEL (1 << 1) 354 #define AR8327_PAD_MAC_MII_EN (1 << 2) 355 #define AR8327_PAD_MAC_GMII_RXCLK_SEL (1 << 4) 356 #define AR8327_PAD_MAC_GMII_TXCLK_SEL (1 << 5) 357 #define AR8327_PAD_MAC_GMII_EN (1 << 6) 358 #define AR8327_PAD_SGMII_EN (1 << 7) 359 #define AR8327_PAD_PHY_MII_RXCLK_SEL (1 << 8) 360 #define AR8327_PAD_PHY_MII_TXCLK_SEL (1 << 9) 361 #define AR8327_PAD_PHY_MII_EN (1 << 10) 362 #define AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL (1 << 11) 363 #define AR8327_PAD_PHY_GMII_RXCLK_SEL (1 << 12) 364 #define AR8327_PAD_PHY_GMII_TXCLK_SEL (1 << 13) 365 #define AR8327_PAD_PHY_GMII_EN (1 << 14) 366 #define AR8327_PAD_PHYX_GMII_EN (1 << 16) 367 #define AR8327_PAD_PHYX_RGMII_EN (1 << 17) 368 #define AR8327_PAD_PHYX_MII_EN (1 << 18) 369 #define AR8327_PAD_SGMII_DELAY_EN (1 << 19) 370 #define AR8327_PAD_RGMII_RXCLK_DELAY_SEL BITS(20, 2) 371 #define AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S 20 372 #define AR8327_PAD_RGMII_TXCLK_DELAY_SEL BITS(22, 2) 373 #define AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S 22 374 #define AR8327_PAD_RGMII_RXCLK_DELAY_EN (1 << 24) 375 #define AR8327_PAD_RGMII_TXCLK_DELAY_EN (1 << 25) 376 #define AR8327_PAD_RGMII_EN (1 << 26) 377 378 #define AR8327_REG_POWER_ON_STRIP 0x010 379 #define AR8327_POWER_ON_STRIP_POWER_ON_SEL (1U << 31) 380 #define AR8327_POWER_ON_STRIP_LED_OPEN_EN (1 << 24) 381 #define AR8327_POWER_ON_STRIP_SERDES_AEN (1 << 7) 382 383 #define AR8327_REG_INT_STATUS0 0x020 384 #define AR8327_INT0_VT_DONE (1 << 20) 385 386 #define AR8327_REG_INT_STATUS1 0x024 387 #define AR8327_REG_INT_MASK0 0x028 388 #define AR8327_REG_INT_MASK1 0x02c 389 390 #define AR8327_REG_MODULE_EN 0x030 391 #define AR8327_MODULE_EN_MIB (1 << 0) 392 393 #define AR8327_REG_MIB_FUNC 0x034 394 #define AR8327_MIB_CPU_KEEP (1 << 20) 395 396 #define AR8327_REG_SERVICE_TAG 0x048 397 #define AR8327_REG_LED_CTRL0 0x050 398 #define AR8327_REG_LED_CTRL1 0x054 399 #define AR8327_REG_LED_CTRL2 0x058 400 #define AR8327_REG_LED_CTRL3 0x05c 401 #define AR8327_REG_MAC_ADDR0 0x060 402 #define AR8327_REG_MAC_ADDR1 0x064 403 404 #define AR8327_REG_MAX_FRAME_SIZE 0x078 405 #define AR8327_MAX_FRAME_SIZE_MTU BITS(0, 14) 406 407 #define AR8327_REG_PORT_STATUS(_i) (0x07c + (_i) * 4) 408 409 #define AR8327_REG_HEADER_CTRL 0x098 410 #define AR8327_REG_PORT_HEADER(_i) (0x09c + (_i) * 4) 411 412 #define AR8327_REG_SGMII_CTRL 0x0e0 413 #define AR8327_SGMII_CTRL_EN_PLL (1 << 1) 414 #define AR8327_SGMII_CTRL_EN_RX (1 << 2) 415 #define AR8327_SGMII_CTRL_EN_TX (1 << 3) 416 417 #define AR8327_REG_PORT_VLAN0(_i) (0x420 + (_i) * 0x8) 418 #define AR8327_PORT_VLAN0_DEF_SVID BITS(0, 12) 419 #define AR8327_PORT_VLAN0_DEF_SVID_S 0 420 #define AR8327_PORT_VLAN0_DEF_CVID BITS(16, 12) 421 #define AR8327_PORT_VLAN0_DEF_CVID_S 16 422 423 #define AR8327_REG_PORT_VLAN1(_i) (0x424 + (_i) * 0x8) 424 #define AR8327_PORT_VLAN1_PORT_VLAN_PROP (1 << 6) 425 #define AR8327_PORT_VLAN1_OUT_MODE BITS(12, 2) 426 #define AR8327_PORT_VLAN1_OUT_MODE_S 12 427 #define AR8327_PORT_VLAN1_OUT_MODE_UNMOD 0 428 #define AR8327_PORT_VLAN1_OUT_MODE_UNTAG 1 429 #define AR8327_PORT_VLAN1_OUT_MODE_TAG 2 430 #define AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH 3 431 432 #define AR8327_REG_ATU_DATA0 0x600 433 #define AR8327_REG_ATU_DATA1 0x604 434 #define AR8327_REG_ATU_DATA2 0x608 435 436 #define AR8327_REG_ATU_FUNC 0x60c 437 #define AR8327_ATU_FUNC_OP BITS(0, 4) 438 #define AR8327_ATU_FUNC_OP_NOOP 0x0 439 #define AR8327_ATU_FUNC_OP_FLUSH 0x1 440 #define AR8327_ATU_FUNC_OP_LOAD 0x2 441 #define AR8327_ATU_FUNC_OP_PURGE 0x3 442 #define AR8327_ATU_FUNC_OP_FLUSH_LOCKED 0x4 443 #define AR8327_ATU_FUNC_OP_FLUSH_UNICAST 0x5 444 #define AR8327_ATU_FUNC_OP_GET_NEXT 0x6 445 #define AR8327_ATU_FUNC_OP_SEARCH_MAC 0x7 446 #define AR8327_ATU_FUNC_OP_CHANGE_TRUNK 0x8 447 #define AR8327_ATU_FUNC_BUSY (1U << 31) 448 449 #define AR8327_REG_VTU_FUNC0 0x0610 450 #define AR8327_VTU_FUNC0_EG_MODE BITS(4, 14) 451 #define AR8327_VTU_FUNC0_EG_MODE_S(_i) (4 + (_i) * 2) 452 #define AR8327_VTU_FUNC0_EG_MODE_KEEP 0 453 #define AR8327_VTU_FUNC0_EG_MODE_UNTAG 1 454 #define AR8327_VTU_FUNC0_EG_MODE_TAG 2 455 #define AR8327_VTU_FUNC0_EG_MODE_NOT 3 456 #define AR8327_VTU_FUNC0_IVL (1 << 19) 457 #define AR8327_VTU_FUNC0_VALID (1 << 20) 458 459 #define AR8327_REG_VTU_FUNC1 0x0614 460 #define AR8327_VTU_FUNC1_OP BITS(0, 3) 461 #define AR8327_VTU_FUNC1_OP_NOOP 0 462 #define AR8327_VTU_FUNC1_OP_FLUSH 1 463 #define AR8327_VTU_FUNC1_OP_LOAD 2 464 #define AR8327_VTU_FUNC1_OP_PURGE 3 465 #define AR8327_VTU_FUNC1_OP_REMOVE_PORT 4 466 #define AR8327_VTU_FUNC1_OP_GET_NEXT 5 467 #define AR8327_VTU_FUNC1_OP_GET_ONE 6 468 #define AR8327_VTU_FUNC1_FULL (1 << 4) 469 #define AR8327_VTU_FUNC1_PORT (1 << 8, 4) 470 #define AR8327_VTU_FUNC1_PORT_S 8 471 #define AR8327_VTU_FUNC1_VID (1 << 16, 12) 472 #define AR8327_VTU_FUNC1_VID_S 16 473 #define AR8327_VTU_FUNC1_BUSY (1U << 31) 474 475 #define AR8327_REG_FWD_CTRL0 0x620 476 #define AR8327_FWD_CTRL0_CPU_PORT_EN (1 << 10) 477 #define AR8327_FWD_CTRL0_MIRROR_PORT BITS(4, 4) 478 #define AR8327_FWD_CTRL0_MIRROR_PORT_S 4 479 480 #define AR8327_REG_FWD_CTRL1 0x624 481 #define AR8327_FWD_CTRL1_UC_FLOOD BITS(0, 7) 482 #define AR8327_FWD_CTRL1_UC_FLOOD_S 0 483 #define AR8327_FWD_CTRL1_MC_FLOOD BITS(8, 7) 484 #define AR8327_FWD_CTRL1_MC_FLOOD_S 8 485 #define AR8327_FWD_CTRL1_BC_FLOOD BITS(16, 7) 486 #define AR8327_FWD_CTRL1_BC_FLOOD_S 16 487 #define AR8327_FWD_CTRL1_IGMP BITS(24, 7) 488 #define AR8327_FWD_CTRL1_IGMP_S 24 489 490 #define AR8327_REG_PORT_LOOKUP(_i) (0x660 + (_i) * 0xc) 491 #define AR8327_PORT_LOOKUP_MEMBER BITS(0, 7) 492 #define AR8327_PORT_LOOKUP_IN_MODE BITS(8, 2) 493 #define AR8327_PORT_LOOKUP_IN_MODE_S 8 494 #define AR8327_PORT_LOOKUP_STATE BITS(16, 3) 495 #define AR8327_PORT_LOOKUP_STATE_S 16 496 #define AR8327_PORT_LOOKUP_LEARN (1 << 20) 497 #define AR8327_PORT_LOOKUP_ING_MIRROR_EN (1 << 25) 498 499 #define AR8327_REG_PORT_PRIO(_i) (0x664 + (_i) * 0xc) 500 501 #define AR8327_REG_PORT_HOL_CTRL1(_i) (0x974 + (_i) * 0x8) 502 #define AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN (1 << 16) 503 504 #define AR8327_REG_PORT_STATS_BASE(_i) (0x1000 + (_i) * 0x100) 505 506 #endif /* __AR8X16_SWITCHREG_H__ */ 507