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Searched refs:vram_start (Results 1 – 25 of 41) sorted by relevance

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/openbsd/src/sys/dev/pci/drm/radeon/
Dradeon_test.c87 void **vram_start, **vram_end; in radeon_do_test_moves() local
149 vram_start = vram_map, vram_end = vram_map + size; in radeon_do_test_moves()
150 vram_start < vram_end; in radeon_do_test_moves()
151 gtt_start++, vram_start++) { in radeon_do_test_moves()
152 if (*vram_start != gtt_start) { in radeon_do_test_moves()
156 i, *vram_start, gtt_start, in radeon_do_test_moves()
161 (vram_addr - rdev->mc.vram_start + in radeon_do_test_moves()
166 *vram_start = vram_start; in radeon_do_test_moves()
200 vram_start = vram_map, vram_end = vram_map + size; in radeon_do_test_moves()
202 gtt_start++, vram_start++) { in radeon_do_test_moves()
[all …]
Drv515.c360 upper_32_bits(rdev->mc.vram_start)); in rv515_mc_resume()
362 upper_32_bits(rdev->mc.vram_start)); in rv515_mc_resume()
365 upper_32_bits(rdev->mc.vram_start)); in rv515_mc_resume()
367 upper_32_bits(rdev->mc.vram_start)); in rv515_mc_resume()
371 (u32)rdev->mc.vram_start); in rv515_mc_resume()
373 (u32)rdev->mc.vram_start); in rv515_mc_resume()
375 WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start); in rv515_mc_resume()
454 S_000001_MC_FB_START(rdev->mc.vram_start >> 16) | in rv515_mc_program()
457 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); in rv515_mc_program()
Dr520.c147 S_000004_MC_FB_START(rdev->mc.vram_start >> 16) | in r520_mc_program()
150 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); in r520_mc_program()
Drv770.c1032 if (rdev->mc.vram_start < rdev->mc.gtt_start) { in rv770_mc_program()
1035 rdev->mc.vram_start >> 12); in rv770_mc_program()
1047 rdev->mc.vram_start >> 12); in rv770_mc_program()
1053 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); in rv770_mc_program()
1055 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); in rv770_mc_program()
1622 mc->vram_start = mc->gtt_start - mc->mc_vram_size; in r700_vram_gtt_location()
1629 mc->vram_start = mc->gtt_end + 1; in r700_vram_gtt_location()
1631 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; in r700_vram_gtt_location()
1633 mc->mc_vram_size >> 20, mc->vram_start, in r700_vram_gtt_location()
Dradeon_device.c582 mc->vram_start = base; in radeon_vram_location()
588 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; in radeon_vram_location()
589 if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) { in radeon_vram_location()
594 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; in radeon_vram_location()
598 mc->mc_vram_size >> 20, mc->vram_start, in radeon_vram_location()
619 size_bf = mc->vram_start & ~mc->gtt_base_align; in radeon_gtt_location()
625 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size; in radeon_gtt_location()
Dradeon_object.h103 start = rdev->mc.vram_start; in radeon_bo_gpu_offset()
Drs600.c610 WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start); in rs600_gart_enable()
977 S_000004_MC_FB_START(rdev->mc.vram_start >> 16) | in rs600_mc_program()
980 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); in rs600_mc_program()
Devergreen.c2769 upper_32_bits(rdev->mc.vram_start)); in evergreen_mc_resume()
2771 upper_32_bits(rdev->mc.vram_start)); in evergreen_mc_resume()
2773 (u32)rdev->mc.vram_start); in evergreen_mc_resume()
2775 (u32)rdev->mc.vram_start); in evergreen_mc_resume()
2779 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start)); in evergreen_mc_resume()
2780 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start); in evergreen_mc_resume()
2873 if (rdev->mc.vram_start < rdev->mc.gtt_start) { in evergreen_mc_program()
2876 rdev->mc.vram_start >> 12); in evergreen_mc_program()
2888 rdev->mc.vram_start >> 12); in evergreen_mc_program()
2899 tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20; in evergreen_mc_program()
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Dr600.c1326 if (rdev->mc.vram_start < rdev->mc.gtt_start) { in r600_mc_program()
1329 rdev->mc.vram_start >> 12); in r600_mc_program()
1340 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12); in r600_mc_program()
1345 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); in r600_mc_program()
1347 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); in r600_mc_program()
1408 mc->vram_start = mc->gtt_start - mc->mc_vram_size; in r600_vram_gtt_location()
1415 mc->vram_start = mc->gtt_end + 1; in r600_vram_gtt_location()
1417 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; in r600_vram_gtt_location()
1419 mc->mc_vram_size >> 20, mc->vram_start, in r600_vram_gtt_location()
Dradeon_ttm.c159 old_start += rdev->mc.vram_start; in radeon_move_blit()
170 new_start += rdev->mc.vram_start; in radeon_move_blit()
Dradeon_fbdev.c269 tmp = radeon_bo_gpu_offset(rbo) - rdev->mc.vram_start; in radeon_fbdev_fb_helper_fb_probe()
Drs690.c688 S_000100_MC_FB_START(rdev->mc.vram_start >> 16) | in rs690_mc_program()
691 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); in rs690_mc_program()
Drs400.c400 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | in rs400_mc_program()
Dr300.c175 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start); in rv370_pcie_gart_enable()
1351 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | in r300_mc_program()
/openbsd/src/sys/dev/pci/drm/amd/amdgpu/
Damdgpu_gmc.c212 mc->vram_start = base; in amdgpu_gmc_vram_location()
213 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; in amdgpu_gmc_vram_location()
224 mc->fb_start = mc->vram_start; in amdgpu_gmc_vram_location()
228 mc->mc_vram_size >> 20, mc->vram_start, in amdgpu_gmc_vram_location()
252 mc->vram_start = mc->xgmi.node_segment_size * mc->xgmi.physical_node_id; in amdgpu_gmc_sysvm_location()
253 mc->vram_end = mc->vram_start + mc->xgmi.node_segment_size - 1; in amdgpu_gmc_sysvm_location()
259 mc->mc_vram_size >> 20, mc->vram_start, in amdgpu_gmc_sysvm_location()
1062 return mc_addr - adev->gmc.vram_start + adev->vm_manager.vram_base_offset; in amdgpu_gmc_vram_mc2pa()
1086 return amdgpu_bo_gpu_offset(bo) - adev->gmc.vram_start + adev->gmc.aper_base; in amdgpu_gmc_vram_cpu_pa()
Dhdp_v4_0.c168 WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8)); in hdp_v4_0_init_registers()
169 WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE_HI, (adev->gmc.vram_start >> 40)); in hdp_v4_0_init_registers()
Damdgpu_fw_attestation.c82 vram_pos = records_addr - adev->gmc.vram_start; in amdgpu_fw_attestation_debugfs_read()
Dimu_v11_0_3.c126 data = adev->gmc.vram_start >> 24; in program_rlc_ram_register_setting()
Dgfxhub_v12_0.c174 value = adev->mem_scratch.gpu_addr - adev->gmc.vram_start in gfxhub_v12_0_init_system_aperture_regs()
369 adev->gmc.vram_start >> 24); in gfxhub_v12_0_gart_enable()
Dgfxhub_v2_1.c366 adev->gmc.vram_start >> 24); in gfxhub_v2_1_gart_enable()
652 WREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE, adev->gmc.vram_start >> 24); in gfxhub_v2_1_restore_regs()
Damdgpu_gmc.h263 u64 vram_start; member
Dgmc_v8_0.c458 adev->gmc.vram_start >> 12); in gmc_v8_0_mc_program()
466 tmp |= ((adev->gmc.vram_start >> 24) & 0xFFFF); in gmc_v8_0_mc_program()
469 WREG32(mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8)); in gmc_v8_0_mc_program()
Dimu_v11_0.c336 data = adev->gmc.vram_start >> 24; in program_imu_rlc_ram()
Dimu_v12_0.c269 data = adev->gmc.vram_start >> 24; in program_imu_rlc_ram_old()
Dgfxhub_v11_5_0.c364 adev->gmc.vram_start >> 24); in gfxhub_v11_5_0_gart_enable()

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