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Searched refs:vclk_div (Results 1 – 6 of 6) sorted by relevance

/openbsd/src/sys/dev/pci/drm/radeon/
Dradeon_uvd.c968 unsigned vclk_div, dclk_div, score; in radeon_uvd_calc_upll_dividers() local
979 vclk_div = radeon_uvd_calc_upll_post_div(vco_freq, vclk, in radeon_uvd_calc_upll_dividers()
981 if (vclk_div > pd_max) in radeon_uvd_calc_upll_dividers()
991 score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div); in radeon_uvd_calc_upll_dividers()
996 *optimal_vclk_div = vclk_div; in radeon_uvd_calc_upll_dividers()
Drv770.c56 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; in rv770_set_uvd_clocks() local
76 &fb_div, &vclk_div, &dclk_div); in rv770_set_uvd_clocks()
81 vclk_div -= 1; in rv770_set_uvd_clocks()
104 UPLL_SW_HILEN(vclk_div >> 1) | in rv770_set_uvd_clocks()
105 UPLL_SW_LOLEN((vclk_div >> 1) + (vclk_div & 1)) | in rv770_set_uvd_clocks()
Dr600.c205 unsigned fb_div = 0, ref_div, vclk_div = 0, dclk_div = 0; in r600_set_uvd_clocks() local
234 &fb_div, &vclk_div, &dclk_div); in r600_set_uvd_clocks()
261 UPLL_SW_HILEN(vclk_div >> 1) | in r600_set_uvd_clocks()
262 UPLL_SW_LOLEN((vclk_div >> 1) + (vclk_div & 1)) | in r600_set_uvd_clocks()
Devergreen.c1192 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; in evergreen_set_uvd_clocks() local
1211 &fb_div, &vclk_div, &dclk_div); in evergreen_set_uvd_clocks()
1250 UPLL_PDIV_A(vclk_div) | UPLL_PDIV_B(dclk_div), in evergreen_set_uvd_clocks()
Dsi.c6979 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; in si_set_uvd_clocks() local
6997 &fb_div, &vclk_div, &dclk_div); in si_set_uvd_clocks()
7038 UPLL_PDIV_A(vclk_div) | UPLL_PDIV_B(dclk_div), in si_set_uvd_clocks()
/openbsd/src/sys/dev/pci/drm/amd/amdgpu/
Damdgpu_si.c1732 unsigned vclk_div, dclk_div, score; in si_calc_upll_dividers() local
1743 vclk_div = si_uvd_calc_upll_post_div(vco_freq, vclk, in si_calc_upll_dividers()
1745 if (vclk_div > pd_max) in si_calc_upll_dividers()
1755 score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div); in si_calc_upll_dividers()
1760 *optimal_vclk_div = vclk_div; in si_calc_upll_dividers()
1777 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; in si_set_uvd_clocks() local
1795 &fb_div, &vclk_div, &dclk_div); in si_set_uvd_clocks()
1838 UPLL_PDIV_A(vclk_div) | UPLL_PDIV_B(dclk_div), in si_set_uvd_clocks()