Home
last modified time | relevance | path

Searched refs:v2i16 (Results 1 – 25 of 50) sorted by relevance

12

/openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/
DAMDGPUCallingConv.td25 CCIfInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16] , CCAssignToReg<[
32 CCIfNotInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16] , CCAssignToReg<[
39 CCIfType<[i32, f32, v2i16, v2f16, i16, f16, i1], CCAssignToStack<4, 4>>
46 CCIfNotInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16] , CCAssignToReg<[
69 CCIfInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16] , CCAssignToReg<[
79 CCIfNotInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16] , CCAssignToReg<[
102 CCIfType<[i32, i16, v2i16] , CCAssignToReg<[
186 CCIfType<[i32, f32, i16, f16, v2i16, v2f16, i1], CCAssignToReg<[
191 CCIfType<[i32, f32, v2i16, v2f16, i16, f16, i1], CCAssignToStack<4, 4>>
198 CCIfType<[i32, f32, i16, f16, v2i16, v2f16], CCAssignToReg<[
DSIRegisterInfo.td411 def SGPR_32 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
460 def TTMP_32 : SIRegisterClass<"AMDGPU", [i32, f32, v2i16, v2f16], 32,
594 def Reg32Types : RegisterTypes<[i32, f32, v2i16, v2f16, p2, p3, p5, p6]>;
682 def AGPR_32 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
734 def Pseudo_SReg_32 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
759 def SReg_32_XM0_XEXEC : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32,
781 def SReg_32_XEXEC : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32,
786 def SReg_32_XEXEC_HI : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32,
791 def SReg_32_XM0 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32,
799 def SReg_32 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32,
[all …]
DSIInstrInfo.td327 // XXX - do v2i16 instructions?
342 bit ret = !or(!eq(SrcVT.Value, v2i16.Value),
1676 !if(!eq(VT.Value, v2i16.Value),
1744 !if(!eq(VT.Value, v2i16.Value),
1764 !if (!eq(VT.Value, v2i16.Value), VCSrc_v2b16,
1774 !eq(SrcVT.Value, v2i16.Value),
2653 def VOP_V2I16_V2I16_V2I16 : VOPProfile <[v2i16, v2i16, v2i16, untyped]>;
2657 def VOP_V2I16_V2I16_V2I16_V2I16 : VOPProfile <[v2i16, v2i16, v2i16, v2i16]>;
2658 def VOP_V2I16_F32_F32 : VOPProfile <[v2i16, f32, f32, untyped]>;
2659 def VOP_V2I16_I32_I32 : VOPProfile <[v2i16, i32, i32, untyped]>;
[all …]
DSIInstructions.td1348 (v2i16 (EXTRACT_SUBREG v4i16:$vec, sub0))
1353 (v2i16 (EXTRACT_SUBREG v4i16:$vec, sub1))
1437 def : BitConvert <v2i16, i32, SReg_32>;
1438 def : BitConvert <i32, v2i16, SReg_32>;
1441 def : BitConvert <v2i16, v2f16, SReg_32>;
1442 def : BitConvert <v2f16, v2i16, SReg_32>;
1445 def : BitConvert <v2i16, f32, SReg_32>;
1446 def : BitConvert <f32, v2i16, SReg_32>;
2668 (v2i16 (bswap v2i16:$a)),
2837 (v2i16 (UniformBinFrag<build_vector> (i16 0), (i16 SReg_32:$src1))),
[all …]
DEXPInstructions.td167 def : ExpComprPattern<v2i16, EXP, 0>;
168 def : ExpComprPattern<v2i16, EXP_DONE, -1>;
DFLATInstructions.td1199 def : FlatLoadPat_D16 <FLAT_LOAD_UBYTE_D16_HI, az_extloadi8_d16_hi_flat, v2i16>;
1201 def : FlatLoadPat_D16 <FLAT_LOAD_SBYTE_D16_HI, sextloadi8_d16_hi_flat, v2i16>;
1203 def : FlatLoadPat_D16 <FLAT_LOAD_SHORT_D16_HI, load_d16_hi_flat, v2i16>;
1206 def : FlatLoadPat_D16 <FLAT_LOAD_UBYTE_D16, az_extloadi8_d16_lo_flat, v2i16>;
1208 def : FlatLoadPat_D16 <FLAT_LOAD_SBYTE_D16, sextloadi8_d16_lo_flat, v2i16>;
1210 def : FlatLoadPat_D16 <FLAT_LOAD_SHORT_D16, load_d16_lo_flat, v2i16>;
1408 defm : GlobalFLATLoadPats_D16 <GLOBAL_LOAD_UBYTE_D16_HI, az_extloadi8_d16_hi_global, v2i16>;
1410 defm : GlobalFLATLoadPats_D16 <GLOBAL_LOAD_SBYTE_D16_HI, sextloadi8_d16_hi_global, v2i16>;
1412 defm : GlobalFLATLoadPats_D16 <GLOBAL_LOAD_SHORT_D16_HI, load_d16_hi_global, v2i16>;
1415 defm : GlobalFLATLoadPats_D16 <GLOBAL_LOAD_UBYTE_D16, az_extloadi8_d16_lo_global, v2i16>;
[all …]
DDSInstructions.td787 def : DSReadPat_D16<DS_READ_U16_D16_HI, load_d16_hi_local, v2i16>;
789 def : DSReadPat_D16<DS_READ_U8_D16_HI, az_extloadi8_d16_hi_local, v2i16>;
791 def : DSReadPat_D16<DS_READ_I8_D16_HI, sextloadi8_d16_hi_local, v2i16>;
794 def : DSReadPat_D16<DS_READ_U16_D16, load_d16_lo_local, v2i16>;
796 def : DSReadPat_D16<DS_READ_U8_D16, az_extloadi8_d16_lo_local, v2i16>;
798 def : DSReadPat_D16<DS_READ_I8_D16, sextloadi8_d16_lo_local, v2i16>;
1141 (v2i16 (int_amdgcn_ds_fadd_v2bf16 i32:$ptr, v2i16:$src)),
1146 (v2i16 (int_amdgcn_ds_fadd_v2bf16_noret i32:$ptr, v2i16:$src)),
DSIISelLowering.cpp149 addRegisterClass(MVT::v2i16, &AMDGPU::SReg_32RegClass); in SITargetLowering()
186 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Expand); in SITargetLowering()
197 setTruncStoreAction(MVT::v2i16, MVT::v2i8, Expand); in SITargetLowering()
237 {MVT::v2i1, MVT::v4i1, MVT::v2i8, MVT::v4i8, MVT::v2i16, in SITargetLowering()
376 {MVT::v2i16, MVT::v2f16, MVT::v2i8, MVT::v4i8, MVT::v8i8, in SITargetLowering()
537 for (MVT VT : {MVT::v2i16, MVT::v2f16, MVT::v4i16, MVT::v4f16, MVT::v8i16, in SITargetLowering()
564 setOperationAction(ISD::BSWAP, {MVT::i16, MVT::v2i16}, Legal); in SITargetLowering()
568 setOperationAction(ISD::Constant, {MVT::v2i16, MVT::v2f16}, Legal); in SITargetLowering()
570 setOperationAction(ISD::UNDEF, {MVT::v2i16, MVT::v2f16}, Legal); in SITargetLowering()
572 setOperationAction(ISD::STORE, MVT::v2i16, Promote); in SITargetLowering()
[all …]
DVOP3PInstructions.td128 (add (v2i16 (VOP3PMods v2i16:$src0, i32:$src0_modifiers)), NegSubInlineConstV216:$src1),
134 (pat (v2i16 (VOP3PMods v2i16:$src0, i32:$src0_modifiers)),
135 (v2i16 (VOP3PMods v2i16:$src1, i32:$src1_modifiers))),
DBUFInstructions.td1292 defm : MUBUF_LoadIntrinsicPat<SIbuffer_load_format_d16, v2i16, "BUFFER_LOAD_FORMAT_D16_XY">;
1301 defm : MUBUF_LoadIntrinsicPat<SIbuffer_load, v2i16, "BUFFER_LOAD_DWORD">;
1375 defm : MUBUF_StoreIntrinsicPat<SIbuffer_store_format_d16, v2i16, "BUFFER_STORE_FORMAT_D16_XY">;
1384 defm : MUBUF_StoreIntrinsicPat<SIbuffer_store, v2i16, "BUFFER_STORE_DWORD">;
1802 …dPat_D16<BUFFER_LOAD_SHORT_D16_HI_OFFEN, BUFFER_LOAD_SHORT_D16_HI_OFFSET, v2i16, load_d16_hi_priva…
1803 …dPat_D16<BUFFER_LOAD_UBYTE_D16_HI_OFFEN, BUFFER_LOAD_UBYTE_D16_HI_OFFSET, v2i16, az_extloadi8_d16_…
1804 …dPat_D16<BUFFER_LOAD_SBYTE_D16_HI_OFFEN, BUFFER_LOAD_SBYTE_D16_HI_OFFSET, v2i16, sextloadi8_d16_hi…
1809 defm : MUBUFScratchLoadPat_D16<BUFFER_LOAD_SHORT_D16_OFFEN, BUFFER_LOAD_SHORT_D16_OFFSET, v2i16, lo…
1810 defm : MUBUFScratchLoadPat_D16<BUFFER_LOAD_UBYTE_D16_OFFEN, BUFFER_LOAD_UBYTE_D16_OFFSET, v2i16, az…
1811 defm : MUBUFScratchLoadPat_D16<BUFFER_LOAD_SBYTE_D16_OFFEN, BUFFER_LOAD_SBYTE_D16_OFFSET, v2i16, se…
/openbsd/src/gnu/llvm/llvm/lib/Target/Mips/
DMipsDSPInstrInfo.td1331 def : BitconvertPat<i32, v2i16, GPR32, DSPR>;
1333 def : BitconvertPat<v2i16, i32, DSPR, GPR32>;
1335 def : BitconvertPat<f32, v2i16, FGR32, DSPR>;
1337 def : BitconvertPat<v2i16, f32, DSPR, FGR32>;
1340 def : DSPPat<(v2i16 (load addr:$a)),
1341 (v2i16 (COPY_TO_REGCLASS (LW addr:$a), DSPR))>;
1344 def : DSPPat<(store (v2i16 DSPR:$val), addr:$a),
1354 def : DSPBinPat<ADDQ_PH, v2i16, int_mips_addq_ph>;
1355 def : DSPBinPat<ADDQ_PH, v2i16, add>;
1356 def : DSPBinPat<SUBQ_PH, v2i16, int_mips_subq_ph>;
[all …]
DMipsRegisterInfo.td318 def DSPR : GPR32Class<[v4i8, v2i16]>;
476 def DSPCC : RegisterClass<"Mips", [v4i8, v2i16], 32, (add DSPCCond)>;
DMipsSEISelLowering.cpp86 MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8}; in MipsSETargetLowering()
112 setOperationAction(ISD::MUL, MVT::v2i16, Legal); in MipsSETargetLowering()
868 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8)) in performSHLCombine()
925 if ((Ty != MVT::v2i16) && ((Ty != MVT::v4i8) || !Subtarget.hasDSPR2())) in performSRACombine()
937 if (((Ty != MVT::v2i16) || !Subtarget.hasDSPR2()) && (Ty != MVT::v4i8)) in performSRLCombine()
944 bool IsV216 = (Ty == MVT::v2i16); in isLegalDSPCondCode()
964 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8)) in performSETCCCombine()
977 if (Ty == MVT::v2i16 || Ty == MVT::v4i8) { in performVSELECTCombine()
/openbsd/src/gnu/llvm/llvm/lib/Target/Hexagon/
DHexagonCallingConv.td15 CCIfType<[i32,v2i16,v4i8],
39 CCIfType<[i32,v2i16,v4i8],
69 CCIfType<[i32,v2i16,v4i8],
97 CCIfType<[i32,v2i16,v4i8],
DHexagonPatterns.td84 def V2I16: PatLeaf<(v2i16 IntRegs:$R)>;
476 // All of these are bitcastable to one another: i32, v2i16, v4i8.
477 defm: NopCast_pat<i32, v2i16, IntRegs>;
479 defm: NopCast_pat<v2i16, v4i8, IntRegs>;
518 def: Pat<(v2i16 (sext V2I1:$Pu)), (S2_vtrunehb (C2_mask V2I1:$Pu))>;
527 def: Pat<(v2i16 (azext V2I1:$Pu)),
546 def: Pat<(v2i32 (sext_inreg V2I32:$Rs, v2i16)),
562 def: Pat<(v2i16 (trunc V2I32:$Rs)),
577 def: Pat<(v2i16 (ssat V2I32:$Rs, v2i16)), (S2_vsatwh V2I32:$Rs)>;
579 def: Pat<(v2i16 (usat V2I32:$Rs, v2i16)), (S2_vsatwuh V2I32:$Rs)>;
[all …]
DHexagonISelLowering.cpp638 VT == MVT::v2i16 || VT == MVT::v2i32 || VT == MVT::v4i8 || in getPostIndexedAddressParts()
1036 if (OpTy == MVT::v2i16 || OpTy == MVT::v4i8) { in LowerSETCC()
1094 if (OpTy == MVT::v2i16 || OpTy == MVT::v4i8) { in LowerVSELECT()
1470 addRegisterClass(MVT::v2i16, &Hexagon::IntRegsRegClass); in HexagonTargetLowering()
1518 setOperationAction(ISD::SETCC, MVT::v2i16, Custom); in HexagonTargetLowering()
1676 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, MVT::v2i8, Legal); in HexagonTargetLowering()
1677 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i16, MVT::v2i8, Legal); in HexagonTargetLowering()
1678 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, MVT::v2i8, Legal); in HexagonTargetLowering()
1684 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Legal); in HexagonTargetLowering()
1689 MVT::v8i8, MVT::v2i16, MVT::v4i16, MVT::v2i32}) { in HexagonTargetLowering()
[all …]
DHexagonRegisterInfo.td533 def IntRegs : RegisterClass<"Hexagon", [i32, f32, v4i8, v2i16], 32,
553 [i1, v2i1, v4i1, v8i1, v4i8, v2i16, i32], 32, (add P0, P1, P2, P3)>;
/openbsd/src/gnu/llvm/llvm/lib/Target/RISCV/
DRISCVTargetTransformInfo.cpp456 {Intrinsic::bswap, MVT::v2i16, 3},
482 {Intrinsic::vp_bswap, MVT::v2i16, 3},
519 {Intrinsic::vp_fshl, MVT::v2i16, 7},
557 {Intrinsic::vp_fshr, MVT::v2i16, 7},
593 {Intrinsic::bitreverse, MVT::v2i16, 24},
628 {Intrinsic::vp_bitreverse, MVT::v2i16, 24},
663 {Intrinsic::ctpop, MVT::v2i16, 19},
698 {Intrinsic::vp_ctpop, MVT::v2i16, 19},
735 {Intrinsic::vp_ctlz, MVT::v2i16, 28},
773 {Intrinsic::vp_cttz, MVT::v2i16, 23},
/openbsd/src/gnu/llvm/llvm/include/llvm/Support/
DMachineValueType.h98 v2i16 = 45, // 2 x i16 enumerator
412 SimpleTy == MVT::v2i16 || SimpleTy == MVT::v1i32 || in is32BitVector()
589 case v2i16: in getVectorElementType()
864 case v2i16: in getVectorMinNumElements()
968 case v2i16: in getSizeInBits()
1305 if (NumElements == 2) return MVT::v2i16; in getVectorVT()
/openbsd/src/gnu/llvm/llvm/include/llvm/IR/
DIntrinsicsNVVM.td2562 "llvm.nvvm.suld.1d.v2i16.clamp">;
2607 "llvm.nvvm.suld.1d.array.v2i16.clamp">;
2652 "llvm.nvvm.suld.2d.v2i16.clamp">;
2697 "llvm.nvvm.suld.2d.array.v2i16.clamp">;
2742 "llvm.nvvm.suld.3d.v2i16.clamp">;
2788 "llvm.nvvm.suld.1d.v2i16.trap">;
2833 "llvm.nvvm.suld.1d.array.v2i16.trap">;
2878 "llvm.nvvm.suld.2d.v2i16.trap">;
2923 "llvm.nvvm.suld.2d.array.v2i16.trap">;
2968 "llvm.nvvm.suld.3d.v2i16.trap">;
[all …]
/openbsd/src/gnu/llvm/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp1530 {TTI::SK_Broadcast, MVT::v2i16, 1}, // pshuflw in getShuffleCost()
1536 {TTI::SK_Reverse, MVT::v2i16, 1}, // pshuflw in getShuffleCost()
1541 {TTI::SK_Splice, MVT::v2i16, 2}, // punpck+psrldq in getShuffleCost()
1546 {TTI::SK_PermuteTwoSrc, MVT::v2i16, 2}, // punpck/pshuflw in getShuffleCost()
1552 {TTI::SK_PermuteSingleSrc, MVT::v2i16, 1}, // pshuflw in getShuffleCost()
2085 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 1 }, in getCastInstrCost()
2104 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 2 }, in getCastInstrCost()
2122 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, in getCastInstrCost()
2140 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i16, 2 }, // vpmovwb in getCastInstrCost()
2200 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 3 }, // sext+vpsllq+vptestmq in getCastInstrCost()
[all …]
/openbsd/src/gnu/llvm/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp661 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i16, 2 }, in getCastInstrCost()
662 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i16, 2 }, in getCastInstrCost()
684 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 }, in getCastInstrCost()
685 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 }, in getCastInstrCost()
716 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i16, 3 }, in getCastInstrCost()
717 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 3 }, in getCastInstrCost()
809 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i16, 10 }, in getCastInstrCost()
810 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i16, 2 }, in getCastInstrCost()
/openbsd/src/gnu/llvm/llvm/lib/Target/AArch64/
DAArch64TargetTransformInfo.cpp1826 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i64, 1}, // xtn in getCastInstrCost()
1892 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 3 }, in getCastInstrCost()
1895 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i16, 3 }, in getCastInstrCost()
1916 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i16, 4 }, in getCastInstrCost()
1919 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 4 }, in getCastInstrCost()
1936 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f32, 1 }, in getCastInstrCost()
1939 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f32, 1 }, in getCastInstrCost()
1960 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f64, 2 }, in getCastInstrCost()
1963 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f64, 2 }, in getCastInstrCost()
2308 {ISD::SDIV, MVT::v8i8, 8}, {ISD::SDIV, MVT::v2i16, 5}, in getArithmeticInstrCost()
[all …]
DAArch64SchedFalkorDetails.td681 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(S|U)QADD(v1i8|v1i16|v2i16|v1i32|v1i64|v2i32|v4i…
685 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(S|U)QSUB(v1i8|v1i16|v2i16|v1i32|v1i64|v2i32|v4i…
690 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(SU|US)QADD(v1i8|v1i16|v2i16|v1i32|v1i64|v2i32|v…
/openbsd/src/gnu/llvm/llvm/lib/Target/SystemZ/
DSystemZRegisterInfo.td267 defm VR32 : SystemZRegClass<"VR32", [f32, v4i8, v2i16], 32,

12