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Searched refs:v2f32 (Results 1 – 25 of 52) sorted by relevance

123

/openbsd/src/gnu/llvm/llvm/lib/Target/AArch64/
DAArch64InstrGISel.td262 def : Pat<(f32 (fadd (vector_extract (v2f32 FPR64:$Rn), (i64 0)),
263 (vector_extract (v2f32 FPR64:$Rn), (i64 1)))),
264 (f32 (FADDPv2i32p (v2f32 FPR64:$Rn)))>;
271 def : Pat<(v2f32 (sint_to_fp v2i64:$src)),
273 def : Pat<(v2f32 (uint_to_fp v2i64:$src)),
276 def : Pat<(v2i64 (fp_to_sint v2f32:$src)),
278 def : Pat<(v2i64 (fp_to_uint v2f32:$src)),
DAArch64CallingConvention.td28 CCIfType<[v2f32], CCBitConvertToType<v2i32>>,
33 CCIfBigEndian<CCIfType<[v2i32, v2f32, v4i16, v4f16, v4bf16, v8i8],
106 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16, v4bf16],
114 CCIfType<[i64, f64, v1f64, v2f32, v1i64, v2i32, v4i16, v8i8, v4f16, v4bf16],
123 CCIfType<[v2f32], CCBitConvertToType<v2i32>>,
131 CCIfBigEndian<CCIfType<[v2i32, v2f32, v4i16, v4f16, v4bf16, v8i8],
143 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16, v4bf16],
172 CCIfType<[f64, v1f64, v1i64, v2f32, v2i32, v4i16, v4f16, v4bf16, v8i8, iPTR],
220 CCIfType<[v2f32], CCBitConvertToType<v2i32>>,
257 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16, v4bf16],
[all …]
DAArch64ISelDAGToDAG.cpp2341 if ((VT != MVT::v2f64 || NarrowVT != MVT::v2f32) && in tryHighFPExt()
4283 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) { in Select()
4310 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) { in Select()
4337 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) { in Select()
4364 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) { in Select()
4391 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) { in Select()
4418 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) { in Select()
4445 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) { in Select()
4472 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) { in Select()
4499 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) { in Select()
[all …]
DAArch64InstrInfo.td1083 def : Pat<(v2f32 (int_aarch64_neon_bfdot
1084 (v2f32 V64:$Rd), (v4bf16 V64:$Rn),
1092 (BF16DOTlanev4bf16 (v2f32 V64:$Rd), (v4bf16 V64:$Rn),
1282 def : Pat<(v2f32 (int_aarch64_neon_vcadd_rot90 (v2f32 V64:$Rn), (v2f32 V64:$Rm))),
1283 (FCADDv2f32 (v2f32 V64:$Rn), (v2f32 V64:$Rm), (i32 0))>;
1284 def : Pat<(v2f32 (int_aarch64_neon_vcadd_rot270 (v2f32 V64:$Rn), (v2f32 V64:$Rm))),
1285 (FCADDv2f32 (v2f32 V64:$Rn), (v2f32 V64:$Rm), (i32 1))>;
1327 defm : FCMLA_PATS<v2f32, V64>;
2795 defm : ScalToVecROLoadPat<ro32, load, f32, v2f32, LDRSroW, LDRSroX, ssub>;
2829 defm : VecROLoadPat<ro64, v2f32, LDRDroW, LDRDroX>;
[all …]
DAArch64SchedA57.td438 // D form - v2f32
446 def : InstRW<[A57Write_5cyc_1V], (instregex "^(FABD|FADD|FSUB)(v2f32|32|64|v2i32p)")>;
451 def : InstRW<[A57Write_5cyc_1V], (instregex "^FADDP(v2f32|32|64|v2i32)")>;
456 def : InstRW<[A57Write_5cyc_1V], (instregex "^(FACGE|FACGT|FCMEQ|FCMGE|FCMGT|FCMLE|FCMLT)(v2f32|32|…
463 def : InstRW<[A57Write_5cyc_1V], (instregex "^[FSU]CVT([AMNPZ][SU])?(_Int)?(v2f32|v1i32|v2i32|v1i64…
483 def : InstRW<[A57Write_5cyc_1V], (instregex "^(FMAX|FMIN)(NM)?(v2f32)")>;
487 def : InstRW<[A57Write_5cyc_1V], (instregex "^(FMAX|FMIN)(NM)?P(v2f32|v2i32)")>;
494 def : InstRW<[A57Write_5cyc_1V_FP_Forward], (instregex "^FMULX?(v2f32|v1i32|v2i32|v1i64|32|64)")>;
508 def : InstRW<[A57WriteFPVMAD, A57ReadFPVMA5], (instregex "^FML[AS](v2f32|v1i32|v2i32|v1i64)")>;
512 def : InstRW<[A57Write_5cyc_1V], (instregex "^FRINT[AIMNPXZ](v2f32)")>;
[all …]
DAArch64TargetTransformInfo.cpp486 LT.second == MVT::v2f32 || LT.second == MVT::v4f32 || in getIntrinsicInstrCost()
1883 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, in getCastInstrCost()
1886 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, in getCastInstrCost()
1891 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 }, in getCastInstrCost()
1892 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 3 }, in getCastInstrCost()
1893 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 2 }, in getCastInstrCost()
1894 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 }, in getCastInstrCost()
1895 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i16, 3 }, in getCastInstrCost()
1896 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 2 }, in getCastInstrCost()
1927 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f32, 1 }, in getCastInstrCost()
[all …]
DAArch64SchedFalkorDetails.td586 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^(FABS|FNEG)v2f32$")>;
588 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^(F(MAX|MIN)(NM)?P?|FAC(GE|GT))(v2f32|v2i32p)$")>;
590 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^FCM(EQ|GE|GT)(32|64|v2f32|v2i32)$")>;
592 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^FRINT(A|I|M|N|P|X|Z)v2f32$")>;
595 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(FABD|FADD|FSUB)v2f32$")>;
596 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^FADDP(v2i32p|v2i64p|v2f32)$")>;
598 def : InstRW<[FalkorWr_1VXVY_4cyc], (instregex "^FCVT(N|M|P|Z|A)(S|U)(v1i32|v1i64|v2f32)$")>;
603 … (instregex "^(FMUL|FMULX)(v2f32|(v1i32_indexed|v2i32_indexed))$")>;
648 … (instregex "^FML(A|S)(v2f32|(v1i32_indexed|v2i32_indexed))$")>;
1159 def : InstRW<[FalkorWr_1VXVY_4cyc], (instregex "^(S|U)CVTF(v1i32|v2i32|v1i64|v2f32|d|s)(_shift)?"…
DAArch64SchedKryoDetails.td147 (instregex "(S|U)CVTF(v1i32|v2i32|v1i64|v2f32|d|s)(_shift)?")>;
621 (instregex "(F(MAX|MIN)(NM)?P?|FAC(GE|GT)|FCM(EQ|GE|GT))(v2f32|v2i32p)")>;
633 (instregex "FABD(32|64|v2f32)")>;
651 (instregex "F(ABS|NEG)v2f32")>;
675 (instregex "(FADD|FSUB|FADDP)v2f32")>;
735 (instregex "FCVT((A|N|M|P)(S|U)|Z(S|U)_Int)(v1i32|v1i64|v2f32)$")>;
747 (instregex "FCVTX?N(v2f32|v4f32|v2i32|v4i16|v4i32|v8i16)$")>;
771 (instregex "FCVTZ(S|U)(v2f32|v1i32|v1i64|v2i32(_shift)?)$")>;
969 (instregex "FRINT(A|I|M|N|P|X|Z)v2f32")>;
DAArch64InstrFormats.td5753 def v2f32 : BaseSIMDThreeSameVector<0, U, {S,0b01}, {0b11,opc}, V64,
5755 [(set (v2f32 V64:$Rd), (OpNode (v2f32 V64:$Rn), (v2f32 V64:$Rm)))]>;
5776 def v2f32 : BaseSIMDThreeSameVector<0, U, {S,0b01}, {0b11,opc}, V64,
5778 [(set (v2i32 V64:$Rd), (OpNode (v2f32 V64:$Rn), (v2f32 V64:$Rm)))]>;
5800 def v2f32 : BaseSIMDThreeSameVectorTied<0, U, {S,0b01}, {0b11,opc}, V64,
5802 [(set (v2f32 V64:$dst),
5803 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn), (v2f32 V64:$Rm)))]>;
5937 v2f32, v4f16, OpNode>;
6200 def v2f32 : BaseSIMDTwoSameVector<0, U, {S,0}, opc, 0b00, V64,
6202 [(set (v2f32 V64:$Rd), (OpNode (v2f32 V64:$Rn)))]>;
[all …]
DAArch64GenRegisterBankInfo.def257 // - v2f32 to v2f64
/openbsd/src/gnu/llvm/llvm/lib/Target/ARM/
DARMCallingConv.td33 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,
59 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,
74 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,
94 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,
111 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,
168 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,
186 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,
213 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,
236 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,
DARMInstrNEON.td1089 def : Pat<(vector_insert (v2f32 DPR:$src),
1102 def : Pat<(insert_subvector undef, (v2f32 DPR:$src), (i32 0)),
1390 def : Pat<(v2f32 (ARMvdup (f32 (load addrmode6dup:$addr)))),
2187 def : Pat<(store (extractelt (v2f32 DPR:$src), imm:$lane), addrmode6:$addr),
3330 def v2f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
3333 [(set DPR:$Vd, (v2i32 (ARMvcmpz (v2f32 DPR:$Vm), fc)))]> {
4255 v2f32, v2f32, fadd, 1>;
4318 v2f32, v2f32, fmul, 1>;
4328 def VMULslfd : N3VDSL<0b10, 0b1001, IIC_VBIND, "vmul", "f32", v2f32, fmul>;
4330 v2f32, fmul>;
[all …]
DARMTargetTransformInfo.cpp635 {ISD::FP_EXTEND, MVT::v2f32, 2}, in getCastInstrCost()
682 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 }, in getCastInstrCost()
683 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 }, in getCastInstrCost()
684 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 }, in getCastInstrCost()
685 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 }, in getCastInstrCost()
686 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, in getCastInstrCost()
687 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, in getCastInstrCost()
1220 {ISD::VECTOR_SHUFFLE, MVT::v2f32, 1}, in getShuffleCost()
1241 {ISD::VECTOR_SHUFFLE, MVT::v2f32, 1}, in getShuffleCost()
1263 {ISD::VECTOR_SHUFFLE, MVT::v2f32, 1}, in getShuffleCost()
DARMRegisterInfo.td446 def DPR : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32, v4f16, v4bf16], 64,
467 def DPR_VFP2 : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32, v4f16, v4bf16], 64,
474 def DPR_8 : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32, v4f16, v4bf16], 64,
/openbsd/src/gnu/llvm/llvm/include/llvm/Support/
DMachineValueType.h168 v2f32 = 106, // 2 x f32 enumerator
422 SimpleTy == MVT::v4bf16 ||SimpleTy == MVT::v2f32 || in is64BitVector()
680 case v2f32: in getVectorElementType()
869 case v2f32: in getVectorMinNumElements()
993 case v2f32: in getSizeInBits()
1378 if (NumElements == 2) return MVT::v2f32; in getVectorVT()
/openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/
DR600RegisterInfo.td251 def R600_Reg64 : RegisterClass<"AMDGPU", [v2f32, v2i32, i64, f64], 64,
254 def R600_Reg64Vertical : RegisterClass<"AMDGPU", [v2f32, v2i32], 64,
DSIInstructions.td1162 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index)
1167 defm : Insert_Element_V2 <SReg_64, f32, v2f32>;
1451 def : BitConvert <v2i32, v2f32, VReg_64>;
1452 def : BitConvert <v2f32, v2i32, VReg_64>;
1455 def : BitConvert <i64, v2f32, VReg_64>;
1456 def : BitConvert <v2f32, i64, VReg_64>;
1457 def : BitConvert <f64, v2f32, VReg_64>;
1458 def : BitConvert <v2f32, f64, VReg_64>;
1470 def : BitConvert <v2f32, v4f16, VReg_64>;
1471 def : BitConvert <v4f16, v2f32, VReg_64>;
[all …]
DSIInstrInfo.td320 !eq(SrcVT.Value, v2f32.Value),
346 !eq(SrcVT.Value, v2f32.Value),
1723 !if(!eq(VT.Value, v2f32.Value),
1775 !eq(SrcVT.Value, v2f32.Value),
2727 def VOP_V2F32_V2F32_V2F32_V2F32 : VOPProfile <[v2f32, v2f32, v2f32, v2f32]>;
2728 def VOP_V2F32_V2F32_V2F32 : VOPProfile <[v2f32, v2f32, v2f32, untyped]>;
2736 def VOP_V4F32_V2F32_V2F32_V4F32 : VOPProfile <[v4f32, v2f32, v2f32, v4f32]>;
2737 def VOP_V16F32_V2F32_V2F32_V16F32 : VOPProfile <[v16f32, v2f32, v2f32, v16f32]>;
DR600Instructions.td1693 def : ExtractVerticalPat <R600_EXTRACT_ELT_V2, v2f32, f32>;
1704 def : InsertVerticalPat <R600_INSERT_ELT_V2, v2f32, f32>;
1757 def : Extract_Element <f32, v2f32, 0, sub0>;
1758 def : Extract_Element <f32, v2f32, 1, sub1>;
1760 def : Insert_Element <f32, v2f32, 0, sub0>;
1761 def : Insert_Element <f32, v2f32, 1, sub1>;
1773 def : BitConvert <v2f32, v2i32, R600_Reg64>;
1774 def : BitConvert <v2i32, v2f32, R600_Reg64>;
DSIRegisterInfo.td813 def SGPR_64 : SIRegisterClass<"AMDGPU", [v2i32, i64, v2f32, f64, v4i16, v4f16], 32,
826 def SReg_64_XEXEC : SIRegisterClass<"AMDGPU", [v2i32, i64, v2f32, f64, i1, v4i16, v4f16], 32,
834 def SReg_64 : SIRegisterClass<"AMDGPU", [v2i32, i64, v2f32, f64, i1, v4i16, v4f16], 32,
938 defm VReg_64 : VRegClass<2, [i64, f64, v2i32, v2f32, v4f16, v4i16, p0, p1, p4],
972 defm AReg_64 : ARegClass<2, [i64, f64, v2i32, v2f32, v4f16, v4i16],
1016 def VS_64 : SIRegisterClass<"AMDGPU", [i64, f64, v2f32], 32, (add VReg_64, SReg_64)> {
DAMDGPUISelLowering.cpp66 setOperationAction(ISD::LOAD, MVT::v2f32, Promote); in AMDGPUTargetLowering()
67 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32); in AMDGPUTargetLowering()
167 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, MVT::v2f16, Expand); in AMDGPUTargetLowering()
175 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f32, Expand); in AMDGPUTargetLowering()
192 setOperationAction(ISD::STORE, MVT::v2f32, Promote); in AMDGPUTargetLowering()
193 AddPromotedToType(ISD::STORE, MVT::v2f32, MVT::v2i32); in AMDGPUTargetLowering()
279 setTruncStoreAction(MVT::v2f32, MVT::v2f16, Expand); in AMDGPUTargetLowering()
290 setTruncStoreAction(MVT::v2f64, MVT::v2f32, Expand); in AMDGPUTargetLowering()
349 {MVT::v2f16, MVT::v3f16, MVT::v4f16, MVT::v16f16, MVT::v2f32, MVT::v3f32, in AMDGPUTargetLowering()
366 {MVT::v2f16, MVT::v2i16, MVT::v4f16, MVT::v4i16, MVT::v2f32, in AMDGPUTargetLowering()
[all …]
DBUFInstructions.td791 "buffer_load_format_xy", v2f32
803 "buffer_store_format_xy", v2f32
1048 "buffer_atomic_fcmpswap", VReg_64, v2f32, null_frag
1266 defm : MUBUF_LoadIntrinsicPat<SIbuffer_load_format, v2f32, "BUFFER_LOAD_FORMAT_XY">;
1303 defm : MUBUF_LoadIntrinsicPat<SIbuffer_load, v2f32, "BUFFER_LOAD_DWORDX2">;
1354 defm : MUBUF_StoreIntrinsicPat<SIbuffer_store_format, v2f32, "BUFFER_STORE_FORMAT_XY">;
1386 defm : MUBUF_StoreIntrinsicPat<SIbuffer_store, v2f32, "BUFFER_STORE_DWORDX2">;
1948 defm : MTBUF_LoadIntrinsicPat<SItbuffer_load, v2f32, "TBUFFER_LOAD_FORMAT_XY">;
2012 defm : MTBUF_StoreIntrinsicPat<SItbuffer_store, v2f32, "TBUFFER_STORE_FORMAT_XY">;
/openbsd/src/gnu/llvm/llvm/lib/Target/RISCV/
DRISCVTargetTransformInfo.cpp371 {Intrinsic::floor, MVT::v2f32, 9},
388 {Intrinsic::ceil, MVT::v2f32, 9},
405 {Intrinsic::trunc, MVT::v2f32, 7},
422 {Intrinsic::round, MVT::v2f32, 9},
439 {Intrinsic::roundeven, MVT::v2f32, 9},
/openbsd/src/gnu/llvm/llvm/lib/Target/SystemZ/
DSystemZRegisterInfo.td151 [i64, f64, v8i8, v4i16, v2i32, v2f32], 64,
275 defm VR64 : SystemZRegClass<"VR64", [f64, v8i8, v4i16, v2i32, v2f32], 64,
/openbsd/src/gnu/llvm/llvm/include/llvm/IR/
DIntrinsicsAMDGPU.td1178 [llvm_any_ty], // overloaded for types f32/i32, v2f32/v2i32, v4f32/v4i32
1195 [llvm_any_ty, // vdata(VGPR), overloaded for types f32/i32, v2f32/v2i32, v4f32/v4i32
1215 [llvm_any_ty], // overloaded for types f32/i32, v2f32/v2i32, v4f32/v4i32
1230 [llvm_any_ty, // vdata(VGPR), overloaded for types f32/i32, v2f32/v2i32, v4f32/v4i32
1244 [llvm_any_ty], // overloaded for types f32/i32, v2f32/v2i32, v4f32/v4i32
1260 [llvm_any_ty, // vdata(VGPR), overloaded for types f32/i32, v2f32/v2i32, v4f32/v4i32

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