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Searched refs:v16f32 (Results 1 – 25 of 25) sorted by relevance

/openbsd/src/gnu/llvm/llvm/lib/Target/X86/
DX86CallingConv.td127 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
157 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
202 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
255 CCIfType<[v64i8, v32i16, v16i32, v8i64, v32f16, v16f32, v8f64],
314 CCIfType<[v16f32, v8f64, v16i32, v8i64],
582 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v32f16, v16f32, v8f64],
602 CCIfType<[v64i8, v32i16, v16i32, v8i64, v32f16, v16f32, v8f64],
656 CCIfType<[v64i8, v32i16, v16i32, v32f16, v16f32, v8f64, v8i64], CCPassIndirect<i64>>,
721 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
780 CCIfType<[v64i8, v32i16, v16i32, v8i64, v32f16, v16f32, v8f64],
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DX86InstrVecCompiler.td92 defm : subvector_subreg_lowering<VR128, v4f32, VR512, v16f32, sub_xmm>;
104 defm : subvector_subreg_lowering<VR256, v8f32, VR512, v16f32, sub_ymm>;
142 defm : subvec_zero_lowering<"APSZ128", VR128X, v16f32, v4f32, sub_xmm>;
149 defm : subvec_zero_lowering<"APSZ256", VR256X, v16f32, v8f32, sub_ymm>;
158 defm : subvec_zero_lowering<"APS", VR128, v16f32, v4f32, sub_xmm>;
165 defm : subvec_zero_lowering<"APSY", VR256, v16f32, v8f32, sub_ymm>;
DX86TargetTransformInfo.cpp909 { ISD::FNEG, MVT::v16f32, { 1, 1, 1, 2 } }, // Skylake from http://www.agner.org/ in getArithmeticInstrCost()
910 { ISD::FADD, MVT::v16f32, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/ in getArithmeticInstrCost()
912 { ISD::FSUB, MVT::v16f32, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/ in getArithmeticInstrCost()
914 { ISD::FMUL, MVT::v16f32, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/ in getArithmeticInstrCost()
922 { ISD::FDIV, MVT::v16f32, { 10, 18, 1, 3 } }, // Skylake from http://www.agner.org/ in getArithmeticInstrCost()
1712 {TTI::SK_Broadcast, MVT::v16f32, { 1, 1, 1, 1 } }, // vbroadcastss in getShuffleCost()
1720 {TTI::SK_Reverse, MVT::v16f32, { 1, 3, 1, 1 } }, // vpermps in getShuffleCost()
1729 {TTI::SK_Splice, MVT::v16f32, { 1, 1, 1, 1 } }, // vpalignd in getShuffleCost()
1742 {TTI::SK_PermuteSingleSrc, MVT::v16f32, { 1, 3, 1, 1 } }, // vpermps in getShuffleCost()
1754 {TTI::SK_PermuteTwoSrc, MVT::v16f32, { 1, 3, 1, 1 } }, // vpermt2ps in getShuffleCost()
[all …]
DX86InstrFragmentsSIMD.td850 def loadv16f32 : PatFrag<(ops node:$ptr), (v16f32 (load node:$ptr))>;
923 (v16f32 (alignedload node:$ptr))>;
978 def bc_v16f32 : PatFrag<(ops node:$in), (v16f32 (bitconvert node:$in))>;
DX86RegisterInfo.td589 def VR512 : RegisterClass<"X86", [v16f32, v8f64, v32f16, v32bf16, v64i8, v32i16, v16i32, v8i64],
593 def VR512_0_15 : RegisterClass<"X86", [v16f32, v8f64, v64i8, v32i16, v16i32, v8i64],
DX86ISelLowering.cpp896 MVT::v4f32, MVT::v8f32, MVT::v16f32, in X86TargetLowering()
1575 setOperationPromotedToType(Opc, MVT::v16f16, MVT::v16f32); in X86TargetLowering()
1658 addRegisterClass(MVT::v16f32, &X86::VR512RegClass); in X86TargetLowering()
1675 for (MVT VT : { MVT::v16f32, MVT::v8f64 }) { in X86TargetLowering()
1700 setOperationAction(ISD::STRICT_FADD, MVT::v16f32, Legal); in X86TargetLowering()
1702 setOperationAction(ISD::STRICT_FSUB, MVT::v16f32, Legal); in X86TargetLowering()
1704 setOperationAction(ISD::STRICT_FMUL, MVT::v16f32, Legal); in X86TargetLowering()
1706 setOperationAction(ISD::STRICT_FDIV, MVT::v16f32, Legal); in X86TargetLowering()
1708 setOperationAction(ISD::STRICT_FSQRT, MVT::v16f32, Legal); in X86TargetLowering()
1752 for (auto VT : { MVT::v16f32, MVT::v8f64 }) { in X86TargetLowering()
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DX86InstrAVX512.td490 def : Pat<(v16f32 immAllZerosV), (AVX512_512_SET0)>;
1018 def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 4))),
1020 (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm)),
1051 def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 4))),
1053 (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm)),
1532 def : Pat<(v16f32 (X86SubVBroadcastld256 addr:$src)),
1547 def : Pat<(v16f32 (X86SubVBroadcastld128 addr:$src)),
1563 (v16f32 immAllZerosV)),
1579 (bc_v8f64 (v16f32 (X86SubVBroadcastld256 addr:$src))),
1583 (bc_v8f64 (v16f32 (X86SubVBroadcastld256 addr:$src))),
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DX86FastISel.cpp436 case MVT::v16f32: in X86FastEmitLoad()
607 case MVT::v16f32: in X86FastEmitStore()
DX86InstrCompiler.td684 def : Pat<(v16f32 (X86cmov VR512:$t, VR512:$f, timm:$cond, EFLAGS)),
/openbsd/src/gnu/llvm/llvm/include/llvm/Support/
DMachineValueType.h179 v16f32 = 117, // 16 x f32 enumerator
448 SimpleTy == MVT::v16f32 || SimpleTy == MVT::v8f64 || in is512BitVector()
691 case v16f32: in getVectorElementType()
795 case v16f32: in getVectorMinNumElements()
1073 case v16f32: in getSizeInBits()
1389 if (NumElements == 16) return MVT::v16f32; in getVectorVT()
/openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/
DSIInstrInfo.td2712 def VOP_V16F32_F32_F32_V16F32 : VOPProfile <[v16f32, f32, f32, v16f32]>;
2715 def VOP_V16F32_V4F16_V4F16_V16F32 : VOPProfile <[v16f32, v4f16, v4f16, v16f32]>;
2718 def VOP_V16F32_V2I16_V2I16_V16F32 : VOPProfile <[v16f32, v2i16, v2i16, v16f32]>;
2731 def VOP_V16F32_V4I16_V4I16_V16F32 : VOPProfile <[v16f32, v4i16, v4i16, v16f32]>;
2737 def VOP_V16F32_V2F32_V2F32_V16F32 : VOPProfile <[v16f32, v2f32, v2f32, v16f32]>;
2739 def VOP_V16F32_I64_I64_V16F32 : VOPProfile <[v16f32, i64, i64, v16f32]>;
2742 def VOP_V16F32_V4F16_V8F16_I32 : VOPProfile <[v16f32, v4f16, v8f16, i32]>;
2744 def VOP_V16F32_V4I16_V8I16_I32 : VOPProfile <[v16f32, v4i16, v8i16, i32]>;
2748 def VOP_V16F32_V2I32_V4I32_I32 : VOPProfile <[v16f32, v2i32, v4i32, i32]>;
DSIInstructions.td1338 f32, v16f32, Index, !cast<SubRegIndex>(sub#Index)
1341 f32, v16f32, Index, !cast<SubRegIndex>(sub#Index)
1611 def : BitConvert <v16i32, v16f32, VReg_512>;
1612 def : BitConvert <v16f32, v16i32, VReg_512>;
1619 def : BitConvert <v8i64, v16f32, VReg_512>;
1620 def : BitConvert <v8f64, v16f32, VReg_512>;
1621 def : BitConvert <v16f32, v8i64, VReg_512>;
1622 def : BitConvert <v16f32, v8f64, VReg_512>;
2154 defm : SI_INDIRECT_Pattern <v16f32, f32, "V16">;
DAMDGPUISelLowering.cpp99 setOperationAction(ISD::LOAD, MVT::v16f32, Promote); in AMDGPUTargetLowering()
100 AddPromotedToType(ISD::LOAD, MVT::v16f32, MVT::v16i32); in AMDGPUTargetLowering()
171 setLoadExtAction(ISD::EXTLOAD, MVT::v16f32, MVT::v16f16, Expand); in AMDGPUTargetLowering()
179 setLoadExtAction(ISD::EXTLOAD, MVT::v16f64, MVT::v16f32, Expand); in AMDGPUTargetLowering()
225 setOperationAction(ISD::STORE, MVT::v16f32, Promote); in AMDGPUTargetLowering()
226 AddPromotedToType(ISD::STORE, MVT::v16f32, MVT::v16i32); in AMDGPUTargetLowering()
283 setTruncStoreAction(MVT::v16f32, MVT::v16f16, Expand); in AMDGPUTargetLowering()
306 setTruncStoreAction(MVT::v16f64, MVT::v16f32, Expand); in AMDGPUTargetLowering()
350 MVT::v4f32, MVT::v5f32, MVT::v6f32, MVT::v7f32, MVT::v8f32, MVT::v16f32, in AMDGPUTargetLowering()
371 MVT::v12f32, MVT::v16f16, MVT::v16i16, MVT::v16f32, MVT::v16i32, in AMDGPUTargetLowering()
DSIRegisterInfo.td900 defm "" : SRegClass<16, [v16i32, v16f32, v8i64, v8f64], SGPR_512Regs, TTMP_512Regs>;
953 defm VReg_512 : VRegClass<16, [v16i32, v16f32, v8i64, v8f64], (add VGPR_512)>;
986 defm AReg_512 : ARegClass<16, [v16i32, v16f32, v8i64, v8f64], (add AGPR_512)>;
DSIISelLowering.cpp136 addRegisterClass(MVT::v16f32, TRI->getVGPRClassForBitWidth(512)); in SITargetLowering()
233 MVT::v10f32, MVT::v11f32, MVT::v12f32, MVT::v16f32}, in SITargetLowering()
261 MVT::v16i32, MVT::v16f32, MVT::v2i64, MVT::v2f64, MVT::v4i16, in SITargetLowering()
368 {MVT::v8i32, MVT::v8f32, MVT::v16i32, MVT::v16f32}, in SITargetLowering()
700 {MVT::v4f32, MVT::v8f32, MVT::v16f32, MVT::v32f32}, in SITargetLowering()
4638 VT == MVT::v16f16 || VT == MVT::v8f32 || VT == MVT::v16f32 || in splitBinaryVectorOp()
4662 VT == MVT::v16f16 || VT == MVT::v8f32 || VT == MVT::v16f32 || in splitTernaryVectorOp()
6224 Type = MVT::v16f32; in getBuildDwordsVector()
DSMInstructions.td942 defm : SMLoad_Pattern <"S_BUFFER_LOAD_DWORDX16", v16f32>;
/openbsd/src/gnu/llvm/llvm/lib/Target/RISCV/
DRISCVTargetTransformInfo.cpp374 {Intrinsic::floor, MVT::v16f32, 9},
391 {Intrinsic::ceil, MVT::v16f32, 9},
408 {Intrinsic::trunc, MVT::v16f32, 7},
425 {Intrinsic::round, MVT::v16f32, 9},
442 {Intrinsic::roundeven, MVT::v16f32, 9},
/openbsd/src/gnu/llvm/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp698 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 }, in getCastInstrCost()
699 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 }, in getCastInstrCost()
700 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 4 }, in getCastInstrCost()
701 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 4 }, in getCastInstrCost()
725 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f32, 8 }, in getCastInstrCost()
726 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 8 } in getCastInstrCost()
/openbsd/src/gnu/llvm/llvm/lib/Target/Hexagon/
DHexagonRegisterInfo.td485 [v16f32, v32f32, v16f32]>;
/openbsd/src/gnu/llvm/llvm/include/llvm/CodeGen/
DValueTypes.td149 def v16f32 : ValueType<512, 117>; // 16 x f32 vector value
/openbsd/src/gnu/llvm/llvm/lib/CodeGen/
DValueTypes.cpp413 case MVT::v16f32: in getTypeForEVT()
/openbsd/src/gnu/llvm/llvm/utils/TableGen/
DCodeGenTarget.cpp183 case MVT::v16f32: return "MVT::v16f32"; in getEnumName()
/openbsd/src/gnu/llvm/llvm/docs/
DLangRef.rst19295 …declare <16 x float> @llvm.vp.copysign.v16f32 (<16 x float> <mag_op>, <16 x float> <sign_op>, <16…
19344 …declare <16 x float> @llvm.vp.minnum.v16f32 (<16 x float> <left_op>, <16 x float> <right_op>, <16…
19393 …declare <16 x float> @llvm.vp.maxnum.v16f32 (<16 x float> <left_op>, <16 x float> <right_op>, <16…
19442 …declare <16 x float> @llvm.vp.fadd.v16f32 (<16 x float> <left_op>, <16 x float> <right_op>, <16 x…
19491 …declare <16 x float> @llvm.vp.fsub.v16f32 (<16 x float> <left_op>, <16 x float> <right_op>, <16 x…
19540 …declare <16 x float> @llvm.vp.fmul.v16f32 (<16 x float> <left_op>, <16 x float> <right_op>, <16 x…
19589 …declare <16 x float> @llvm.vp.fdiv.v16f32 (<16 x float> <left_op>, <16 x float> <right_op>, <16 x…
19638 …declare <16 x float> @llvm.vp.frem.v16f32 (<16 x float> <left_op>, <16 x float> <right_op>, <16 x…
19687 …declare <16 x float> @llvm.vp.fneg.v16f32 (<16 x float> <op>, <16 x i1> <mask>, i32 <vector_lengt…
19735 …declare <16 x float> @llvm.vp.fabs.v16f32 (<16 x float> <op>, <16 x i1> <mask>, i32 <vector_lengt…
[all …]
/openbsd/src/gnu/llvm/llvm/lib/Target/AArch64/
DAArch64TargetTransformInfo.cpp1911 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 21 }, in getCastInstrCost()
1912 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i8, 21 }, in getCastInstrCost()
/openbsd/src/gnu/llvm/llvm/include/llvm/IR/
DIntrinsics.td338 def llvm_v16f32_ty : LLVMType<v16f32>; // 16 x float