| /openbsd/src/sys/dev/pci/drm/amd/amdgpu/ |
| D | mmhub_v3_0_2.c | 163 uint32_t tmp; in mmhub_v3_0_2_init_system_aperture_regs() local
196 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2); in mmhub_v3_0_2_init_system_aperture_regs()
197 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2, in mmhub_v3_0_2_init_system_aperture_regs()
199 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2, tmp); in mmhub_v3_0_2_init_system_aperture_regs()
204 uint32_t tmp; in mmhub_v3_0_2_init_tlb_regs() local
207 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v3_0_2_init_tlb_regs()
209 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v3_0_2_init_tlb_regs()
210 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in mmhub_v3_0_2_init_tlb_regs()
211 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, in mmhub_v3_0_2_init_tlb_regs()
213 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, in mmhub_v3_0_2_init_tlb_regs()
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| D | mmhub_v3_3.c | 168 uint32_t tmp; in mmhub_v3_3_init_system_aperture_regs() local
199 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2); in mmhub_v3_3_init_system_aperture_regs()
200 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2, in mmhub_v3_3_init_system_aperture_regs()
202 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2, tmp); in mmhub_v3_3_init_system_aperture_regs()
207 uint32_t tmp; in mmhub_v3_3_init_tlb_regs() local
210 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v3_3_init_tlb_regs()
212 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v3_3_init_tlb_regs()
213 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in mmhub_v3_3_init_tlb_regs()
214 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, in mmhub_v3_3_init_tlb_regs()
216 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, in mmhub_v3_3_init_tlb_regs()
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| D | gfxhub_v3_0_3.c | 191 uint32_t tmp; in gfxhub_v3_0_3_init_tlb_regs() local
194 tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL); in gfxhub_v3_0_3_init_tlb_regs()
196 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v3_0_3_init_tlb_regs()
197 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in gfxhub_v3_0_3_init_tlb_regs()
198 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v3_0_3_init_tlb_regs()
200 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v3_0_3_init_tlb_regs()
202 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); in gfxhub_v3_0_3_init_tlb_regs()
203 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v3_0_3_init_tlb_regs()
206 WREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, tmp); in gfxhub_v3_0_3_init_tlb_regs()
211 uint32_t tmp; in gfxhub_v3_0_3_init_cache_regs() local
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| D | gfxhub_v1_0.c | 156 uint32_t tmp; in gfxhub_v1_0_init_tlb_regs() local
159 tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL); in gfxhub_v1_0_init_tlb_regs()
161 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v1_0_init_tlb_regs()
162 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in gfxhub_v1_0_init_tlb_regs()
163 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in gfxhub_v1_0_init_tlb_regs()
165 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in gfxhub_v1_0_init_tlb_regs()
167 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in gfxhub_v1_0_init_tlb_regs()
169 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1); in gfxhub_v1_0_init_tlb_regs()
171 WREG32_SOC15_RLC(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp); in gfxhub_v1_0_init_tlb_regs()
176 uint32_t tmp; in gfxhub_v1_0_init_cache_regs() local
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| D | gfxhub_v2_0.c | 188 uint32_t tmp; in gfxhub_v2_0_init_tlb_regs() local
191 tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL); in gfxhub_v2_0_init_tlb_regs()
193 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v2_0_init_tlb_regs()
194 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in gfxhub_v2_0_init_tlb_regs()
195 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v2_0_init_tlb_regs()
197 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v2_0_init_tlb_regs()
199 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v2_0_init_tlb_regs()
202 WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp); in gfxhub_v2_0_init_tlb_regs()
207 uint32_t tmp; in gfxhub_v2_0_init_cache_regs() local
214 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL); in gfxhub_v2_0_init_cache_regs()
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| D | gfxhub_v12_0.c | 194 uint32_t tmp; in gfxhub_v12_0_init_tlb_regs() local
197 tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL); in gfxhub_v12_0_init_tlb_regs()
199 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v12_0_init_tlb_regs()
200 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in gfxhub_v12_0_init_tlb_regs()
201 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v12_0_init_tlb_regs()
203 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v12_0_init_tlb_regs()
205 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); in gfxhub_v12_0_init_tlb_regs()
206 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v12_0_init_tlb_regs()
209 WREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, tmp); in gfxhub_v12_0_init_tlb_regs()
214 uint32_t tmp; in gfxhub_v12_0_init_cache_regs() local
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| D | gfxhub_v11_5_0.c | 189 uint32_t tmp; in gfxhub_v11_5_0_init_tlb_regs() local
192 tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL); in gfxhub_v11_5_0_init_tlb_regs()
194 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v11_5_0_init_tlb_regs()
195 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in gfxhub_v11_5_0_init_tlb_regs()
196 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v11_5_0_init_tlb_regs()
198 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v11_5_0_init_tlb_regs()
200 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); in gfxhub_v11_5_0_init_tlb_regs()
201 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v11_5_0_init_tlb_regs()
204 WREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, tmp); in gfxhub_v11_5_0_init_tlb_regs()
209 uint32_t tmp; in gfxhub_v11_5_0_init_cache_regs() local
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| D | gfxhub_v3_0.c | 186 uint32_t tmp; in gfxhub_v3_0_init_tlb_regs() local
189 tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL); in gfxhub_v3_0_init_tlb_regs()
191 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v3_0_init_tlb_regs()
192 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in gfxhub_v3_0_init_tlb_regs()
193 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v3_0_init_tlb_regs()
195 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v3_0_init_tlb_regs()
197 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); in gfxhub_v3_0_init_tlb_regs()
198 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v3_0_init_tlb_regs()
201 WREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, tmp); in gfxhub_v3_0_init_tlb_regs()
206 uint32_t tmp; in gfxhub_v3_0_init_cache_regs() local
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| D | mmhub_v3_0_1.c | 172 uint32_t tmp; in mmhub_v3_0_1_init_system_aperture_regs() local
203 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2); in mmhub_v3_0_1_init_system_aperture_regs()
204 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2, in mmhub_v3_0_1_init_system_aperture_regs()
206 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2, tmp); in mmhub_v3_0_1_init_system_aperture_regs()
211 uint32_t tmp; in mmhub_v3_0_1_init_tlb_regs() local
214 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v3_0_1_init_tlb_regs()
216 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v3_0_1_init_tlb_regs()
217 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in mmhub_v3_0_1_init_tlb_regs()
218 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, in mmhub_v3_0_1_init_tlb_regs()
220 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, in mmhub_v3_0_1_init_tlb_regs()
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| D | mmhub_v3_0.c | 170 uint32_t tmp; in mmhub_v3_0_init_system_aperture_regs() local
204 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2); in mmhub_v3_0_init_system_aperture_regs()
205 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2, in mmhub_v3_0_init_system_aperture_regs()
207 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2, tmp); in mmhub_v3_0_init_system_aperture_regs()
212 uint32_t tmp; in mmhub_v3_0_init_tlb_regs() local
215 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v3_0_init_tlb_regs()
217 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v3_0_init_tlb_regs()
218 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in mmhub_v3_0_init_tlb_regs()
219 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, in mmhub_v3_0_init_tlb_regs()
221 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, in mmhub_v3_0_init_tlb_regs()
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| D | mmhub_v4_1_0.c | 170 uint32_t tmp; in mmhub_v4_1_0_init_system_aperture_regs() local
205 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2); in mmhub_v4_1_0_init_system_aperture_regs()
206 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2, in mmhub_v4_1_0_init_system_aperture_regs()
208 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2, tmp); in mmhub_v4_1_0_init_system_aperture_regs()
213 uint32_t tmp; in mmhub_v4_1_0_init_tlb_regs() local
216 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v4_1_0_init_tlb_regs()
218 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v4_1_0_init_tlb_regs()
219 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in mmhub_v4_1_0_init_tlb_regs()
220 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, in mmhub_v4_1_0_init_tlb_regs()
222 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, in mmhub_v4_1_0_init_tlb_regs()
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| D | mmhub_v2_0.c | 221 uint32_t tmp; in mmhub_v2_0_init_system_aperture_regs() local
249 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2); in mmhub_v2_0_init_system_aperture_regs()
250 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2, in mmhub_v2_0_init_system_aperture_regs()
252 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2, tmp); in mmhub_v2_0_init_system_aperture_regs()
257 uint32_t tmp; in mmhub_v2_0_init_tlb_regs() local
260 tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v2_0_init_tlb_regs()
262 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v2_0_init_tlb_regs()
263 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in mmhub_v2_0_init_tlb_regs()
264 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, in mmhub_v2_0_init_tlb_regs()
266 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, in mmhub_v2_0_init_tlb_regs()
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| D | mmhub_v2_3.c | 153 uint32_t tmp; in mmhub_v2_3_init_system_aperture_regs() local
179 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2); in mmhub_v2_3_init_system_aperture_regs()
180 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2, in mmhub_v2_3_init_system_aperture_regs()
182 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2, tmp); in mmhub_v2_3_init_system_aperture_regs()
187 uint32_t tmp; in mmhub_v2_3_init_tlb_regs() local
190 tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v2_3_init_tlb_regs()
192 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v2_3_init_tlb_regs()
193 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in mmhub_v2_3_init_tlb_regs()
194 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, in mmhub_v2_3_init_tlb_regs()
196 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, in mmhub_v2_3_init_tlb_regs()
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| D | lsdma_v7_0.c | 45 uint32_t tmp; in lsdma_v7_0_copy_mem() local
55 tmp = RREG32_SOC15(LSDMA, 0, regLSDMA_PIO_COMMAND); in lsdma_v7_0_copy_mem()
56 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, BYTE_COUNT, size); in lsdma_v7_0_copy_mem()
57 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, SRC_LOCATION, 0); in lsdma_v7_0_copy_mem()
58 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, DST_LOCATION, 0); in lsdma_v7_0_copy_mem()
59 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, SRC_ADDR_INC, 0); in lsdma_v7_0_copy_mem()
60 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, DST_ADDR_INC, 0); in lsdma_v7_0_copy_mem()
61 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, OVERLAP_DISABLE, 0); in lsdma_v7_0_copy_mem()
62 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, CONSTANT_FILL, 0); in lsdma_v7_0_copy_mem()
63 WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_COMMAND, tmp); in lsdma_v7_0_copy_mem()
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| D | lsdma_v6_0.c | 45 uint32_t tmp; in lsdma_v6_0_copy_mem() local
55 tmp = RREG32_SOC15(LSDMA, 0, regLSDMA_PIO_COMMAND); in lsdma_v6_0_copy_mem()
56 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, BYTE_COUNT, size); in lsdma_v6_0_copy_mem()
57 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, SRC_LOCATION, 0); in lsdma_v6_0_copy_mem()
58 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, DST_LOCATION, 0); in lsdma_v6_0_copy_mem()
59 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, SRC_ADDR_INC, 0); in lsdma_v6_0_copy_mem()
60 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, DST_ADDR_INC, 0); in lsdma_v6_0_copy_mem()
61 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, OVERLAP_DISABLE, 0); in lsdma_v6_0_copy_mem()
62 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, CONSTANT_FILL, 0); in lsdma_v6_0_copy_mem()
63 WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_COMMAND, tmp); in lsdma_v6_0_copy_mem()
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| D | mmhub_v1_8.c | 130 uint32_t tmp, inst_mask; in mmhub_v1_8_init_system_aperture_regs() local
184 tmp = RREG32_SOC15(MMHUB, i, regVM_L2_PROTECTION_FAULT_CNTL2); in mmhub_v1_8_init_system_aperture_regs()
185 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2, in mmhub_v1_8_init_system_aperture_regs()
187 WREG32_SOC15(MMHUB, i, regVM_L2_PROTECTION_FAULT_CNTL2, tmp); in mmhub_v1_8_init_system_aperture_regs()
193 uint32_t tmp, inst_mask; in mmhub_v1_8_init_tlb_regs() local
199 tmp = RREG32_SOC15(MMHUB, i, regMC_VM_MX_L1_TLB_CNTL); in mmhub_v1_8_init_tlb_regs()
201 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, in mmhub_v1_8_init_tlb_regs()
203 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in mmhub_v1_8_init_tlb_regs()
205 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in mmhub_v1_8_init_tlb_regs()
207 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in mmhub_v1_8_init_tlb_regs()
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| D | gfxhub_v1_2.c | 128 uint32_t tmp; in gfxhub_v1_2_xcc_init_system_aperture_regs() local
174 tmp = RREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_CNTL2); in gfxhub_v1_2_xcc_init_system_aperture_regs()
175 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2, in gfxhub_v1_2_xcc_init_system_aperture_regs()
177 WREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_CNTL2, tmp); in gfxhub_v1_2_xcc_init_system_aperture_regs()
197 uint32_t tmp; in gfxhub_v1_2_xcc_init_tlb_regs() local
202 tmp = RREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_MX_L1_TLB_CNTL); in gfxhub_v1_2_xcc_init_tlb_regs()
204 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in gfxhub_v1_2_xcc_init_tlb_regs()
206 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in gfxhub_v1_2_xcc_init_tlb_regs()
208 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in gfxhub_v1_2_xcc_init_tlb_regs()
210 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in gfxhub_v1_2_xcc_init_tlb_regs()
[all …]
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| D | mmhub_v1_0.c | 88 uint32_t tmp; in mmhub_v1_0_init_system_aperture_regs() local
131 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2); in mmhub_v1_0_init_system_aperture_regs()
132 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2, in mmhub_v1_0_init_system_aperture_regs()
134 WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2, tmp); in mmhub_v1_0_init_system_aperture_regs()
139 uint32_t tmp; in mmhub_v1_0_init_tlb_regs() local
142 tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL); in mmhub_v1_0_init_tlb_regs()
144 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v1_0_init_tlb_regs()
145 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in mmhub_v1_0_init_tlb_regs()
146 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in mmhub_v1_0_init_tlb_regs()
148 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in mmhub_v1_0_init_tlb_regs()
[all …]
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| /openbsd/src/gnu/usr.bin/gcc/gcc/testsuite/lib/ |
| D | old-dejagnu.exp | 51 set tmp [grep $prog "$option.*" line]
52 if ![string match "" $tmp] then {
53 foreach i $tmp {
198 set tmp [grep $prog "FIXME -.*"]
199 if ![string match "" $tmp] then {
200 foreach i $tmp {
206 set tmp [lindex [grep $prog "Special.*Options:.*"] 0]
210 regsub -all "\n\[^\n\]+(\n|$)" $tmp "\n" tmp
211 set tmp [string trim $tmp]
212 if ![string match "" $tmp] then {
[all …]
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| /openbsd/src/sys/dev/pci/drm/radeon/ |
| D | vce_v2_0.c | 41 u32 tmp; in vce_v2_0_set_sw_cg() local
44 tmp = RREG32(VCE_CLOCK_GATING_B); in vce_v2_0_set_sw_cg()
45 tmp |= 0xe70000; in vce_v2_0_set_sw_cg()
46 WREG32(VCE_CLOCK_GATING_B, tmp); in vce_v2_0_set_sw_cg()
48 tmp = RREG32(VCE_UENC_CLOCK_GATING); in vce_v2_0_set_sw_cg()
49 tmp |= 0xff000000; in vce_v2_0_set_sw_cg()
50 WREG32(VCE_UENC_CLOCK_GATING, tmp); in vce_v2_0_set_sw_cg()
52 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); in vce_v2_0_set_sw_cg()
53 tmp &= ~0x3fc; in vce_v2_0_set_sw_cg()
54 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp); in vce_v2_0_set_sw_cg()
[all …]
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| D | radeon_clocks.c | 284 u32 tmp = RREG32_PLL(RADEON_PPLL_REF_DIV); in radeon_get_clock_info() local
287 (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> R300_PPLL_REF_DIV_ACC_SHIFT; in radeon_get_clock_info()
289 p1pll->reference_div = tmp & RADEON_PPLL_REF_DIV_MASK; in radeon_get_clock_info()
477 uint32_t tmp; in radeon_legacy_set_engine_clock() local
484 tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL); in radeon_legacy_set_engine_clock()
485 tmp &= ~RADEON_DONT_USE_XTALIN; in radeon_legacy_set_engine_clock()
486 WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp); in radeon_legacy_set_engine_clock()
488 tmp = RREG32_PLL(RADEON_SCLK_CNTL); in radeon_legacy_set_engine_clock()
489 tmp &= ~RADEON_SCLK_SRC_SEL_MASK; in radeon_legacy_set_engine_clock()
490 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_engine_clock()
[all …]
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| D | rs400.c | 67 uint32_t tmp; in rs400_gart_tlb_flush() local
72 tmp = RREG32_MC(RS480_GART_CACHE_CNTRL); in rs400_gart_tlb_flush()
73 if ((tmp & RS480_GART_CACHE_INVALIDATE) == 0) in rs400_gart_tlb_flush()
114 uint32_t tmp; in rs400_gart_enable() local
116 tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH); in rs400_gart_enable()
117 tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS; in rs400_gart_enable()
118 WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp); in rs400_gart_enable()
153 tmp = REG_SET(RS690_MC_AGP_TOP, rdev->mc.gtt_end >> 16); in rs400_gart_enable()
154 tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_start >> 16); in rs400_gart_enable()
156 WREG32_MC(RS690_MCCFG_AGP_LOCATION, tmp); in rs400_gart_enable()
[all …]
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| /openbsd/src/gnu/usr.bin/binutils/opcodes/ |
| D | cgen.sh | 85 rm -f tmp-desc.h tmp-desc.h1
86 rm -f tmp-desc.c tmp-desc.c1
87 rm -f tmp-opc.h tmp-opc.h1
88 rm -f tmp-opc.c tmp-opc.c1
89 rm -f tmp-opinst.c tmp-opinst.c1
90 rm -f tmp-ibld.h tmp-ibld.h1
91 rm -f tmp-ibld.c tmp-ibld.in1
92 rm -f tmp-asm.c tmp-asm.in1
93 rm -f tmp-dis.c tmp-dis.in1
103 -H tmp-desc.h1 \
[all …]
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| /openbsd/src/gnu/usr.bin/binutils-2.17/opcodes/ |
| D | cgen.sh | 85 rm -f tmp-desc.h tmp-desc.h1
86 rm -f tmp-desc.c tmp-desc.c1
87 rm -f tmp-opc.h tmp-opc.h1
88 rm -f tmp-opc.c tmp-opc.c1
89 rm -f tmp-opinst.c tmp-opinst.c1
90 rm -f tmp-ibld.h tmp-ibld.h1
91 rm -f tmp-ibld.c tmp-ibld.in1
92 rm -f tmp-asm.c tmp-asm.in1
93 rm -f tmp-dis.c tmp-dis.in1
103 -H tmp-desc.h1 \
[all …]
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| /openbsd/src/sys/kern/ |
| D | subr_tree.c | 102 struct rb_entry *tmp; in rbe_rotate_left() local
104 tmp = RBE_RIGHT(rbe); in rbe_rotate_left()
105 RBE_RIGHT(rbe) = RBE_LEFT(tmp); in rbe_rotate_left()
107 RBE_PARENT(RBE_LEFT(tmp)) = rbe; in rbe_rotate_left()
110 RBE_PARENT(tmp) = parent; in rbe_rotate_left()
113 RBE_LEFT(parent) = tmp; in rbe_rotate_left()
115 RBE_RIGHT(parent) = tmp; in rbe_rotate_left()
117 RBH_ROOT(rbt) = tmp; in rbe_rotate_left()
119 RBE_LEFT(tmp) = rbe; in rbe_rotate_left()
120 RBE_PARENT(rbe) = tmp; in rbe_rotate_left()
[all …]
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